drivers/mmc/dw_mmc.c

   1 /*
   2  * (C) Copyright 2012 SAMSUNG Electronics
   3  * Jaehoon Chung <jh80.chung@samsung.com>
   4  * Rajeshawari Shinde <rajeshwari.s@samsung.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <bouncebuf.h>
  10 #include <common.h>
  11 #include <errno.h>
  12 #include <malloc.h>
  13 #include <memalign.h>
  14 #include <mmc.h>
  15 #include <dwmmc.h>
  16
  17 #define PAGE_SIZE 4096
  18
  19 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
  20 {
  21         unsigned long timeout = 1000;
  22         u32 ctrl;
  23
  24         dwmci_writel(host, DWMCI_CTRL, value);
  25
  26         while (timeout--) {
  27                 ctrl = dwmci_readl(host, DWMCI_CTRL);
  28                 if (!(ctrl & DWMCI_RESET_ALL))
  29                         return 1;
  30         }
  31         return 0;
  32 }
  33
  34 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
  35                 u32 desc0, u32 desc1, u32 desc2)
  36 {
  37         struct dwmci_idmac *desc = idmac;
  38
  39         desc->flags = desc0;
  40         desc->cnt = desc1;
  41         desc->addr = desc2;
  42         desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
  43 }
  44
  45 static void dwmci_prepare_data(struct dwmci_host *host,
  46                                struct mmc_data *data,
  47                                struct dwmci_idmac *cur_idmac,
  48                                void *bounce_buffer)
  49 {
  50         unsigned long ctrl;
  51         unsigned int i = 0, flags, cnt, blk_cnt;
  52         ulong data_start, data_end;
  53
  54
  55         blk_cnt = data->blocks;
  56
  57         dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
  58
  59         data_start = (ulong)cur_idmac;
  60         dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
  61
  62         do {
  63                 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
  64                 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
  65                 if (blk_cnt <= 8) {
  66                         flags |= DWMCI_IDMAC_LD;
  67                         cnt = data->blocksize * blk_cnt;
  68                 } else
  69                         cnt = data->blocksize * 8;
  70
  71                 dwmci_set_idma_desc(cur_idmac, flags, cnt,
  72                                     (ulong)bounce_buffer + (i * PAGE_SIZE));
  73
  74                 if (blk_cnt <= 8)
  75                         break;
  76                 blk_cnt -= 8;
  77                 cur_idmac++;
  78                 i++;
  79         } while(1);
  80
  81         data_end = (ulong)cur_idmac;
  82         flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
  83
  84         ctrl = dwmci_readl(host, DWMCI_CTRL);
  85         ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
  86         dwmci_writel(host, DWMCI_CTRL, ctrl);
  87
  88         ctrl = dwmci_readl(host, DWMCI_BMOD);
  89         ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
  90         dwmci_writel(host, DWMCI_BMOD, ctrl);
  91
  92         dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
  93         dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
  94 }
  95
  96 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
  97 {
  98         int ret = 0;
  99         u32 timeout = 240000;
 100         u32 mask, size, i, len = 0;
 101         u32 *buf = NULL;
 102         ulong start = get_timer(0);
 103         u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
 104                             RX_WMARK_SHIFT) + 1) * 2;
 105
 106         size = data->blocksize * data->blocks / 4;
 107         if (data->flags == MMC_DATA_READ)
 108                 buf = (unsigned int *)data->dest;
 109         else
 110                 buf = (unsigned int *)data->src;
 111
 112         for (;;) {
 113                 mask = dwmci_readl(host, DWMCI_RINTSTS);
 114                 /* Error during data transfer. */
 115                 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
 116                         debug("%s: DATA ERROR!\n", __func__);
 117                         ret = -EINVAL;
 118                         break;
 119                 }
 120
 121                 if (host->fifo_mode && size) {
 122                         if (data->flags == MMC_DATA_READ) {
 123                                 if ((dwmci_readl(host, DWMCI_RINTSTS) &
 124                                      DWMCI_INTMSK_RXDR)) {
 125                                         len = dwmci_readl(host, DWMCI_STATUS);
 126                                         len = (len >> DWMCI_FIFO_SHIFT) &
 127                                                     DWMCI_FIFO_MASK;
 128                                         len = min(size, len);
 129                                         for (i = 0; i < len; i++)
 130                                                 *buf++ =
 131                                                 dwmci_readl(host, DWMCI_DATA);
 132                                         dwmci_writel(host, DWMCI_RINTSTS,
 133                                                      DWMCI_INTMSK_RXDR);
 134                                 }
 135                         } else {
 136                                 if ((dwmci_readl(host, DWMCI_RINTSTS) &
 137                                      DWMCI_INTMSK_TXDR)) {
 138                                         len = dwmci_readl(host, DWMCI_STATUS);
 139                                         len = fifo_depth - ((len >>
 140                                                    DWMCI_FIFO_SHIFT) &
 141                                                    DWMCI_FIFO_MASK);
 142                                         len = min(size, len);
 143                                         for (i = 0; i < len; i++)
 144                                                 dwmci_writel(host, DWMCI_DATA,
 145                                                              *buf++);
 146                                         dwmci_writel(host, DWMCI_RINTSTS,
 147                                                      DWMCI_INTMSK_TXDR);
 148                                 }
 149                         }
 150                         size = size > len ? (size - len) : 0;
 151                 }
 152
 153                 /* Data arrived correctly. */
 154                 if (mask & DWMCI_INTMSK_DTO) {
 155                         ret = 0;
 156                         break;
 157                 }
 158
 159                 /* Check for timeout. */
 160                 if (get_timer(start) > timeout) {
 161                         debug("%s: Timeout waiting for data!\n",
 162                               __func__);
 163                         ret = -ETIMEDOUT;
 164                         break;
 165                 }
 166         }
 167
 168         dwmci_writel(host, DWMCI_RINTSTS, mask);
 169
 170         return ret;
 171 }
 172
 173 static int dwmci_set_transfer_mode(struct dwmci_host *host,
 174                 struct mmc_data *data)
 175 {
 176         unsigned long mode;
 177
 178         mode = DWMCI_CMD_DATA_EXP;
 179         if (data->flags & MMC_DATA_WRITE)
 180                 mode |= DWMCI_CMD_RW;
 181
 182         return mode;
 183 }
 184
 185 #ifdef CONFIG_DM_MMC_OPS
 186 static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 187                    struct mmc_data *data)
 188 {
 189         struct mmc *mmc = mmc_get_mmc_dev(dev);
 190 #else
 191 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 192                 struct mmc_data *data)
 193 {
 194 #endif
 195         struct dwmci_host *host = mmc->priv;
 196         ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
 197                                  data ? DIV_ROUND_UP(data->blocks, 8) : 0);
 198         int ret = 0, flags = 0, i;
 199         unsigned int timeout = 500;
 200         u32 retry = 100000;
 201         u32 mask, ctrl;
 202         ulong start = get_timer(0);
 203         struct bounce_buffer bbstate;
 204
 205         while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
 206                 if (get_timer(start) > timeout) {
 207                         debug("%s: Timeout on data busy\n", __func__);
 208                         return -ETIMEDOUT;
 209                 }
 210         }
 211
 212         dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
 213
 214         if (data) {
 215                 if (host->fifo_mode) {
 216                         dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
 217                         dwmci_writel(host, DWMCI_BYTCNT,
 218                                      data->blocksize * data->blocks);
 219                         dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
 220                 } else {
 221                         if (data->flags == MMC_DATA_READ) {
 222                                 bounce_buffer_start(&bbstate, (void*)data->dest,
 223                                                 data->blocksize *
 224                                                 data->blocks, GEN_BB_WRITE);
 225                         } else {
 226                                 bounce_buffer_start(&bbstate, (void*)data->src,
 227                                                 data->blocksize *
 228                                                 data->blocks, GEN_BB_READ);
 229                         }
 230                         dwmci_prepare_data(host, data, cur_idmac,
 231                                            bbstate.bounce_buffer);
 232                 }
 233         }
 234
 235         dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
 236
 237         if (data)
 238                 flags = dwmci_set_transfer_mode(host, data);
 239
 240         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 241                 return -1;
 242
 243         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 244                 flags |= DWMCI_CMD_ABORT_STOP;
 245         else
 246                 flags |= DWMCI_CMD_PRV_DAT_WAIT;
 247
 248         if (cmd->resp_type & MMC_RSP_PRESENT) {
 249                 flags |= DWMCI_CMD_RESP_EXP;
 250                 if (cmd->resp_type & MMC_RSP_136)
 251                         flags |= DWMCI_CMD_RESP_LENGTH;
 252         }
 253
 254         if (cmd->resp_type & MMC_RSP_CRC)
 255                 flags |= DWMCI_CMD_CHECK_CRC;
 256
 257         flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
 258
 259         debug("Sending CMD%d\n",cmd->cmdidx);
 260
 261         dwmci_writel(host, DWMCI_CMD, flags);
 262
 263         for (i = 0; i < retry; i++) {
 264                 mask = dwmci_readl(host, DWMCI_RINTSTS);
 265                 if (mask & DWMCI_INTMSK_CDONE) {
 266                         if (!data)
 267                                 dwmci_writel(host, DWMCI_RINTSTS, mask);
 268                         break;
 269                 }
 270         }
 271
 272         if (i == retry) {
 273                 debug("%s: Timeout.\n", __func__);
 274                 return -ETIMEDOUT;
 275         }
 276
 277         if (mask & DWMCI_INTMSK_RTO) {
 278                 /*
 279                  * Timeout here is not necessarily fatal. (e)MMC cards
 280                  * will splat here when they receive CMD55 as they do
 281                  * not support this command and that is exactly the way
 282                  * to tell them apart from SD cards. Thus, this output
 283                  * below shall be debug(). eMMC cards also do not favor
 284                  * CMD8, please keep that in mind.
 285                  */
 286                 debug("%s: Response Timeout.\n", __func__);
 287                 return -ETIMEDOUT;
 288         } else if (mask & DWMCI_INTMSK_RE) {
 289                 debug("%s: Response Error.\n", __func__);
 290                 return -EIO;
 291         }
 292
 293
 294         if (cmd->resp_type & MMC_RSP_PRESENT) {
 295                 if (cmd->resp_type & MMC_RSP_136) {
 296                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
 297                         cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
 298                         cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
 299                         cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
 300                 } else {
 301                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
 302                 }
 303         }
 304
 305         if (data) {
 306                 ret = dwmci_data_transfer(host, data);
 307
 308                 /* only dma mode need it */
 309                 if (!host->fifo_mode) {
 310                         ctrl = dwmci_readl(host, DWMCI_CTRL);
 311                         ctrl &= ~(DWMCI_DMA_EN);
 312                         dwmci_writel(host, DWMCI_CTRL, ctrl);
 313                         bounce_buffer_stop(&bbstate);
 314                 }
 315         }
 316
 317         udelay(100);
 318
 319         return ret;
 320 }
 321
 322 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 323 {
 324         u32 div, status;
 325         int timeout = 10000;
 326         unsigned long sclk;
 327
 328         if ((freq == host->clock) || (freq == 0))
 329                 return 0;
 330         /*
 331          * If host->get_mmc_clk isn't defined,
 332          * then assume that host->bus_hz is source clock value.
 333          * host->bus_hz should be set by user.
 334          */
 335         if (host->get_mmc_clk)
 336                 sclk = host->get_mmc_clk(host, freq);
 337         else if (host->bus_hz)
 338                 sclk = host->bus_hz;
 339         else {
 340                 debug("%s: Didn't get source clock value.\n", __func__);
 341                 return -EINVAL;
 342         }
 343
 344         if (sclk == freq)
 345                 div = 0;        /* bypass mode */
 346         else
 347                 div = DIV_ROUND_UP(sclk, 2 * freq);
 348
 349         dwmci_writel(host, DWMCI_CLKENA, 0);
 350         dwmci_writel(host, DWMCI_CLKSRC, 0);
 351
 352         dwmci_writel(host, DWMCI_CLKDIV, div);
 353         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 354                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 355
 356         do {
 357                 status = dwmci_readl(host, DWMCI_CMD);
 358                 if (timeout-- < 0) {
 359                         debug("%s: Timeout!\n", __func__);
 360                         return -ETIMEDOUT;
 361                 }
 362         } while (status & DWMCI_CMD_START);
 363
 364         dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
 365                         DWMCI_CLKEN_LOW_PWR);
 366
 367         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 368                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 369
 370         timeout = 10000;
 371         do {
 372                 status = dwmci_readl(host, DWMCI_CMD);
 373                 if (timeout-- < 0) {
 374                         debug("%s: Timeout!\n", __func__);
 375                         return -ETIMEDOUT;
 376                 }
 377         } while (status & DWMCI_CMD_START);
 378
 379         host->clock = freq;
 380
 381         return 0;
 382 }
 383
 384 #ifdef CONFIG_DM_MMC_OPS
 385 static int dwmci_set_ios(struct udevice *dev)
 386 {
 387         struct mmc *mmc = mmc_get_mmc_dev(dev);
 388 #else
 389 static void dwmci_set_ios(struct mmc *mmc)
 390 {
 391 #endif
 392         struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
 393         u32 ctype, regs;
 394
 395         debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
 396
 397         dwmci_setup_bus(host, mmc->clock);
 398         switch (mmc->bus_width) {
 399         case 8:
 400                 ctype = DWMCI_CTYPE_8BIT;
 401                 break;
 402         case 4:
 403                 ctype = DWMCI_CTYPE_4BIT;
 404                 break;
 405         default:
 406                 ctype = DWMCI_CTYPE_1BIT;
 407                 break;
 408         }
 409
 410         dwmci_writel(host, DWMCI_CTYPE, ctype);
 411
 412         regs = dwmci_readl(host, DWMCI_UHS_REG);
 413         if (mmc->ddr_mode)
 414                 regs |= DWMCI_DDR_MODE;
 415         else
 416                 regs &= ~DWMCI_DDR_MODE;
 417
 418         dwmci_writel(host, DWMCI_UHS_REG, regs);
 419
 420         if (host->clksel)
 421                 host->clksel(host);
 422 #ifdef CONFIG_DM_MMC_OPS
 423         return 0;
 424 #endif
 425 }
 426
 427 static int dwmci_init(struct mmc *mmc)
 428 {
 429         struct dwmci_host *host = mmc->priv;
 430
 431         if (host->board_init)
 432                 host->board_init(host);
 433
 434         dwmci_writel(host, DWMCI_PWREN, 1);
 435
 436         if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
 437                 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
 438                 return -EIO;
 439         }
 440
 441         /* Enumerate at 400KHz */
 442         dwmci_setup_bus(host, mmc->cfg->f_min);
 443
 444         dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
 445         dwmci_writel(host, DWMCI_INTMASK, 0);
 446
 447         dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
 448
 449         dwmci_writel(host, DWMCI_IDINTEN, 0);
 450         dwmci_writel(host, DWMCI_BMOD, 1);
 451
 452         if (!host->fifoth_val) {
 453                 uint32_t fifo_size;
 454
 455                 fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
 456                 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
 457                 host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
 458                                 TX_WMARK(fifo_size / 2);
 459         }
 460         dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
 461
 462         dwmci_writel(host, DWMCI_CLKENA, 0);
 463         dwmci_writel(host, DWMCI_CLKSRC, 0);
 464
 465         return 0;
 466 }
 467
 468 #ifdef CONFIG_DM_MMC_OPS
 469 int dwmci_probe(struct udevice *dev)
 470 {
 471         struct mmc *mmc = mmc_get_mmc_dev(dev);
 472
 473         return dwmci_init(mmc);
 474 }
 475
 476 const struct dm_mmc_ops dm_dwmci_ops = {
 477         .send_cmd       = dwmci_send_cmd,
 478         .set_ios        = dwmci_set_ios,
 479 };
 480
 481 #else
 482 static const struct mmc_ops dwmci_ops = {
 483         .send_cmd       = dwmci_send_cmd,
 484         .set_ios        = dwmci_set_ios,
 485         .init           = dwmci_init,
 486 };
 487 #endif
 488
 489 void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
 490                      uint caps, u32 max_clk, u32 min_clk)
 491 {
 492         cfg->name = name;
 493 #ifndef CONFIG_DM_MMC_OPS
 494         cfg->ops = &dwmci_ops;
 495 #endif
 496         cfg->f_min = min_clk;
 497         cfg->f_max = max_clk;
 498
 499         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 500
 501         cfg->host_caps = caps;
 502
 503         if (buswidth == 8) {
 504                 cfg->host_caps |= MMC_MODE_8BIT;
 505                 cfg->host_caps &= ~MMC_MODE_4BIT;
 506         } else {
 507                 cfg->host_caps |= MMC_MODE_4BIT;
 508                 cfg->host_caps &= ~MMC_MODE_8BIT;
 509         }
 510         cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
 511
 512         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 513 }
 514
 515 #ifdef CONFIG_BLK
 516 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 517 {
 518         return mmc_bind(dev, mmc, cfg);
 519 }
 520 #else
 521 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
 522 {
 523         dwmci_setup_cfg(&host->cfg, host->name, host->buswidth, host->caps,
 524                         max_clk, min_clk);
 525
 526         host->mmc = mmc_create(&host->cfg, host);
 527         if (host->mmc == NULL)
 528                 return -1;
 529
 530         return 0;
 531 }
 532 #endif