1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012 SAMSUNG Electronics
4 * Jaehoon Chung <jh80.chung@samsung.com>
5 * Rajeshawari Shinde <rajeshwari.s@samsung.com>
16 #include <power/regulator.h>
18 #define PAGE_SIZE 4096
20 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
22 unsigned long timeout = 1000;
25 dwmci_writel(host, DWMCI_CTRL, value);
28 ctrl = dwmci_readl(host, DWMCI_CTRL);
29 if (!(ctrl & DWMCI_RESET_ALL))
35 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
36 u32 desc0, u32 desc1, u32 desc2)
38 struct dwmci_idmac *desc = idmac;
43 desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
46 static void dwmci_prepare_data(struct dwmci_host *host,
47 struct mmc_data *data,
48 struct dwmci_idmac *cur_idmac,
52 unsigned int i = 0, flags, cnt, blk_cnt;
53 ulong data_start, data_end;
56 blk_cnt = data->blocks;
58 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
60 /* Clear IDMAC interrupt */
61 dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF);
63 data_start = (ulong)cur_idmac;
64 dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
67 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
68 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
70 flags |= DWMCI_IDMAC_LD;
71 cnt = data->blocksize * blk_cnt;
73 cnt = data->blocksize * 8;
75 dwmci_set_idma_desc(cur_idmac, flags, cnt,
76 (ulong)bounce_buffer + (i * PAGE_SIZE));
85 data_end = (ulong)cur_idmac;
86 flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN));
88 ctrl = dwmci_readl(host, DWMCI_CTRL);
89 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
90 dwmci_writel(host, DWMCI_CTRL, ctrl);
92 ctrl = dwmci_readl(host, DWMCI_BMOD);
93 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
94 dwmci_writel(host, DWMCI_BMOD, ctrl);
96 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
97 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
100 static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len)
104 *len = dwmci_readl(host, DWMCI_STATUS);
105 while (--timeout && (*len & bit)) {
107 *len = dwmci_readl(host, DWMCI_STATUS);
111 debug("%s: FIFO underflow timeout\n", __func__);
118 static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size)
120 unsigned int timeout;
122 timeout = size * 8; /* counting in bits */
123 timeout *= 10; /* wait 10 times as long */
124 timeout /= mmc->clock;
125 timeout /= mmc->bus_width;
126 timeout /= mmc->ddr_mode ? 2 : 1;
127 timeout *= 1000; /* counting in msec */
128 timeout = (timeout < 1000) ? 1000 : timeout;
133 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
135 struct mmc *mmc = host->mmc;
137 u32 timeout, mask, size, i, len = 0;
139 ulong start = get_timer(0);
140 u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
141 RX_WMARK_SHIFT) + 1) * 2;
143 size = data->blocksize * data->blocks;
144 if (data->flags == MMC_DATA_READ)
145 buf = (unsigned int *)data->dest;
147 buf = (unsigned int *)data->src;
149 timeout = dwmci_get_timeout(mmc, size);
154 mask = dwmci_readl(host, DWMCI_RINTSTS);
155 /* Error during data transfer. */
156 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
157 debug("%s: DATA ERROR!\n", __func__);
162 if (host->fifo_mode && size) {
164 if (data->flags == MMC_DATA_READ &&
165 (mask & DWMCI_INTMSK_RXDR)) {
167 ret = dwmci_fifo_ready(host,
173 len = (len >> DWMCI_FIFO_SHIFT) &
175 len = min(size, len);
176 for (i = 0; i < len; i++)
178 dwmci_readl(host, DWMCI_DATA);
179 size = size > len ? (size - len) : 0;
181 dwmci_writel(host, DWMCI_RINTSTS,
183 } else if (data->flags == MMC_DATA_WRITE &&
184 (mask & DWMCI_INTMSK_TXDR)) {
186 ret = dwmci_fifo_ready(host,
192 len = fifo_depth - ((len >>
195 len = min(size, len);
196 for (i = 0; i < len; i++)
197 dwmci_writel(host, DWMCI_DATA,
199 size = size > len ? (size - len) : 0;
201 dwmci_writel(host, DWMCI_RINTSTS,
206 /* Data arrived correctly. */
207 if (mask & DWMCI_INTMSK_DTO) {
212 /* Check for timeout. */
213 if (get_timer(start) > timeout) {
214 debug("%s: Timeout waiting for data!\n",
221 dwmci_writel(host, DWMCI_RINTSTS, mask);
226 static int dwmci_set_transfer_mode(struct dwmci_host *host,
227 struct mmc_data *data)
231 mode = DWMCI_CMD_DATA_EXP;
232 if (data->flags & MMC_DATA_WRITE)
233 mode |= DWMCI_CMD_RW;
239 static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
240 struct mmc_data *data)
242 struct mmc *mmc = mmc_get_mmc_dev(dev);
244 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
245 struct mmc_data *data)
248 struct dwmci_host *host = mmc->priv;
249 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
250 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
251 int ret = 0, flags = 0, i;
252 unsigned int timeout = 500;
255 ulong start = get_timer(0);
256 struct bounce_buffer bbstate;
258 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
259 if (get_timer(start) > timeout) {
260 debug("%s: Timeout on data busy\n", __func__);
265 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
268 if (host->fifo_mode) {
269 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
270 dwmci_writel(host, DWMCI_BYTCNT,
271 data->blocksize * data->blocks);
272 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
274 if (data->flags == MMC_DATA_READ) {
275 ret = bounce_buffer_start(&bbstate,
278 data->blocks, GEN_BB_WRITE);
280 ret = bounce_buffer_start(&bbstate,
283 data->blocks, GEN_BB_READ);
289 dwmci_prepare_data(host, data, cur_idmac,
290 bbstate.bounce_buffer);
294 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
297 flags = dwmci_set_transfer_mode(host, data);
299 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
302 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
303 flags |= DWMCI_CMD_ABORT_STOP;
305 flags |= DWMCI_CMD_PRV_DAT_WAIT;
307 if (cmd->resp_type & MMC_RSP_PRESENT) {
308 flags |= DWMCI_CMD_RESP_EXP;
309 if (cmd->resp_type & MMC_RSP_136)
310 flags |= DWMCI_CMD_RESP_LENGTH;
313 if (cmd->resp_type & MMC_RSP_CRC)
314 flags |= DWMCI_CMD_CHECK_CRC;
316 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
318 debug("Sending CMD%d\n",cmd->cmdidx);
320 dwmci_writel(host, DWMCI_CMD, flags);
322 for (i = 0; i < retry; i++) {
323 mask = dwmci_readl(host, DWMCI_RINTSTS);
324 if (mask & DWMCI_INTMSK_CDONE) {
326 dwmci_writel(host, DWMCI_RINTSTS, mask);
332 debug("%s: Timeout.\n", __func__);
336 if (mask & DWMCI_INTMSK_RTO) {
338 * Timeout here is not necessarily fatal. (e)MMC cards
339 * will splat here when they receive CMD55 as they do
340 * not support this command and that is exactly the way
341 * to tell them apart from SD cards. Thus, this output
342 * below shall be debug(). eMMC cards also do not favor
343 * CMD8, please keep that in mind.
345 debug("%s: Response Timeout.\n", __func__);
347 } else if (mask & DWMCI_INTMSK_RE) {
348 debug("%s: Response Error.\n", __func__);
350 } else if ((cmd->resp_type & MMC_RSP_CRC) &&
351 (mask & DWMCI_INTMSK_RCRC)) {
352 debug("%s: Response CRC Error.\n", __func__);
357 if (cmd->resp_type & MMC_RSP_PRESENT) {
358 if (cmd->resp_type & MMC_RSP_136) {
359 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
360 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
361 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
362 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
364 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
369 ret = dwmci_data_transfer(host, data);
371 /* only dma mode need it */
372 if (!host->fifo_mode) {
373 if (data->flags == MMC_DATA_READ)
374 mask = DWMCI_IDINTEN_RI;
376 mask = DWMCI_IDINTEN_TI;
377 ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS,
378 mask, true, 1000, false);
380 debug("%s: DWMCI_IDINTEN mask 0x%x timeout.\n",
382 /* clear interrupts */
383 dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK);
385 ctrl = dwmci_readl(host, DWMCI_CTRL);
386 ctrl &= ~(DWMCI_DMA_EN);
387 dwmci_writel(host, DWMCI_CTRL, ctrl);
388 bounce_buffer_stop(&bbstate);
397 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
403 if ((freq == host->clock) || (freq == 0))
406 * If host->get_mmc_clk isn't defined,
407 * then assume that host->bus_hz is source clock value.
408 * host->bus_hz should be set by user.
410 if (host->get_mmc_clk)
411 sclk = host->get_mmc_clk(host, freq);
412 else if (host->bus_hz)
415 debug("%s: Didn't get source clock value.\n", __func__);
420 div = 0; /* bypass mode */
422 div = DIV_ROUND_UP(sclk, 2 * freq);
424 dwmci_writel(host, DWMCI_CLKENA, 0);
425 dwmci_writel(host, DWMCI_CLKSRC, 0);
427 dwmci_writel(host, DWMCI_CLKDIV, div);
428 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
429 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
432 status = dwmci_readl(host, DWMCI_CMD);
434 debug("%s: Timeout!\n", __func__);
437 } while (status & DWMCI_CMD_START);
439 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
440 DWMCI_CLKEN_LOW_PWR);
442 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
443 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
447 status = dwmci_readl(host, DWMCI_CMD);
449 debug("%s: Timeout!\n", __func__);
452 } while (status & DWMCI_CMD_START);
460 static int dwmci_set_ios(struct udevice *dev)
462 struct mmc *mmc = mmc_get_mmc_dev(dev);
464 static int dwmci_set_ios(struct mmc *mmc)
467 struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
470 debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
472 dwmci_setup_bus(host, mmc->clock);
473 switch (mmc->bus_width) {
475 ctype = DWMCI_CTYPE_8BIT;
478 ctype = DWMCI_CTYPE_4BIT;
481 ctype = DWMCI_CTYPE_1BIT;
485 dwmci_writel(host, DWMCI_CTYPE, ctype);
487 regs = dwmci_readl(host, DWMCI_UHS_REG);
489 regs |= DWMCI_DDR_MODE;
491 regs &= ~DWMCI_DDR_MODE;
493 dwmci_writel(host, DWMCI_UHS_REG, regs);
498 #if CONFIG_IS_ENABLED(DM_REGULATOR)
499 if (mmc->vqmmc_supply) {
502 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
503 regulator_set_value(mmc->vqmmc_supply, 1800000);
505 regulator_set_value(mmc->vqmmc_supply, 3300000);
507 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
516 static int dwmci_init(struct mmc *mmc)
518 struct dwmci_host *host = mmc->priv;
520 if (host->board_init)
521 host->board_init(host);
523 dwmci_writel(host, DWMCI_PWREN, 1);
525 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
526 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
530 /* Enumerate at 400KHz */
531 dwmci_setup_bus(host, mmc->cfg->f_min);
533 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
534 dwmci_writel(host, DWMCI_INTMASK, 0);
536 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
538 dwmci_writel(host, DWMCI_IDINTEN, 0);
539 dwmci_writel(host, DWMCI_BMOD, 1);
541 if (!host->fifoth_val) {
544 fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
545 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
546 host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
547 TX_WMARK(fifo_size / 2);
549 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
551 dwmci_writel(host, DWMCI_CLKENA, 0);
552 dwmci_writel(host, DWMCI_CLKSRC, 0);
554 if (!host->fifo_mode)
555 dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK);
561 int dwmci_probe(struct udevice *dev)
563 struct mmc *mmc = mmc_get_mmc_dev(dev);
565 return dwmci_init(mmc);
568 const struct dm_mmc_ops dm_dwmci_ops = {
569 .send_cmd = dwmci_send_cmd,
570 .set_ios = dwmci_set_ios,
574 static const struct mmc_ops dwmci_ops = {
575 .send_cmd = dwmci_send_cmd,
576 .set_ios = dwmci_set_ios,
581 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
582 u32 max_clk, u32 min_clk)
584 cfg->name = host->name;
585 #ifndef CONFIG_DM_MMC
586 cfg->ops = &dwmci_ops;
588 cfg->f_min = min_clk;
589 cfg->f_max = max_clk;
591 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
593 cfg->host_caps = host->caps;
595 if (host->buswidth == 8) {
596 cfg->host_caps |= MMC_MODE_8BIT;
597 cfg->host_caps &= ~MMC_MODE_4BIT;
599 cfg->host_caps |= MMC_MODE_4BIT;
600 cfg->host_caps &= ~MMC_MODE_8BIT;
602 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
604 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
608 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
610 return mmc_bind(dev, mmc, cfg);
613 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
615 dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
617 host->mmc = mmc_create(&host->cfg, host);
618 if (host->mmc == NULL)