1 // SPDX-License-Identifier: GPL-2.0+
3 * Davinci MMC Controller Driver
5 * Copyright (C) 2010 Texas Instruments Incorporated
17 #include <asm/arch/sdmmc_defs.h>
18 #include <asm-generic/gpio.h>
20 #define DAVINCI_MAX_BLOCKS (32)
21 #define WATCHDOG_COUNT (100000)
23 #define get_val(addr) REG(addr)
24 #define set_val(addr, val) REG(addr) = (val)
25 #define set_bit(addr, val) set_val((addr), (get_val(addr) | (val)))
26 #define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val)))
29 /* Davinci MMC board definitions */
30 struct davinci_mmc_priv {
31 struct davinci_mmc_regs *reg_base; /* Register base address */
32 uint input_clk; /* Input clock to MMC controller */
33 struct gpio_desc cd_gpio; /* Card Detect GPIO */
34 struct gpio_desc wp_gpio; /* Write Protect GPIO */
35 struct mmc_config cfg;
40 /* Set davinci clock prescalar value based on the required clock in HZ */
41 #if !CONFIG_IS_ENABLED(DM_MMC)
42 static void dmmc_set_clock(struct mmc *mmc, uint clock)
44 struct davinci_mmc *host = mmc->priv;
47 static void davinci_mmc_set_clock(struct udevice *dev, uint clock)
49 struct davinci_mmc_priv *host = dev_get_priv(dev);
50 struct mmc *mmc = mmc_get_mmc_dev(dev);
52 struct davinci_mmc_regs *regs = host->reg_base;
53 uint clkrt, sysclk2, act_clock;
55 if (clock < mmc->cfg->f_min)
56 clock = mmc->cfg->f_min;
57 if (clock > mmc->cfg->f_max)
58 clock = mmc->cfg->f_max;
60 set_val(®s->mmcclk, 0);
61 sysclk2 = host->input_clk;
62 clkrt = (sysclk2 / (2 * clock)) - 1;
64 /* Calculate the actual clock for the divider used */
65 act_clock = (sysclk2 / (2 * (clkrt + 1)));
67 /* Adjust divider if actual clock exceeds the required clock */
68 if (act_clock > clock)
71 /* check clock divider boundary and correct it */
75 set_val(®s->mmcclk, (clkrt | MMCCLK_CLKEN));
78 /* Status bit wait loop for MMCST1 */
80 dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status)
82 uint wdog = WATCHDOG_COUNT;
84 while (--wdog && ((get_val(®s->mmcst1) & status) != status))
87 if (!(get_val(®s->mmcctl) & MMCCTL_WIDTH_4_BIT))
96 /* Busy bit wait loop for MMCST1 */
97 static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs)
99 uint wdog = WATCHDOG_COUNT;
101 while (--wdog && (get_val(®s->mmcst1) & MMCST1_BUSY))
110 /* Status bit wait loop for MMCST0 - Checks for error bits as well */
111 static int dmmc_check_status(volatile struct davinci_mmc_regs *regs,
112 uint *cur_st, uint st_ready, uint st_error)
114 uint wdog = WATCHDOG_COUNT;
115 uint mmcstatus = *cur_st;
118 if (mmcstatus & st_ready) {
120 mmcstatus = get_val(®s->mmcst1);
122 } else if (mmcstatus & st_error) {
123 if (mmcstatus & MMCST0_TOUTRS)
125 printf("[ ST0 ERROR %x]\n", mmcstatus);
127 * Ignore CRC errors as some MMC cards fail to
128 * initialize on DM365-EVM on the SD1 slot
130 if (mmcstatus & MMCST0_CRCRS)
136 mmcstatus = get_val(®s->mmcst0);
139 printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus,
140 get_val(®s->mmcst1));
145 * Sends a command out on the bus. Takes the device pointer,
146 * a command pointer, and an optional data pointer.
148 #if !CONFIG_IS_ENABLED(DM_MMC)
149 static int dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
151 struct davinci_mmc *host = mmc->priv;
154 davinci_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
156 struct davinci_mmc_priv *host = dev_get_priv(dev);
158 volatile struct davinci_mmc_regs *regs = host->reg_base;
159 uint mmcstatus, status_rdy, status_err;
160 uint i, cmddata, bytes_left = 0;
161 int fifo_words, fifo_bytes, err;
162 char *data_buf = NULL;
164 /* Clear status registers */
165 mmcstatus = get_val(®s->mmcst0);
167 fifo_bytes = fifo_words << 2;
169 /* Wait for any previous busy signal to be cleared */
170 dmmc_busy_wait(regs);
172 cmddata = cmd->cmdidx;
173 cmddata |= MMCCMD_PPLEN;
175 /* Send init clock for CMD0 */
176 if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE)
177 cmddata |= MMCCMD_INITCK;
179 switch (cmd->resp_type) {
181 cmddata |= MMCCMD_BSYEXP;
183 case MMC_RSP_R1: /* R1, R1b, R5, R6, R7 */
184 cmddata |= MMCCMD_RSPFMT_R1567;
187 cmddata |= MMCCMD_RSPFMT_R2;
189 case MMC_RSP_R3: /* R3, R4 */
190 cmddata |= MMCCMD_RSPFMT_R3;
194 set_val(®s->mmcim, 0);
197 /* clear previous data transfer if any and set new one */
198 bytes_left = (data->blocksize * data->blocks);
200 /* Reset FIFO - Always use 32 byte fifo threshold */
201 set_val(®s->mmcfifoctl,
202 (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
204 cmddata |= MMCCMD_DMATRIG;
206 cmddata |= MMCCMD_WDATX;
207 if (data->flags == MMC_DATA_READ) {
208 set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
209 } else if (data->flags == MMC_DATA_WRITE) {
210 set_val(®s->mmcfifoctl,
211 (MMCFIFOCTL_FIFOLEV |
212 MMCFIFOCTL_FIFODIR));
213 cmddata |= MMCCMD_DTRW;
216 set_val(®s->mmctod, 0xFFFF);
217 set_val(®s->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK));
218 set_val(®s->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK));
220 if (data->flags == MMC_DATA_WRITE) {
222 data_buf = (char *)data->src;
223 /* For write, fill FIFO with data before issue of CMD */
224 for (i = 0; (i < fifo_words) && bytes_left; i++) {
225 memcpy((char *)&val, data_buf, 4);
226 set_val(®s->mmcdxr, val);
232 set_val(®s->mmcblen, 0);
233 set_val(®s->mmcnblk, 0);
236 set_val(®s->mmctor, 0x1FFF);
238 /* Send the command */
239 set_val(®s->mmcarghl, cmd->cmdarg);
240 set_val(®s->mmccmd, cmddata);
242 status_rdy = MMCST0_RSPDNE;
243 status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD |
244 MMCST0_CRCWR | MMCST0_CRCRD);
245 if (cmd->resp_type & MMC_RSP_CRC)
246 status_err |= MMCST0_CRCRS;
248 mmcstatus = get_val(®s->mmcst0);
249 err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err);
253 /* For R1b wait for busy done */
254 if (cmd->resp_type == MMC_RSP_R1b)
255 dmmc_busy_wait(regs);
257 /* Collect response from controller for specific commands */
258 if (mmcstatus & MMCST0_RSPDNE) {
259 /* Copy the response to the response buffer */
260 if (cmd->resp_type & MMC_RSP_136) {
261 cmd->response[0] = get_val(®s->mmcrsp67);
262 cmd->response[1] = get_val(®s->mmcrsp45);
263 cmd->response[2] = get_val(®s->mmcrsp23);
264 cmd->response[3] = get_val(®s->mmcrsp01);
265 } else if (cmd->resp_type & MMC_RSP_PRESENT) {
266 cmd->response[0] = get_val(®s->mmcrsp67);
273 if (data->flags == MMC_DATA_READ) {
274 /* check for DATDNE along with DRRDY as the controller might
275 * set the DATDNE without DRRDY for smaller transfers with
276 * less than FIFO threshold bytes
278 status_rdy = MMCST0_DRRDY | MMCST0_DATDNE;
279 status_err = MMCST0_TOUTRD | MMCST0_CRCRD;
280 data_buf = data->dest;
282 status_rdy = MMCST0_DXRDY | MMCST0_DATDNE;
283 status_err = MMCST0_CRCWR;
286 /* Wait until all of the blocks are transferred */
288 err = dmmc_check_status(regs, &mmcstatus, status_rdy,
293 if (data->flags == MMC_DATA_READ) {
295 * MMC controller sets the Data receive ready bit
296 * (DRRDY) in MMCST0 even before the entire FIFO is
297 * full. This results in erratic behavior if we start
298 * reading the FIFO soon after DRRDY. Wait for the
299 * FIFO full bit in MMCST1 for proper FIFO clearing.
301 if (bytes_left > fifo_bytes)
302 dmmc_wait_fifo_status(regs, 0x4a);
303 else if (bytes_left == fifo_bytes) {
304 dmmc_wait_fifo_status(regs, 0x40);
305 if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD)
309 for (i = 0; bytes_left && (i < fifo_words); i++) {
310 cmddata = get_val(®s->mmcdrr);
311 memcpy(data_buf, (char *)&cmddata, 4);
317 * MMC controller sets the Data transmit ready bit
318 * (DXRDY) in MMCST0 even before the entire FIFO is
319 * empty. This results in erratic behavior if we start
320 * writing the FIFO soon after DXRDY. Wait for the
321 * FIFO empty bit in MMCST1 for proper FIFO clearing.
323 dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP);
324 for (i = 0; bytes_left && (i < fifo_words); i++) {
325 memcpy((char *)&cmddata, data_buf, 4);
326 set_val(®s->mmcdxr, cmddata);
330 dmmc_busy_wait(regs);
334 err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err);
341 /* Initialize Davinci MMC controller */
342 #if !CONFIG_IS_ENABLED(DM_MMC)
343 static int dmmc_init(struct mmc *mmc)
345 struct davinci_mmc *host = mmc->priv;
347 static int davinci_dm_mmc_init(struct udevice *dev)
349 struct davinci_mmc_priv *host = dev_get_priv(dev);
351 struct davinci_mmc_regs *regs = host->reg_base;
353 /* Clear status registers explicitly - soft reset doesn't clear it
354 * If Uboot is invoked from UBL with SDMMC Support, the status
355 * registers can have uncleared bits
357 get_val(®s->mmcst0);
358 get_val(®s->mmcst1);
360 /* Hold software reset */
361 set_bit(®s->mmcctl, MMCCTL_DATRST);
362 set_bit(®s->mmcctl, MMCCTL_CMDRST);
365 set_val(®s->mmcclk, 0x0);
366 set_val(®s->mmctor, 0x1FFF);
367 set_val(®s->mmctod, 0xFFFF);
369 /* Clear software reset */
370 clear_bit(®s->mmcctl, MMCCTL_DATRST);
371 clear_bit(®s->mmcctl, MMCCTL_CMDRST);
375 /* Reset FIFO - Always use the maximum fifo threshold */
376 set_val(®s->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
377 set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
382 /* Set buswidth or clock as indicated by the MMC framework */
383 #if !CONFIG_IS_ENABLED(DM_MMC)
384 static int dmmc_set_ios(struct mmc *mmc)
386 struct davinci_mmc *host = mmc->priv;
387 struct davinci_mmc_regs *regs = host->reg_base;
389 static int davinci_mmc_set_ios(struct udevice *dev)
391 struct mmc *mmc = mmc_get_mmc_dev(dev);
393 struct davinci_mmc_priv *host = dev_get_priv(dev);
394 struct davinci_mmc_regs *regs = host->reg_base;
396 /* Set the bus width */
397 if (mmc->bus_width == 4)
398 set_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
400 clear_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
402 /* Set clock speed */
404 #if !CONFIG_IS_ENABLED(DM_MMC)
405 dmmc_set_clock(mmc, mmc->clock);
407 davinci_mmc_set_clock(dev, mmc->clock);
413 #if !CONFIG_IS_ENABLED(DM_MMC)
414 static const struct mmc_ops dmmc_ops = {
415 .send_cmd = dmmc_send_cmd,
416 .set_ios = dmmc_set_ios,
421 static int davinci_mmc_getcd(struct udevice *dev)
424 #if CONFIG_IS_ENABLED(DM_GPIO)
425 struct davinci_mmc_priv *priv = dev_get_priv(dev);
426 value = dm_gpio_get_value(&priv->cd_gpio);
428 /* if no CD return as 1 */
435 static int davinci_mmc_getwp(struct udevice *dev)
438 #if CONFIG_IS_ENABLED(DM_GPIO)
439 struct davinci_mmc_priv *priv = dev_get_priv(dev);
441 value = dm_gpio_get_value(&priv->wp_gpio);
443 /* if no WP return as 0 */
450 static const struct dm_mmc_ops davinci_mmc_ops = {
451 .send_cmd = davinci_mmc_send_cmd,
452 .set_ios = davinci_mmc_set_ios,
453 .get_cd = davinci_mmc_getcd,
454 .get_wp = davinci_mmc_getwp,
458 #if !CONFIG_IS_ENABLED(DM_MMC)
459 /* Called from board_mmc_init during startup. Can be called multiple times
460 * depending on the number of slots available on board and controller
462 int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
464 host->cfg.name = "davinci";
465 host->cfg.ops = &dmmc_ops;
466 host->cfg.f_min = 200000;
467 host->cfg.f_max = 25000000;
468 host->cfg.voltages = host->voltages;
469 host->cfg.host_caps = host->host_caps;
471 host->cfg.b_max = DAVINCI_MAX_BLOCKS;
473 mmc_create(&host->cfg, host);
480 static int davinci_mmc_probe(struct udevice *dev)
482 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
483 struct davinci_mmc_priv *priv = dev_get_priv(dev);
484 struct mmc_config *cfg = &priv->cfg;
485 #ifdef CONFIG_SPL_BUILD
490 cfg->f_max = 25000000;
491 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
492 cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
493 cfg->b_max = DAVINCI_MAX_BLOCKS;
494 cfg->name = "da830-mmc";
496 priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
497 priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);
499 #if CONFIG_IS_ENABLED(DM_GPIO)
500 /* These GPIOs are optional */
501 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
502 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
505 upriv->mmc = &priv->mmc;
507 #ifdef CONFIG_SPL_BUILD
509 * FIXME This is a temporary workaround to enable the driver model in
510 * SPL on omapl138-lcdk. For some reason the bind() callback is not
511 * being called in SPL for MMC which breaks the mmc boot - the hack
512 * is to call mmc_bind() from probe(). We also don't have full DT
513 * support in SPL, hence the hard-coded base register address.
515 priv->reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE;
516 ret = mmc_bind(dev, &priv->mmc, &priv->cfg);
521 return davinci_dm_mmc_init(dev);
524 static int davinci_mmc_bind(struct udevice *dev)
526 struct davinci_mmc_priv *priv = dev_get_priv(dev);
528 return mmc_bind(dev, &priv->mmc, &priv->cfg);
531 static const struct udevice_id davinci_mmc_ids[] = {
532 { .compatible = "ti,da830-mmc" },
536 U_BOOT_DRIVER(davinci_mmc_drv) = {
537 .name = "davinci_mmc",
539 .of_match = davinci_mmc_ids,
541 .bind = davinci_mmc_bind,
543 .probe = davinci_mmc_probe,
544 .ops = &davinci_mmc_ops,
545 .priv_auto_alloc_size = sizeof(struct davinci_mmc_priv),