1 // SPDX-License-Identifier: GPL-2.0
3 * bcm2835 sdhost driver.
5 * The 2835 has two SD controllers: The Arasan sdhci controller
6 * (supported by the iproc driver) and a custom sdhost controller
7 * (supported by this driver).
9 * The sdhci controller supports both sdcard and sdio. The sdhost
10 * controller supports the sdcard only, but has better performance.
11 * Also note that the rpi3 has sdio wifi, so driving the sdcard with
12 * the sdhost controller allows to use the sdhci controller for wifi
15 * The configuration is done by devicetree via pin muxing. Both
16 * SD controller are available on the same pins (2 pin groups = pin 22
17 * to 27 + pin 48 to 53). So it's possible to use both SD controllers
18 * at the same time with different pin groups.
20 * This code was ported to U-Boot by
21 * Alexander Graf <agraf@suse.de>
22 * and is based on drivers/mmc/host/bcm2835.c in Linux which is written by
23 * Phil Elwell <phil@raspberrypi.org>
24 * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
26 * mmc-bcm2835.c by Gellert Weisz
27 * which is, in turn, based on
28 * sdhci-bcm2708.c by Broadcom
29 * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
30 * sdhci.c and sdhci-pci.c by Pierre Ossman
36 #include <asm/arch/msg.h>
37 #include <asm/arch/mbox.h>
38 #include <asm/unaligned.h>
39 #include <dm/device_compat.h>
40 #include <linux/compat.h>
42 #include <linux/iopoll.h>
43 #include <linux/sizes.h>
44 #include <mach/gpio.h>
45 #include <power/regulator.h>
47 #define msleep(a) udelay(a * 1000)
49 #define SDCMD 0x00 /* Command to SD card - 16 R/W */
50 #define SDARG 0x04 /* Argument to SD card - 32 R/W */
51 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
52 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
53 #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
54 #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
55 #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
56 #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
57 #define SDHSTS 0x20 /* SD host status - 11 R/W */
58 #define SDVDD 0x30 /* SD card power control - 1 R/W */
59 #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
60 #define SDHCFG 0x38 /* Host configuration - 2 R/W */
61 #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
62 #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
63 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
65 #define SDCMD_NEW_FLAG 0x8000
66 #define SDCMD_FAIL_FLAG 0x4000
67 #define SDCMD_BUSYWAIT 0x800
68 #define SDCMD_NO_RESPONSE 0x400
69 #define SDCMD_LONG_RESPONSE 0x200
70 #define SDCMD_WRITE_CMD 0x80
71 #define SDCMD_READ_CMD 0x40
72 #define SDCMD_CMD_MASK 0x3f
74 #define SDCDIV_MAX_CDIV 0x7ff
76 #define SDHSTS_BUSY_IRPT 0x400
77 #define SDHSTS_BLOCK_IRPT 0x200
78 #define SDHSTS_SDIO_IRPT 0x100
79 #define SDHSTS_REW_TIME_OUT 0x80
80 #define SDHSTS_CMD_TIME_OUT 0x40
81 #define SDHSTS_CRC16_ERROR 0x20
82 #define SDHSTS_CRC7_ERROR 0x10
83 #define SDHSTS_FIFO_ERROR 0x08
84 #define SDHSTS_DATA_FLAG 0x01
86 #define SDHSTS_CLEAR_MASK (SDHSTS_BUSY_IRPT | \
89 SDHSTS_REW_TIME_OUT | \
90 SDHSTS_CMD_TIME_OUT | \
91 SDHSTS_CRC16_ERROR | \
95 #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
96 SDHSTS_CRC16_ERROR | \
97 SDHSTS_REW_TIME_OUT | \
100 #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
101 SDHSTS_TRANSFER_ERROR_MASK)
103 #define SDHCFG_BUSY_IRPT_EN BIT(10)
104 #define SDHCFG_BLOCK_IRPT_EN BIT(8)
105 #define SDHCFG_SDIO_IRPT_EN BIT(5)
106 #define SDHCFG_DATA_IRPT_EN BIT(4)
107 #define SDHCFG_SLOW_CARD BIT(3)
108 #define SDHCFG_WIDE_EXT_BUS BIT(2)
109 #define SDHCFG_WIDE_INT_BUS BIT(1)
110 #define SDHCFG_REL_CMD_LINE BIT(0)
112 #define SDVDD_POWER_OFF 0
113 #define SDVDD_POWER_ON 1
115 #define SDEDM_FORCE_DATA_MODE BIT(19)
116 #define SDEDM_CLOCK_PULSE BIT(20)
117 #define SDEDM_BYPASS BIT(21)
119 #define SDEDM_FIFO_FILL_SHIFT 4
120 #define SDEDM_FIFO_FILL_MASK 0x1f
121 static u32 edm_fifo_fill(u32 edm)
123 return (edm >> SDEDM_FIFO_FILL_SHIFT) & SDEDM_FIFO_FILL_MASK;
126 #define SDEDM_WRITE_THRESHOLD_SHIFT 9
127 #define SDEDM_READ_THRESHOLD_SHIFT 14
128 #define SDEDM_THRESHOLD_MASK 0x1f
130 #define SDEDM_FSM_MASK 0xf
131 #define SDEDM_FSM_IDENTMODE 0x0
132 #define SDEDM_FSM_DATAMODE 0x1
133 #define SDEDM_FSM_READDATA 0x2
134 #define SDEDM_FSM_WRITEDATA 0x3
135 #define SDEDM_FSM_READWAIT 0x4
136 #define SDEDM_FSM_READCRC 0x5
137 #define SDEDM_FSM_WRITECRC 0x6
138 #define SDEDM_FSM_WRITEWAIT1 0x7
139 #define SDEDM_FSM_POWERDOWN 0x8
140 #define SDEDM_FSM_POWERUP 0x9
141 #define SDEDM_FSM_WRITESTART1 0xa
142 #define SDEDM_FSM_WRITESTART2 0xb
143 #define SDEDM_FSM_GENPULSES 0xc
144 #define SDEDM_FSM_WRITEWAIT2 0xd
145 #define SDEDM_FSM_STARTPOWDOWN 0xf
147 #define SDDATA_FIFO_WORDS 16
149 #define FIFO_READ_THRESHOLD 4
150 #define FIFO_WRITE_THRESHOLD 4
151 #define SDDATA_FIFO_PIO_BURST 8
153 #define SDHST_TIMEOUT_MAX_USEC 100000
155 struct bcm2835_plat {
156 struct mmc_config cfg;
160 struct bcm2835_host {
161 void __iomem *ioaddr;
164 int clock; /* Current clock speed */
165 unsigned int max_clk; /* Max possible freq */
166 unsigned int blocks; /* remaining PIO blocks */
168 u32 ns_per_fifo_word;
170 /* cached registers */
174 struct mmc_cmd *cmd; /* Current command */
175 struct mmc_data *data; /* Current data request */
176 bool use_busy:1; /* Wait for busy interrupt */
180 struct bcm2835_plat *plat;
183 static void bcm2835_dumpregs(struct bcm2835_host *host)
185 dev_dbg(dev, "=========== REGISTER DUMP ===========\n");
186 dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD));
187 dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG));
188 dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
189 dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
190 dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
191 dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
192 dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
193 dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
194 dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
195 dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD));
196 dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM));
197 dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
198 dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
199 dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
200 dev_dbg(dev, "===========================================\n");
203 static void bcm2835_reset_internal(struct bcm2835_host *host)
207 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
208 writel(0, host->ioaddr + SDCMD);
209 writel(0, host->ioaddr + SDARG);
210 /* Set timeout to a big enough value so we don't hit it */
211 writel(0xf00000, host->ioaddr + SDTOUT);
212 writel(0, host->ioaddr + SDCDIV);
213 /* Clear status register */
214 writel(SDHSTS_CLEAR_MASK, host->ioaddr + SDHSTS);
215 writel(0, host->ioaddr + SDHCFG);
216 writel(0, host->ioaddr + SDHBCT);
217 writel(0, host->ioaddr + SDHBLC);
219 /* Limit fifo usage due to silicon bug */
220 temp = readl(host->ioaddr + SDEDM);
221 temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
222 (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
223 temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
224 (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
225 writel(temp, host->ioaddr + SDEDM);
226 /* Wait for FIFO threshold to populate */
228 writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
229 /* Wait for all components to go through power on cycle */
232 writel(host->hcfg, host->ioaddr + SDHCFG);
233 writel(host->cdiv, host->ioaddr + SDCDIV);
236 static int bcm2835_wait_transfer_complete(struct bcm2835_host *host)
238 ulong tstart_ms = get_timer(0);
243 edm = readl(host->ioaddr + SDEDM);
244 fsm = edm & SDEDM_FSM_MASK;
246 if ((fsm == SDEDM_FSM_IDENTMODE) ||
247 (fsm == SDEDM_FSM_DATAMODE))
250 if ((fsm == SDEDM_FSM_READWAIT) ||
251 (fsm == SDEDM_FSM_WRITESTART1) ||
252 (fsm == SDEDM_FSM_READDATA)) {
253 writel(edm | SDEDM_FORCE_DATA_MODE,
254 host->ioaddr + SDEDM);
258 /* Error out after ~1s */
259 ulong tlapse_ms = get_timer(tstart_ms);
260 if ( tlapse_ms > 1000 /* ms */ ) {
263 "wait_transfer_complete - still waiting after %lu ms\n",
265 bcm2835_dumpregs(host);
273 static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
275 struct mmc_data *data = host->data;
276 size_t blksize = data->blocksize;
281 if (blksize % sizeof(u32))
284 buf = is_read ? (u32 *)data->dest : (u32 *)data->src;
287 data->dest += blksize;
289 data->src += blksize;
291 copy_words = blksize / sizeof(u32);
294 * Copy all contents from/to the FIFO as far as it reaches,
295 * then wait for it to fill/empty again and rewind.
298 int burst_words, words;
301 burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
302 edm = readl(host->ioaddr + SDEDM);
304 words = edm_fifo_fill(edm);
306 words = SDDATA_FIFO_WORDS - edm_fifo_fill(edm);
308 if (words < burst_words) {
309 int fsm_state = (edm & SDEDM_FSM_MASK);
312 (fsm_state != SDEDM_FSM_READDATA &&
313 fsm_state != SDEDM_FSM_READWAIT &&
314 fsm_state != SDEDM_FSM_READCRC)) ||
316 (fsm_state != SDEDM_FSM_WRITEDATA &&
317 fsm_state != SDEDM_FSM_WRITEWAIT1 &&
318 fsm_state != SDEDM_FSM_WRITEWAIT2 &&
319 fsm_state != SDEDM_FSM_WRITECRC &&
320 fsm_state != SDEDM_FSM_WRITESTART1 &&
321 fsm_state != SDEDM_FSM_WRITESTART2))) {
322 hsts = readl(host->ioaddr + SDHSTS);
323 printf("fsm %x, hsts %08x\n", fsm_state, hsts);
324 if (hsts & SDHSTS_ERROR_MASK)
329 } else if (words > copy_words) {
335 /* Copy current chunk to/from the FIFO */
338 *(buf++) = readl(host->ioaddr + SDDATA);
340 writel(*(buf++), host->ioaddr + SDDATA);
348 static int bcm2835_transfer_pio(struct bcm2835_host *host)
354 is_read = (host->data->flags & MMC_DATA_READ) != 0;
355 ret = bcm2835_transfer_block_pio(host, is_read);
359 sdhsts = readl(host->ioaddr + SDHSTS);
360 if (sdhsts & (SDHSTS_CRC16_ERROR |
362 SDHSTS_FIFO_ERROR)) {
363 printf("%s transfer error - HSTS %08x\n",
364 is_read ? "read" : "write", sdhsts);
366 } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
367 SDHSTS_REW_TIME_OUT))) {
368 printf("%s timeout error - HSTS %08x\n",
369 is_read ? "read" : "write", sdhsts);
376 static void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd,
377 struct mmc_data *data)
386 host->blocks = data->blocks;
388 writel(data->blocksize, host->ioaddr + SDHBCT);
389 writel(data->blocks, host->ioaddr + SDHBLC);
392 static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host)
396 int timeout_us = SDHST_TIMEOUT_MAX_USEC;
398 ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
399 !(value & SDCMD_NEW_FLAG), timeout_us);
400 if (ret == -ETIMEDOUT)
401 printf("%s: timeout (%d us)\n", __func__, timeout_us);
406 static int bcm2835_send_command(struct bcm2835_host *host, struct mmc_cmd *cmd,
407 struct mmc_data *data)
413 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) {
414 printf("unsupported response type!\n");
418 sdcmd = bcm2835_read_wait_sdcmd(host);
419 if (sdcmd & SDCMD_NEW_FLAG) {
420 printf("previous command never completed.\n");
421 bcm2835_dumpregs(host);
427 /* Clear any error flags */
428 sdhsts = readl(host->ioaddr + SDHSTS);
429 if (sdhsts & SDHSTS_ERROR_MASK)
430 writel(sdhsts, host->ioaddr + SDHSTS);
432 bcm2835_prepare_data(host, cmd, data);
434 writel(cmd->cmdarg, host->ioaddr + SDARG);
436 sdcmd = cmd->cmdidx & SDCMD_CMD_MASK;
438 host->use_busy = false;
439 if (!(cmd->resp_type & MMC_RSP_PRESENT)) {
440 sdcmd |= SDCMD_NO_RESPONSE;
442 if (cmd->resp_type & MMC_RSP_136)
443 sdcmd |= SDCMD_LONG_RESPONSE;
444 if (cmd->resp_type & MMC_RSP_BUSY) {
445 sdcmd |= SDCMD_BUSYWAIT;
446 host->use_busy = true;
451 if (data->flags & MMC_DATA_WRITE)
452 sdcmd |= SDCMD_WRITE_CMD;
453 if (data->flags & MMC_DATA_READ)
454 sdcmd |= SDCMD_READ_CMD;
457 writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
462 static int bcm2835_finish_command(struct bcm2835_host *host)
464 struct mmc_cmd *cmd = host->cmd;
468 sdcmd = bcm2835_read_wait_sdcmd(host);
470 /* Check for errors */
471 if (sdcmd & SDCMD_NEW_FLAG) {
472 printf("command never completed.\n");
473 bcm2835_dumpregs(host);
475 } else if (sdcmd & SDCMD_FAIL_FLAG) {
476 u32 sdhsts = readl(host->ioaddr + SDHSTS);
478 /* Clear the errors */
479 writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
481 if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
482 (host->cmd->cmdidx != MMC_CMD_SEND_OP_COND)) {
483 if (sdhsts & SDHSTS_CMD_TIME_OUT) {
486 printf("unexpected command %d error\n",
488 bcm2835_dumpregs(host);
496 if (cmd->resp_type & MMC_RSP_PRESENT) {
497 if (cmd->resp_type & MMC_RSP_136) {
500 for (i = 0; i < 4; i++) {
501 cmd->response[3 - i] =
502 readl(host->ioaddr + SDRSP0 + i * 4);
505 cmd->response[0] = readl(host->ioaddr + SDRSP0);
509 /* Processed actual command. */
515 static int bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
519 if (!(intmask & SDHSTS_ERROR_MASK))
525 printf("sdhost_busy_irq: intmask %08x\n", intmask);
526 if (intmask & SDHSTS_CRC7_ERROR) {
528 } else if (intmask & (SDHSTS_CRC16_ERROR |
529 SDHSTS_FIFO_ERROR)) {
531 } else if (intmask & (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT)) {
534 bcm2835_dumpregs(host);
538 static int bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
544 if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
546 if (intmask & SDHSTS_REW_TIME_OUT)
550 printf("%s:%d %d\n", __func__, __LINE__, ret);
555 static int bcm2835_transmit(struct bcm2835_host *host)
557 u32 intmask = readl(host->ioaddr + SDHSTS);
560 /* Check for errors */
561 ret = bcm2835_check_data_error(host, intmask);
565 ret = bcm2835_check_cmd_error(host, intmask);
569 /* Handle wait for busy end */
570 if (host->use_busy && (intmask & SDHSTS_BUSY_IRPT)) {
571 writel(SDHSTS_BUSY_IRPT, host->ioaddr + SDHSTS);
572 host->use_busy = false;
573 bcm2835_finish_command(host);
576 /* Handle PIO data transfer */
578 ret = bcm2835_transfer_pio(host);
582 if (host->blocks == 0) {
583 /* Wait for command to complete for real */
584 ret = bcm2835_wait_transfer_complete(host);
587 /* Transfer complete */
595 static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
599 /* The SDCDIV register has 11 bits, and holds (div - 2). But
600 * in data mode the max is 50MHz wihout a minimum, and only
601 * the bottom 3 bits are used. Since the switch over is
602 * automatic (unless we have marked the card as slow...),
603 * chosen values have to make sense in both modes. Ident mode
604 * must be 100-400KHz, so can range check the requested
605 * clock. CMD15 must be used to return to data mode, so this
608 * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
609 * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
611 * 623->400KHz/27.8MHz
612 * reset value (507)->491159/50MHz
614 * BUT, the 3-bit clock divisor in data mode is too small if
615 * the core clock is higher than 250MHz, so instead use the
616 * SLOW_CARD configuration bit to force the use of the ident
617 * clock divisor at all times.
620 if (clock < 100000) {
621 /* Can't stop the clock, but make it as slow as possible
624 host->cdiv = SDCDIV_MAX_CDIV;
625 writel(host->cdiv, host->ioaddr + SDCDIV);
629 div = host->max_clk / clock;
632 if ((host->max_clk / div) > clock)
636 if (div > SDCDIV_MAX_CDIV)
637 div = SDCDIV_MAX_CDIV;
639 clock = host->max_clk / (div + 2);
640 host->mmc->clock = clock;
642 /* Calibrate some delays */
644 host->ns_per_fifo_word = (1000000000 / clock) *
645 ((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32);
648 writel(host->cdiv, host->ioaddr + SDCDIV);
650 /* Set the timeout to 500ms */
651 writel(host->mmc->clock / 2, host->ioaddr + SDTOUT);
654 static inline int is_power_of_2(u64 x)
656 return !(x & (x - 1));
659 static int bcm2835_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
660 struct mmc_data *data)
662 struct bcm2835_host *host = dev_get_priv(dev);
666 if (data && !is_power_of_2(data->blocksize)) {
667 printf("unsupported block size (%d bytes)\n", data->blocksize);
673 edm = readl(host->ioaddr + SDEDM);
674 fsm = edm & SDEDM_FSM_MASK;
676 if ((fsm != SDEDM_FSM_IDENTMODE) &&
677 (fsm != SDEDM_FSM_DATAMODE) &&
678 (cmd && cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
679 printf("previous command (%d) not complete (EDM %08x)\n",
680 readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, edm);
681 bcm2835_dumpregs(host);
690 ret = bcm2835_send_command(host, cmd, data);
691 if (!ret && !host->use_busy)
692 ret = bcm2835_finish_command(host);
695 /* Wait for completion of busy signal or data transfer */
696 while (host->use_busy || host->data) {
697 ret = bcm2835_transmit(host);
705 static int bcm2835_set_ios(struct udevice *dev)
707 struct bcm2835_host *host = dev_get_priv(dev);
708 struct mmc *mmc = mmc_get_mmc_dev(dev);
710 if (!mmc->clock || mmc->clock != host->clock) {
711 bcm2835_set_clock(host, mmc->clock);
712 host->clock = mmc->clock;
716 host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
717 if (mmc->bus_width == 4)
718 host->hcfg |= SDHCFG_WIDE_EXT_BUS;
720 host->hcfg |= SDHCFG_WIDE_INT_BUS;
722 /* Disable clever clock switching, to cope with fast core clocks */
723 host->hcfg |= SDHCFG_SLOW_CARD;
725 writel(host->hcfg, host->ioaddr + SDHCFG);
730 static void bcm2835_add_host(struct bcm2835_host *host)
732 struct mmc_config *cfg = &host->plat->cfg;
734 cfg->f_max = host->max_clk;
735 cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV;
738 dev_dbg(dev, "f_max %d, f_min %d\n",
739 cfg->f_max, cfg->f_min);
741 /* host controller capabilities */
742 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
744 /* report supported voltage ranges */
745 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
747 /* Set interrupt enables */
748 host->hcfg = SDHCFG_BUSY_IRPT_EN;
750 bcm2835_reset_internal(host);
753 static int bcm2835_probe(struct udevice *dev)
755 struct bcm2835_plat *plat = dev_get_platdata(dev);
756 struct bcm2835_host *host = dev_get_priv(dev);
757 struct mmc *mmc = mmc_get_mmc_dev(dev);
758 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
763 upriv->mmc = &plat->mmc;
764 plat->cfg.name = dev->name;
766 host->phys_addr = devfdt_get_addr(dev);
767 if (host->phys_addr == FDT_ADDR_T_NONE)
770 host->ioaddr = devm_ioremap(dev, host->phys_addr, SZ_256);
774 host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE);
776 bcm2835_add_host(host);
778 dev_dbg(dev, "%s -> OK\n", __func__);
783 static const struct udevice_id bcm2835_match[] = {
784 { .compatible = "brcm,bcm2835-sdhost" },
788 static const struct dm_mmc_ops bcm2835_ops = {
789 .send_cmd = bcm2835_send_cmd,
790 .set_ios = bcm2835_set_ios,
793 static int bcm2835_bind(struct udevice *dev)
795 struct bcm2835_plat *plat = dev_get_platdata(dev);
797 return mmc_bind(dev, &plat->mmc, &plat->cfg);
800 U_BOOT_DRIVER(bcm2835_sdhost) = {
801 .name = "bcm2835-sdhost",
803 .of_match = bcm2835_match,
804 .bind = bcm2835_bind,
805 .probe = bcm2835_probe,
806 .priv_auto_alloc_size = sizeof(struct bcm2835_host),
807 .platdata_auto_alloc_size = sizeof(struct bcm2835_plat),