drivers/mmc/am654_sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Texas Instruments' K3 SD Host Controller Interface
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <malloc.h>
  12 #include <power-domain.h>
  13 #include <regmap.h>
  14 #include <sdhci.h>
  15 #include <dm/device_compat.h>
  16 #include <linux/err.h>
  17
  18 /* CTL_CFG Registers */
  19 #define CTL_CFG_2               0x14
  20
  21 #define SLOTTYPE_MASK           GENMASK(31, 30)
  22 #define SLOTTYPE_EMBEDDED       BIT(30)
  23
  24 /* PHY Registers */
  25 #define PHY_CTRL1       0x100
  26 #define PHY_CTRL2       0x104
  27 #define PHY_CTRL3       0x108
  28 #define PHY_CTRL4       0x10C
  29 #define PHY_CTRL5       0x110
  30 #define PHY_CTRL6       0x114
  31 #define PHY_STAT1       0x130
  32 #define PHY_STAT2       0x134
  33
  34 #define IOMUX_ENABLE_SHIFT      31
  35 #define IOMUX_ENABLE_MASK       BIT(IOMUX_ENABLE_SHIFT)
  36 #define OTAPDLYENA_SHIFT        20
  37 #define OTAPDLYENA_MASK         BIT(OTAPDLYENA_SHIFT)
  38 #define OTAPDLYSEL_SHIFT        12
  39 #define OTAPDLYSEL_MASK         GENMASK(15, 12)
  40 #define STRBSEL_SHIFT           24
  41 #define STRBSEL_4BIT_MASK       GENMASK(27, 24)
  42 #define STRBSEL_8BIT_MASK       GENMASK(31, 24)
  43 #define SEL50_SHIFT             8
  44 #define SEL50_MASK              BIT(SEL50_SHIFT)
  45 #define SEL100_SHIFT            9
  46 #define SEL100_MASK             BIT(SEL100_SHIFT)
  47 #define FREQSEL_SHIFT           8
  48 #define FREQSEL_MASK            GENMASK(10, 8)
  49 #define DLL_TRIM_ICP_SHIFT      4
  50 #define DLL_TRIM_ICP_MASK       GENMASK(7, 4)
  51 #define DR_TY_SHIFT             20
  52 #define DR_TY_MASK              GENMASK(22, 20)
  53 #define ENDLL_SHIFT             1
  54 #define ENDLL_MASK              BIT(ENDLL_SHIFT)
  55 #define DLLRDY_SHIFT            0
  56 #define DLLRDY_MASK             BIT(DLLRDY_SHIFT)
  57 #define PDB_SHIFT               0
  58 #define PDB_MASK                BIT(PDB_SHIFT)
  59 #define CALDONE_SHIFT           1
  60 #define CALDONE_MASK            BIT(CALDONE_SHIFT)
  61 #define RETRIM_SHIFT            17
  62 #define RETRIM_MASK             BIT(RETRIM_SHIFT)
  63
  64 #define DRIVER_STRENGTH_50_OHM  0x0
  65 #define DRIVER_STRENGTH_33_OHM  0x1
  66 #define DRIVER_STRENGTH_66_OHM  0x2
  67 #define DRIVER_STRENGTH_100_OHM 0x3
  68 #define DRIVER_STRENGTH_40_OHM  0x4
  69
  70 #define AM654_SDHCI_MIN_FREQ    400000
  71
  72 struct am654_sdhci_plat {
  73         struct mmc_config cfg;
  74         struct mmc mmc;
  75         struct regmap *base;
  76         bool non_removable;
  77         u32 otap_del_sel[11];
  78         u32 trm_icp;
  79         u32 drv_strength;
  80         u32 strb_sel;
  81         u32 flags;
  82 #define DLL_PRESENT     (1 << 0)
  83 #define IOMUX_PRESENT   (1 << 1)
  84 #define FREQSEL_2_BIT   (1 << 2)
  85 #define STRBSEL_4_BIT   (1 << 3)
  86         bool dll_on;
  87 };
  88
  89 struct timing_data {
  90         const char *binding;
  91         u32 capability;
  92 };
  93
  94 static const struct timing_data td[] = {
  95         [MMC_LEGACY] = {"ti,otap-del-sel-legacy", 0},
  96         [MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP(MMC_HS)},
  97         [SD_HS]  = {"ti,otap-del-sel-sd-hs", MMC_CAP(SD_HS)},
  98         [UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP(UHS_SDR12)},
  99         [UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP(UHS_SDR25)},
 100         [UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP(UHS_SDR50)},
 101         [UHS_SDR104] = {"ti,otap-del-sel-sdr104", MMC_CAP(UHS_SDR104)},
 102         [UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP(UHS_DDR50)},
 103         [MMC_DDR_52] = {"ti,otap-del-sel-ddr52", MMC_CAP(MMC_DDR_52)},
 104         [MMC_HS_200] = {"ti,otap-del-sel-hs200", MMC_CAP(MMC_HS_200)},
 105         [MMC_HS_400] = {"ti,otap-del-sel-hs400", MMC_CAP(MMC_HS_400)},
 106 };
 107
 108 struct am654_driver_data {
 109         const struct sdhci_ops *ops;
 110         u32 flags;
 111 };
 112
 113 static void am654_sdhci_set_control_reg(struct sdhci_host *host)
 114 {
 115         struct mmc *mmc = (struct mmc *)host->mmc;
 116         u32 reg;
 117
 118         if (IS_SD(host->mmc) &&
 119             mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 120                 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 121                 reg |= SDHCI_CTRL_VDD_180;
 122                 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 123         }
 124
 125         sdhci_set_uhs_timing(host);
 126 }
 127
 128 static int am654_sdhci_set_ios_post(struct sdhci_host *host)
 129 {
 130         struct udevice *dev = host->mmc->dev;
 131         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
 132         unsigned int speed = host->mmc->clock;
 133         int sel50, sel100, freqsel;
 134         u32 otap_del_sel;
 135         u32 mask, val;
 136         int ret;
 137
 138         /* Reset SD Clock Enable */
 139         val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 140         val &= ~SDHCI_CLOCK_CARD_EN;
 141         sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
 142
 143         /* power off phy */
 144         if (plat->dll_on) {
 145                 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
 146
 147                 plat->dll_on = false;
 148         }
 149
 150         /* restart clock */
 151         sdhci_set_clock(host->mmc, speed);
 152
 153         /* switch phy back on */
 154         if (speed > AM654_SDHCI_MIN_FREQ) {
 155                 otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
 156                 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 157                 val = (1 << OTAPDLYENA_SHIFT) |
 158                       (otap_del_sel << OTAPDLYSEL_SHIFT);
 159
 160                 /* Write to STRBSEL for HS400 speed mode */
 161                 if (host->mmc->selected_mode == MMC_HS_400) {
 162                         if (plat->flags & STRBSEL_4_BIT)
 163                                 mask |= STRBSEL_4BIT_MASK;
 164                         else
 165                                 mask |= STRBSEL_8BIT_MASK;
 166
 167                         val |= plat->strb_sel << STRBSEL_SHIFT;
 168                 }
 169
 170                 regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
 171
 172                 if (plat->flags & FREQSEL_2_BIT) {
 173                         switch (speed) {
 174                         case 200000000:
 175                                 sel50 = 0;
 176                                 sel100 = 0;
 177                                 break;
 178                         case 100000000:
 179                                 sel50 = 0;
 180                                 sel100 = 1;
 181                                 break;
 182                         default:
 183                                 sel50 = 1;
 184                                 sel100 = 0;
 185                         }
 186
 187                         /* Configure PHY DLL frequency */
 188                         mask = SEL50_MASK | SEL100_MASK;
 189                         val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
 190                         regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
 191                 } else {
 192                         switch (speed) {
 193                         case 200000000:
 194                                 freqsel = 0x0;
 195                                 break;
 196                         default:
 197                                 freqsel = 0x4;
 198                         }
 199                         regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK,
 200                                            freqsel << FREQSEL_SHIFT);
 201                 }
 202
 203                 /* Enable DLL */
 204                 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
 205                                    0x1 << ENDLL_SHIFT);
 206                 /*
 207                  * Poll for DLL ready. Use a one second timeout.
 208                  * Works in all experiments done so far
 209                  */
 210                 ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
 211                                          val & DLLRDY_MASK, 1000, 1000000);
 212                 if (ret)
 213                         return ret;
 214
 215                 plat->dll_on = true;
 216         }
 217
 218         return 0;
 219 }
 220
 221 int am654_sdhci_init(struct am654_sdhci_plat *plat)
 222 {
 223         u32 ctl_cfg_2 = 0;
 224         u32 mask, val;
 225         int ret;
 226
 227         /* Reset OTAP to default value */
 228         mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 229         regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
 230
 231         if (plat->flags & DLL_PRESENT) {
 232                 regmap_read(plat->base, PHY_STAT1, &val);
 233                 if (~val & CALDONE_MASK) {
 234                         /* Calibrate IO lines */
 235                         regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK,
 236                                            PDB_MASK);
 237                         ret = regmap_read_poll_timeout(plat->base, PHY_STAT1,
 238                                                        val, val & CALDONE_MASK,
 239                                                        1, 20);
 240                         if (ret)
 241                                 return ret;
 242                 }
 243
 244                 /* Configure DLL TRIM */
 245                 mask = DLL_TRIM_ICP_MASK;
 246                 val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
 247
 248                 /* Configure DLL driver strength */
 249                 mask |= DR_TY_MASK;
 250                 val |= plat->drv_strength << DR_TY_SHIFT;
 251                 regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
 252         }
 253
 254         /* Enable pins by setting IO mux to 0 */
 255         if (plat->flags & IOMUX_PRESENT)
 256                 regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
 257
 258         /* Set slot type based on SD or eMMC */
 259         if (plat->non_removable)
 260                 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
 261
 262         regmap_update_bits(plat->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2);
 263
 264         return 0;
 265 }
 266
 267 #define MAX_SDCD_DEBOUNCE_TIME 2000
 268 static int am654_sdhci_deferred_probe(struct sdhci_host *host)
 269 {
 270         struct udevice *dev = host->mmc->dev;
 271         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
 272         unsigned long start;
 273         int val;
 274
 275         /*
 276          * The controller takes about 1 second to debounce the card detect line
 277          * and doesn't let us power on until that time is up. Instead of waiting
 278          * for 1 second at every stage, poll on the CARD_PRESENT bit upto a
 279          * maximum of 2 seconds to be safe..
 280          */
 281         start = get_timer(0);
 282         do {
 283                 if (get_timer(start) > MAX_SDCD_DEBOUNCE_TIME)
 284                         return -ENOMEDIUM;
 285
 286                 val = mmc_getcd(host->mmc);
 287         } while (!val);
 288
 289         am654_sdhci_init(plat);
 290
 291         return sdhci_probe(dev);
 292 }
 293
 294 const struct sdhci_ops am654_sdhci_ops = {
 295         .deferred_probe         = am654_sdhci_deferred_probe,
 296         .set_ios_post           = &am654_sdhci_set_ios_post,
 297         .set_control_reg        = &am654_sdhci_set_control_reg,
 298 };
 299
 300 const struct am654_driver_data am654_drv_data = {
 301         .ops = &am654_sdhci_ops,
 302         .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | STRBSEL_4_BIT,
 303 };
 304
 305 const struct am654_driver_data j721e_8bit_drv_data = {
 306         .ops = &am654_sdhci_ops,
 307         .flags = DLL_PRESENT,
 308 };
 309
 310 static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
 311 {
 312         struct udevice *dev = host->mmc->dev;
 313         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
 314         u32 otap_del_sel, mask, val;
 315
 316         otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
 317         mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 318         val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT);
 319         regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
 320
 321         return 0;
 322 }
 323
 324 const struct sdhci_ops j721e_4bit_sdhci_ops = {
 325         .deferred_probe         = am654_sdhci_deferred_probe,
 326         .set_ios_post           = &j721e_4bit_sdhci_set_ios_post,
 327 };
 328
 329 const struct am654_driver_data j721e_4bit_drv_data = {
 330         .ops = &j721e_4bit_sdhci_ops,
 331         .flags = IOMUX_PRESENT,
 332 };
 333
 334 static int sdhci_am654_get_otap_delay(struct udevice *dev,
 335                                       struct mmc_config *cfg)
 336 {
 337         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
 338         int ret;
 339         int i;
 340
 341         /* ti,otap-del-sel-legacy is mandatory */
 342         ret = dev_read_u32(dev, "ti,otap-del-sel-legacy",
 343                            &plat->otap_del_sel[0]);
 344         if (ret)
 345                 return ret;
 346         /*
 347          * Remove the corresponding capability if an otap-del-sel
 348          * value is not found
 349          */
 350         for (i = MMC_HS; i <= MMC_HS_400; i++) {
 351                 ret = dev_read_u32(dev, td[i].binding, &plat->otap_del_sel[i]);
 352                 if (ret) {
 353                         dev_dbg(dev, "Couldn't find %s\n", td[i].binding);
 354                         /*
 355                          * Remove the corresponding capability
 356                          * if an otap-del-sel value is not found
 357                          */
 358                         cfg->host_caps &= ~td[i].capability;
 359                 }
 360         }
 361
 362         return 0;
 363 }
 364
 365 static int am654_sdhci_probe(struct udevice *dev)
 366 {
 367         struct am654_driver_data *drv_data =
 368                         (struct am654_driver_data *)dev_get_driver_data(dev);
 369         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
 370         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 371         struct sdhci_host *host = dev_get_priv(dev);
 372         struct mmc_config *cfg = &plat->cfg;
 373         struct clk clk;
 374         unsigned long clock;
 375         int ret;
 376
 377         ret = clk_get_by_name(dev, "clk_xin", &clk);
 378         if (ret) {
 379                 dev_err(dev, "failed to get clock\n");
 380                 return ret;
 381         }
 382
 383         clock = clk_get_rate(&clk);
 384         if (IS_ERR_VALUE(clock)) {
 385                 dev_err(dev, "failed to get rate\n");
 386                 return clock;
 387         }
 388
 389         host->max_clk = clock;
 390         host->mmc = &plat->mmc;
 391         host->mmc->dev = dev;
 392         ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
 393                               AM654_SDHCI_MIN_FREQ);
 394         if (ret)
 395                 return ret;
 396
 397         ret = sdhci_am654_get_otap_delay(dev, cfg);
 398         if (ret)
 399                 return ret;
 400
 401         host->ops = drv_data->ops;
 402         host->mmc->priv = host;
 403         upriv->mmc = host->mmc;
 404
 405         regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1);
 406
 407         return 0;
 408 }
 409
 410 static int am654_sdhci_ofdata_to_platdata(struct udevice *dev)
 411 {
 412         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
 413         struct sdhci_host *host = dev_get_priv(dev);
 414         struct mmc_config *cfg = &plat->cfg;
 415         u32 drv_strength;
 416         int ret;
 417
 418         host->name = dev->name;
 419         host->ioaddr = (void *)dev_read_addr(dev);
 420         plat->non_removable = dev_read_bool(dev, "non-removable");
 421
 422         if (plat->flags & DLL_PRESENT) {
 423                 ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp);
 424                 if (ret)
 425                         return ret;
 426
 427                 ret = dev_read_u32(dev, "ti,driver-strength-ohm",
 428                                    &drv_strength);
 429                 if (ret)
 430                         return ret;
 431
 432                 switch (drv_strength) {
 433                 case 50:
 434                         plat->drv_strength = DRIVER_STRENGTH_50_OHM;
 435                         break;
 436                 case 33:
 437                         plat->drv_strength = DRIVER_STRENGTH_33_OHM;
 438                         break;
 439                 case 66:
 440                         plat->drv_strength = DRIVER_STRENGTH_66_OHM;
 441                         break;
 442                 case 100:
 443                         plat->drv_strength = DRIVER_STRENGTH_100_OHM;
 444                         break;
 445                 case 40:
 446                         plat->drv_strength = DRIVER_STRENGTH_40_OHM;
 447                         break;
 448                 default:
 449                         dev_err(dev, "Invalid driver strength\n");
 450                         return -EINVAL;
 451                 }
 452         }
 453
 454         ret = mmc_of_parse(dev, cfg);
 455         if (ret)
 456                 return ret;
 457
 458         return 0;
 459 }
 460
 461 static int am654_sdhci_bind(struct udevice *dev)
 462 {
 463         struct am654_driver_data *drv_data =
 464                         (struct am654_driver_data *)dev_get_driver_data(dev);
 465         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
 466
 467         plat->flags = drv_data->flags;
 468
 469         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 470 }
 471
 472 static const struct udevice_id am654_sdhci_ids[] = {
 473         {
 474                 .compatible = "ti,am654-sdhci-5.1",
 475                 .data = (ulong)&am654_drv_data,
 476         },
 477         {
 478                 .compatible = "ti,j721e-sdhci-8bit",
 479                 .data = (ulong)&j721e_8bit_drv_data,
 480         },
 481         {
 482                 .compatible = "ti,j721e-sdhci-4bit",
 483                 .data = (ulong)&j721e_4bit_drv_data,
 484         },
 485         { }
 486 };
 487
 488 U_BOOT_DRIVER(am654_sdhci_drv) = {
 489         .name           = "am654_sdhci",
 490         .id             = UCLASS_MMC,
 491         .of_match       = am654_sdhci_ids,
 492         .ofdata_to_platdata = am654_sdhci_ofdata_to_platdata,
 493         .ops            = &sdhci_ops,
 494         .bind           = am654_sdhci_bind,
 495         .probe          = am654_sdhci_probe,
 496         .priv_auto_alloc_size = sizeof(struct sdhci_host),
 497         .platdata_auto_alloc_size = sizeof(struct am654_sdhci_plat),
 498 };