1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
5 * Texas Instruments' K3 SD Host Controller Interface
12 #include <power-domain.h>
15 #include <dm/device_compat.h>
16 #include <linux/err.h>
18 /* CTL_CFG Registers */
19 #define CTL_CFG_2 0x14
21 #define SLOTTYPE_MASK GENMASK(31, 30)
22 #define SLOTTYPE_EMBEDDED BIT(30)
25 #define PHY_CTRL1 0x100
26 #define PHY_CTRL2 0x104
27 #define PHY_CTRL3 0x108
28 #define PHY_CTRL4 0x10C
29 #define PHY_CTRL5 0x110
30 #define PHY_CTRL6 0x114
31 #define PHY_STAT1 0x130
32 #define PHY_STAT2 0x134
34 #define IOMUX_ENABLE_SHIFT 31
35 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
36 #define OTAPDLYENA_SHIFT 20
37 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
38 #define OTAPDLYSEL_SHIFT 12
39 #define OTAPDLYSEL_MASK GENMASK(15, 12)
40 #define STRBSEL_SHIFT 24
41 #define STRBSEL_4BIT_MASK GENMASK(27, 24)
42 #define STRBSEL_8BIT_MASK GENMASK(31, 24)
44 #define SEL50_MASK BIT(SEL50_SHIFT)
45 #define SEL100_SHIFT 9
46 #define SEL100_MASK BIT(SEL100_SHIFT)
47 #define FREQSEL_SHIFT 8
48 #define FREQSEL_MASK GENMASK(10, 8)
49 #define DLL_TRIM_ICP_SHIFT 4
50 #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
51 #define DR_TY_SHIFT 20
52 #define DR_TY_MASK GENMASK(22, 20)
54 #define ENDLL_MASK BIT(ENDLL_SHIFT)
55 #define DLLRDY_SHIFT 0
56 #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
58 #define PDB_MASK BIT(PDB_SHIFT)
59 #define CALDONE_SHIFT 1
60 #define CALDONE_MASK BIT(CALDONE_SHIFT)
61 #define RETRIM_SHIFT 17
62 #define RETRIM_MASK BIT(RETRIM_SHIFT)
64 #define DRIVER_STRENGTH_50_OHM 0x0
65 #define DRIVER_STRENGTH_33_OHM 0x1
66 #define DRIVER_STRENGTH_66_OHM 0x2
67 #define DRIVER_STRENGTH_100_OHM 0x3
68 #define DRIVER_STRENGTH_40_OHM 0x4
70 #define AM654_SDHCI_MIN_FREQ 400000
72 struct am654_sdhci_plat {
73 struct mmc_config cfg;
82 #define DLL_PRESENT (1 << 0)
83 #define IOMUX_PRESENT (1 << 1)
84 #define FREQSEL_2_BIT (1 << 2)
85 #define STRBSEL_4_BIT (1 << 3)
94 static const struct timing_data td[] = {
95 [MMC_LEGACY] = {"ti,otap-del-sel-legacy", 0},
96 [MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP(MMC_HS)},
97 [SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP(SD_HS)},
98 [UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP(UHS_SDR12)},
99 [UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP(UHS_SDR25)},
100 [UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP(UHS_SDR50)},
101 [UHS_SDR104] = {"ti,otap-del-sel-sdr104", MMC_CAP(UHS_SDR104)},
102 [UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP(UHS_DDR50)},
103 [MMC_DDR_52] = {"ti,otap-del-sel-ddr52", MMC_CAP(MMC_DDR_52)},
104 [MMC_HS_200] = {"ti,otap-del-sel-hs200", MMC_CAP(MMC_HS_200)},
105 [MMC_HS_400] = {"ti,otap-del-sel-hs400", MMC_CAP(MMC_HS_400)},
108 struct am654_driver_data {
109 const struct sdhci_ops *ops;
113 static void am654_sdhci_set_control_reg(struct sdhci_host *host)
115 struct mmc *mmc = (struct mmc *)host->mmc;
118 if (IS_SD(host->mmc) &&
119 mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
120 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
121 reg |= SDHCI_CTRL_VDD_180;
122 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
125 sdhci_set_uhs_timing(host);
128 static int am654_sdhci_set_ios_post(struct sdhci_host *host)
130 struct udevice *dev = host->mmc->dev;
131 struct am654_sdhci_plat *plat = dev_get_platdata(dev);
132 unsigned int speed = host->mmc->clock;
133 int sel50, sel100, freqsel;
138 /* Reset SD Clock Enable */
139 val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
140 val &= ~SDHCI_CLOCK_CARD_EN;
141 sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
145 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
147 plat->dll_on = false;
151 sdhci_set_clock(host->mmc, speed);
153 /* switch phy back on */
154 if (speed > AM654_SDHCI_MIN_FREQ) {
155 otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
156 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
157 val = (1 << OTAPDLYENA_SHIFT) |
158 (otap_del_sel << OTAPDLYSEL_SHIFT);
160 /* Write to STRBSEL for HS400 speed mode */
161 if (host->mmc->selected_mode == MMC_HS_400) {
162 if (plat->flags & STRBSEL_4_BIT)
163 mask |= STRBSEL_4BIT_MASK;
165 mask |= STRBSEL_8BIT_MASK;
167 val |= plat->strb_sel << STRBSEL_SHIFT;
170 regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
172 if (plat->flags & FREQSEL_2_BIT) {
187 /* Configure PHY DLL frequency */
188 mask = SEL50_MASK | SEL100_MASK;
189 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
190 regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
199 regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK,
200 freqsel << FREQSEL_SHIFT);
204 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
207 * Poll for DLL ready. Use a one second timeout.
208 * Works in all experiments done so far
210 ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
211 val & DLLRDY_MASK, 1000, 1000000);
221 int am654_sdhci_init(struct am654_sdhci_plat *plat)
227 /* Reset OTAP to default value */
228 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
229 regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
231 if (plat->flags & DLL_PRESENT) {
232 regmap_read(plat->base, PHY_STAT1, &val);
233 if (~val & CALDONE_MASK) {
234 /* Calibrate IO lines */
235 regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK,
237 ret = regmap_read_poll_timeout(plat->base, PHY_STAT1,
238 val, val & CALDONE_MASK,
244 /* Configure DLL TRIM */
245 mask = DLL_TRIM_ICP_MASK;
246 val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
248 /* Configure DLL driver strength */
250 val |= plat->drv_strength << DR_TY_SHIFT;
251 regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
254 /* Enable pins by setting IO mux to 0 */
255 if (plat->flags & IOMUX_PRESENT)
256 regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
258 /* Set slot type based on SD or eMMC */
259 if (plat->non_removable)
260 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
262 regmap_update_bits(plat->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2);
267 #define MAX_SDCD_DEBOUNCE_TIME 2000
268 static int am654_sdhci_deferred_probe(struct sdhci_host *host)
270 struct udevice *dev = host->mmc->dev;
271 struct am654_sdhci_plat *plat = dev_get_platdata(dev);
276 * The controller takes about 1 second to debounce the card detect line
277 * and doesn't let us power on until that time is up. Instead of waiting
278 * for 1 second at every stage, poll on the CARD_PRESENT bit upto a
279 * maximum of 2 seconds to be safe..
281 start = get_timer(0);
283 if (get_timer(start) > MAX_SDCD_DEBOUNCE_TIME)
286 val = mmc_getcd(host->mmc);
289 am654_sdhci_init(plat);
291 return sdhci_probe(dev);
294 const struct sdhci_ops am654_sdhci_ops = {
295 .deferred_probe = am654_sdhci_deferred_probe,
296 .set_ios_post = &am654_sdhci_set_ios_post,
297 .set_control_reg = &am654_sdhci_set_control_reg,
300 const struct am654_driver_data am654_drv_data = {
301 .ops = &am654_sdhci_ops,
302 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | STRBSEL_4_BIT,
305 const struct am654_driver_data j721e_8bit_drv_data = {
306 .ops = &am654_sdhci_ops,
307 .flags = DLL_PRESENT,
310 static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
312 struct udevice *dev = host->mmc->dev;
313 struct am654_sdhci_plat *plat = dev_get_platdata(dev);
314 u32 otap_del_sel, mask, val;
316 otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
317 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
318 val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT);
319 regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
324 const struct sdhci_ops j721e_4bit_sdhci_ops = {
325 .deferred_probe = am654_sdhci_deferred_probe,
326 .set_ios_post = &j721e_4bit_sdhci_set_ios_post,
329 const struct am654_driver_data j721e_4bit_drv_data = {
330 .ops = &j721e_4bit_sdhci_ops,
331 .flags = IOMUX_PRESENT,
334 static int sdhci_am654_get_otap_delay(struct udevice *dev,
335 struct mmc_config *cfg)
337 struct am654_sdhci_plat *plat = dev_get_platdata(dev);
341 /* ti,otap-del-sel-legacy is mandatory */
342 ret = dev_read_u32(dev, "ti,otap-del-sel-legacy",
343 &plat->otap_del_sel[0]);
347 * Remove the corresponding capability if an otap-del-sel
350 for (i = MMC_HS; i <= MMC_HS_400; i++) {
351 ret = dev_read_u32(dev, td[i].binding, &plat->otap_del_sel[i]);
353 dev_dbg(dev, "Couldn't find %s\n", td[i].binding);
355 * Remove the corresponding capability
356 * if an otap-del-sel value is not found
358 cfg->host_caps &= ~td[i].capability;
365 static int am654_sdhci_probe(struct udevice *dev)
367 struct am654_driver_data *drv_data =
368 (struct am654_driver_data *)dev_get_driver_data(dev);
369 struct am654_sdhci_plat *plat = dev_get_platdata(dev);
370 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
371 struct sdhci_host *host = dev_get_priv(dev);
372 struct mmc_config *cfg = &plat->cfg;
377 ret = clk_get_by_name(dev, "clk_xin", &clk);
379 dev_err(dev, "failed to get clock\n");
383 clock = clk_get_rate(&clk);
384 if (IS_ERR_VALUE(clock)) {
385 dev_err(dev, "failed to get rate\n");
389 host->max_clk = clock;
390 host->mmc = &plat->mmc;
391 host->mmc->dev = dev;
392 ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
393 AM654_SDHCI_MIN_FREQ);
397 ret = sdhci_am654_get_otap_delay(dev, cfg);
401 host->ops = drv_data->ops;
402 host->mmc->priv = host;
403 upriv->mmc = host->mmc;
405 regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1);
410 static int am654_sdhci_ofdata_to_platdata(struct udevice *dev)
412 struct am654_sdhci_plat *plat = dev_get_platdata(dev);
413 struct sdhci_host *host = dev_get_priv(dev);
414 struct mmc_config *cfg = &plat->cfg;
418 host->name = dev->name;
419 host->ioaddr = (void *)dev_read_addr(dev);
420 plat->non_removable = dev_read_bool(dev, "non-removable");
422 if (plat->flags & DLL_PRESENT) {
423 ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp);
427 ret = dev_read_u32(dev, "ti,driver-strength-ohm",
432 switch (drv_strength) {
434 plat->drv_strength = DRIVER_STRENGTH_50_OHM;
437 plat->drv_strength = DRIVER_STRENGTH_33_OHM;
440 plat->drv_strength = DRIVER_STRENGTH_66_OHM;
443 plat->drv_strength = DRIVER_STRENGTH_100_OHM;
446 plat->drv_strength = DRIVER_STRENGTH_40_OHM;
449 dev_err(dev, "Invalid driver strength\n");
454 ret = mmc_of_parse(dev, cfg);
461 static int am654_sdhci_bind(struct udevice *dev)
463 struct am654_driver_data *drv_data =
464 (struct am654_driver_data *)dev_get_driver_data(dev);
465 struct am654_sdhci_plat *plat = dev_get_platdata(dev);
467 plat->flags = drv_data->flags;
469 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
472 static const struct udevice_id am654_sdhci_ids[] = {
474 .compatible = "ti,am654-sdhci-5.1",
475 .data = (ulong)&am654_drv_data,
478 .compatible = "ti,j721e-sdhci-8bit",
479 .data = (ulong)&j721e_8bit_drv_data,
482 .compatible = "ti,j721e-sdhci-4bit",
483 .data = (ulong)&j721e_4bit_drv_data,
488 U_BOOT_DRIVER(am654_sdhci_drv) = {
489 .name = "am654_sdhci",
491 .of_match = am654_sdhci_ids,
492 .ofdata_to_platdata = am654_sdhci_ofdata_to_platdata,
494 .bind = am654_sdhci_bind,
495 .probe = am654_sdhci_probe,
496 .priv_auto_alloc_size = sizeof(struct sdhci_host),
497 .platdata_auto_alloc_size = sizeof(struct am654_sdhci_plat),