1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
5 * Texas Instruments' K3 SD Host Controller Interface
12 #include <power-domain.h>
16 /* CTL_CFG Registers */
17 #define CTL_CFG_2 0x14
19 #define SLOTTYPE_MASK GENMASK(31, 30)
20 #define SLOTTYPE_EMBEDDED BIT(30)
23 #define PHY_CTRL1 0x100
24 #define PHY_CTRL2 0x104
25 #define PHY_CTRL3 0x108
26 #define PHY_CTRL4 0x10C
27 #define PHY_CTRL5 0x110
28 #define PHY_CTRL6 0x114
29 #define PHY_STAT1 0x130
30 #define PHY_STAT2 0x134
32 #define IOMUX_ENABLE_SHIFT 31
33 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
34 #define OTAPDLYENA_SHIFT 20
35 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
36 #define OTAPDLYSEL_SHIFT 12
37 #define OTAPDLYSEL_MASK GENMASK(15, 12)
38 #define STRBSEL_SHIFT 24
39 #define STRBSEL_MASK GENMASK(27, 24)
41 #define SEL50_MASK BIT(SEL50_SHIFT)
42 #define SEL100_SHIFT 9
43 #define SEL100_MASK BIT(SEL100_SHIFT)
44 #define DLL_TRIM_ICP_SHIFT 4
45 #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
46 #define DR_TY_SHIFT 20
47 #define DR_TY_MASK GENMASK(22, 20)
49 #define ENDLL_MASK BIT(ENDLL_SHIFT)
50 #define DLLRDY_SHIFT 0
51 #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
53 #define PDB_MASK BIT(PDB_SHIFT)
54 #define CALDONE_SHIFT 1
55 #define CALDONE_MASK BIT(CALDONE_SHIFT)
56 #define RETRIM_SHIFT 17
57 #define RETRIM_MASK BIT(RETRIM_SHIFT)
59 #define DRIVER_STRENGTH_50_OHM 0x0
60 #define DRIVER_STRENGTH_33_OHM 0x1
61 #define DRIVER_STRENGTH_66_OHM 0x2
62 #define DRIVER_STRENGTH_100_OHM 0x3
63 #define DRIVER_STRENGTH_40_OHM 0x4
65 #define AM654_SDHCI_MIN_FREQ 400000
67 struct am654_sdhci_plat {
68 struct mmc_config cfg;
76 #define DLL_PRESENT (1 << 0)
80 static void am654_sdhci_set_control_reg(struct sdhci_host *host)
82 struct mmc *mmc = (struct mmc *)host->mmc;
85 if (IS_SD(host->mmc) &&
86 mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
87 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
88 reg |= SDHCI_CTRL_VDD_180;
89 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
92 sdhci_set_uhs_timing(host);
95 static int am654_sdhci_set_ios_post(struct sdhci_host *host)
97 struct udevice *dev = host->mmc->dev;
98 struct am654_sdhci_plat *plat = dev_get_platdata(dev);
99 unsigned int speed = host->mmc->clock;
104 /* Reset SD Clock Enable */
105 val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
106 val &= ~SDHCI_CLOCK_CARD_EN;
107 sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
111 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
113 plat->dll_on = false;
117 sdhci_set_clock(host->mmc, speed);
119 /* switch phy back on */
120 if (speed > AM654_SDHCI_MIN_FREQ) {
121 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
122 val = (1 << OTAPDLYENA_SHIFT) |
123 (plat->otap_del_sel << OTAPDLYSEL_SHIFT);
124 regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
139 /* Configure PHY DLL frequency */
140 mask = SEL50_MASK | SEL100_MASK;
141 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
142 regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
145 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
148 * Poll for DLL ready. Use a one second timeout.
149 * Works in all experiments done so far
151 ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
152 val & DLLRDY_MASK, 1000, 1000000);
162 const struct sdhci_ops am654_sdhci_ops = {
163 .set_ios_post = &am654_sdhci_set_ios_post,
164 .set_control_reg = &am654_sdhci_set_control_reg,
167 const struct sdhci_ops j721e_4bit_sdhci_ops = {
168 .set_control_reg = &am654_sdhci_set_control_reg,
171 int am654_sdhci_init(struct am654_sdhci_plat *plat)
177 /* Reset OTAP to default value */
178 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
179 regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
181 if (plat->flags & DLL_PRESENT) {
182 regmap_read(plat->base, PHY_STAT1, &val);
183 if (~val & CALDONE_MASK) {
184 /* Calibrate IO lines */
185 regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK,
187 ret = regmap_read_poll_timeout(plat->base, PHY_STAT1,
188 val, val & CALDONE_MASK,
194 /* Configure DLL TRIM */
195 mask = DLL_TRIM_ICP_MASK;
196 val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
198 /* Configure DLL driver strength */
200 val |= plat->drv_strength << DR_TY_SHIFT;
201 regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
204 /* Enable pins by setting IO mux to 0 */
205 regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
207 /* Set slot type based on SD or eMMC */
208 if (plat->non_removable)
209 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
211 regmap_update_bits(plat->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2);
216 static int am654_sdhci_probe(struct udevice *dev)
218 struct am654_sdhci_plat *plat = dev_get_platdata(dev);
219 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
220 struct sdhci_host *host = dev_get_priv(dev);
221 struct mmc_config *cfg = &plat->cfg;
226 ret = clk_get_by_index(dev, 0, &clk);
228 dev_err(dev, "failed to get clock\n");
232 clock = clk_get_rate(&clk);
233 if (IS_ERR_VALUE(clock)) {
234 dev_err(dev, "failed to get rate\n");
238 host->max_clk = clock;
239 host->mmc = &plat->mmc;
240 host->mmc->dev = dev;
241 ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
242 AM654_SDHCI_MIN_FREQ);
245 host->ops = (struct sdhci_ops *)dev_get_driver_data(dev);
246 host->mmc->priv = host;
247 upriv->mmc = host->mmc;
249 regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1);
251 am654_sdhci_init(plat);
253 return sdhci_probe(dev);
256 static int am654_sdhci_ofdata_to_platdata(struct udevice *dev)
258 struct am654_sdhci_plat *plat = dev_get_platdata(dev);
259 struct sdhci_host *host = dev_get_priv(dev);
260 struct mmc_config *cfg = &plat->cfg;
264 host->name = dev->name;
265 host->ioaddr = (void *)dev_read_addr(dev);
266 plat->non_removable = dev_read_bool(dev, "non-removable");
268 if (device_is_compatible(dev, "ti,am654-sdhci-5.1") ||
269 device_is_compatible(dev, "ti,j721e-sdhci-8bit"))
270 plat->flags |= DLL_PRESENT;
272 ret = dev_read_u32(dev, "ti,otap-del-sel", &plat->otap_del_sel);
276 if (plat->flags & DLL_PRESENT) {
277 ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp);
281 ret = dev_read_u32(dev, "ti,driver-strength-ohm",
286 switch (drv_strength) {
288 plat->drv_strength = DRIVER_STRENGTH_50_OHM;
291 plat->drv_strength = DRIVER_STRENGTH_33_OHM;
294 plat->drv_strength = DRIVER_STRENGTH_66_OHM;
297 plat->drv_strength = DRIVER_STRENGTH_100_OHM;
300 plat->drv_strength = DRIVER_STRENGTH_40_OHM;
303 dev_err(dev, "Invalid driver strength\n");
308 ret = mmc_of_parse(dev, cfg);
315 static int am654_sdhci_bind(struct udevice *dev)
317 struct am654_sdhci_plat *plat = dev_get_platdata(dev);
319 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
322 static const struct udevice_id am654_sdhci_ids[] = {
324 .compatible = "ti,am654-sdhci-5.1",
325 .data = (ulong)&am654_sdhci_ops,
328 .compatible = "ti,j721e-sdhci-8bit",
329 .data = (ulong)&am654_sdhci_ops,
332 .compatible = "ti,j721e-sdhci-4bit",
333 .data = (ulong)&j721e_4bit_sdhci_ops,
338 U_BOOT_DRIVER(am654_sdhci_drv) = {
339 .name = "am654_sdhci",
341 .of_match = am654_sdhci_ids,
342 .ofdata_to_platdata = am654_sdhci_ofdata_to_platdata,
344 .bind = am654_sdhci_bind,
345 .probe = am654_sdhci_probe,
346 .priv_auto_alloc_size = sizeof(struct sdhci_host),
347 .platdata_auto_alloc_size = sizeof(struct am654_sdhci_plat),