drivers/mmc/am654_sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Texas Instruments' K3 SD Host Controller Interface
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <malloc.h>
  12 #include <power-domain.h>
  13 #include <regmap.h>
  14 #include <sdhci.h>
  15
  16 /* CTL_CFG Registers */
  17 #define CTL_CFG_2               0x14
  18
  19 #define SLOTTYPE_MASK           GENMASK(31, 30)
  20 #define SLOTTYPE_EMBEDDED       BIT(30)
  21
  22 /* PHY Registers */
  23 #define PHY_CTRL1       0x100
  24 #define PHY_CTRL2       0x104
  25 #define PHY_CTRL3       0x108
  26 #define PHY_CTRL4       0x10C
  27 #define PHY_CTRL5       0x110
  28 #define PHY_CTRL6       0x114
  29 #define PHY_STAT1       0x130
  30 #define PHY_STAT2       0x134
  31
  32 #define IOMUX_ENABLE_SHIFT      31
  33 #define IOMUX_ENABLE_MASK       BIT(IOMUX_ENABLE_SHIFT)
  34 #define OTAPDLYENA_SHIFT        20
  35 #define OTAPDLYENA_MASK         BIT(OTAPDLYENA_SHIFT)
  36 #define OTAPDLYSEL_SHIFT        12
  37 #define OTAPDLYSEL_MASK         GENMASK(15, 12)
  38 #define STRBSEL_SHIFT           24
  39 #define STRBSEL_4BIT_MASK       GENMASK(27, 24)
  40 #define STRBSEL_8BIT_MASK       GENMASK(31, 24)
  41 #define SEL50_SHIFT             8
  42 #define SEL50_MASK              BIT(SEL50_SHIFT)
  43 #define SEL100_SHIFT            9
  44 #define SEL100_MASK             BIT(SEL100_SHIFT)
  45 #define FREQSEL_SHIFT           8
  46 #define FREQSEL_MASK            GENMASK(10, 8)
  47 #define DLL_TRIM_ICP_SHIFT      4
  48 #define DLL_TRIM_ICP_MASK       GENMASK(7, 4)
  49 #define DR_TY_SHIFT             20
  50 #define DR_TY_MASK              GENMASK(22, 20)
  51 #define ENDLL_SHIFT             1
  52 #define ENDLL_MASK              BIT(ENDLL_SHIFT)
  53 #define DLLRDY_SHIFT            0
  54 #define DLLRDY_MASK             BIT(DLLRDY_SHIFT)
  55 #define PDB_SHIFT               0
  56 #define PDB_MASK                BIT(PDB_SHIFT)
  57 #define CALDONE_SHIFT           1
  58 #define CALDONE_MASK            BIT(CALDONE_SHIFT)
  59 #define RETRIM_SHIFT            17
  60 #define RETRIM_MASK             BIT(RETRIM_SHIFT)
  61
  62 #define DRIVER_STRENGTH_50_OHM  0x0
  63 #define DRIVER_STRENGTH_33_OHM  0x1
  64 #define DRIVER_STRENGTH_66_OHM  0x2
  65 #define DRIVER_STRENGTH_100_OHM 0x3
  66 #define DRIVER_STRENGTH_40_OHM  0x4
  67
  68 #define AM654_SDHCI_MIN_FREQ    400000
  69
  70 struct am654_sdhci_plat {
  71         struct mmc_config cfg;
  72         struct mmc mmc;
  73         struct regmap *base;
  74         bool non_removable;
  75         u32 otap_del_sel;
  76         u32 trm_icp;
  77         u32 drv_strength;
  78         u32 strb_sel;
  79         u32 flags;
  80 #define DLL_PRESENT     (1 << 0)
  81 #define IOMUX_PRESENT   (1 << 1)
  82 #define FREQSEL_2_BIT   (1 << 2)
  83 #define STRBSEL_4_BIT   (1 << 3)
  84         bool dll_on;
  85 };
  86
  87 struct am654_driver_data {
  88         const struct sdhci_ops *ops;
  89         u32 flags;
  90 };
  91
  92 static void am654_sdhci_set_control_reg(struct sdhci_host *host)
  93 {
  94         struct mmc *mmc = (struct mmc *)host->mmc;
  95         u32 reg;
  96
  97         if (IS_SD(host->mmc) &&
  98             mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  99                 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 100                 reg |= SDHCI_CTRL_VDD_180;
 101                 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 102         }
 103
 104         sdhci_set_uhs_timing(host);
 105 }
 106
 107 static int am654_sdhci_set_ios_post(struct sdhci_host *host)
 108 {
 109         struct udevice *dev = host->mmc->dev;
 110         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
 111         unsigned int speed = host->mmc->clock;
 112         int sel50, sel100, freqsel;
 113         u32 mask, val;
 114         int ret;
 115
 116         /* Reset SD Clock Enable */
 117         val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 118         val &= ~SDHCI_CLOCK_CARD_EN;
 119         sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
 120
 121         /* power off phy */
 122         if (plat->dll_on) {
 123                 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
 124
 125                 plat->dll_on = false;
 126         }
 127
 128         /* restart clock */
 129         sdhci_set_clock(host->mmc, speed);
 130
 131         /* switch phy back on */
 132         if (speed > AM654_SDHCI_MIN_FREQ) {
 133                 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 134                 val = (1 << OTAPDLYENA_SHIFT) |
 135                       (plat->otap_del_sel << OTAPDLYSEL_SHIFT);
 136
 137                 /* Write to STRBSEL for HS400 speed mode */
 138                 if (host->mmc->selected_mode == MMC_HS_400) {
 139                         if (plat->flags & STRBSEL_4_BIT)
 140                                 mask |= STRBSEL_4BIT_MASK;
 141                         else
 142                                 mask |= STRBSEL_8BIT_MASK;
 143
 144                         val |= plat->strb_sel << STRBSEL_SHIFT;
 145                 }
 146
 147                 regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
 148
 149                 if (plat->flags & FREQSEL_2_BIT) {
 150                         switch (speed) {
 151                         case 200000000:
 152                                 sel50 = 0;
 153                                 sel100 = 0;
 154                                 break;
 155                         case 100000000:
 156                                 sel50 = 0;
 157                                 sel100 = 1;
 158                                 break;
 159                         default:
 160                                 sel50 = 1;
 161                                 sel100 = 0;
 162                         }
 163
 164                         /* Configure PHY DLL frequency */
 165                         mask = SEL50_MASK | SEL100_MASK;
 166                         val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
 167                         regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
 168                 } else {
 169                         switch (speed) {
 170                         case 200000000:
 171                                 freqsel = 0x0;
 172                                 break;
 173                         default:
 174                                 freqsel = 0x4;
 175                         }
 176                         regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK,
 177                                            freqsel << FREQSEL_SHIFT);
 178                 }
 179
 180                 /* Enable DLL */
 181                 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
 182                                    0x1 << ENDLL_SHIFT);
 183                 /*
 184                  * Poll for DLL ready. Use a one second timeout.
 185                  * Works in all experiments done so far
 186                  */
 187                 ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
 188                                          val & DLLRDY_MASK, 1000, 1000000);
 189                 if (ret)
 190                         return ret;
 191
 192                 plat->dll_on = true;
 193         }
 194
 195         return 0;
 196 }
 197
 198 const struct sdhci_ops am654_sdhci_ops = {
 199         .set_ios_post           = &am654_sdhci_set_ios_post,
 200         .set_control_reg        = &am654_sdhci_set_control_reg,
 201 };
 202
 203 const struct am654_driver_data am654_drv_data = {
 204         .ops = &am654_sdhci_ops,
 205         .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | STRBSEL_4_BIT,
 206 };
 207
 208 const struct am654_driver_data j721e_8bit_drv_data = {
 209         .ops = &am654_sdhci_ops,
 210         .flags = DLL_PRESENT,
 211 };
 212
 213 static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
 214 {
 215         struct udevice *dev = host->mmc->dev;
 216         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
 217         u32 mask, val;
 218
 219         mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 220         val = (1 << OTAPDLYENA_SHIFT) |
 221               (plat->otap_del_sel << OTAPDLYSEL_SHIFT);
 222         regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
 223
 224         return 0;
 225 }
 226
 227 const struct sdhci_ops j721e_4bit_sdhci_ops = {
 228         .set_ios_post           = &j721e_4bit_sdhci_set_ios_post,
 229 };
 230
 231 const struct am654_driver_data j721e_4bit_drv_data = {
 232         .ops = &j721e_4bit_sdhci_ops,
 233         .flags = IOMUX_PRESENT,
 234 };
 235
 236 int am654_sdhci_init(struct am654_sdhci_plat *plat)
 237 {
 238         u32 ctl_cfg_2 = 0;
 239         u32 mask, val;
 240         int ret;
 241
 242         /* Reset OTAP to default value */
 243         mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 244         regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
 245
 246         if (plat->flags & DLL_PRESENT) {
 247                 regmap_read(plat->base, PHY_STAT1, &val);
 248                 if (~val & CALDONE_MASK) {
 249                         /* Calibrate IO lines */
 250                         regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK,
 251                                            PDB_MASK);
 252                         ret = regmap_read_poll_timeout(plat->base, PHY_STAT1,
 253                                                        val, val & CALDONE_MASK,
 254                                                        1, 20);
 255                         if (ret)
 256                                 return ret;
 257                 }
 258
 259                 /* Configure DLL TRIM */
 260                 mask = DLL_TRIM_ICP_MASK;
 261                 val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
 262
 263                 /* Configure DLL driver strength */
 264                 mask |= DR_TY_MASK;
 265                 val |= plat->drv_strength << DR_TY_SHIFT;
 266                 regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
 267         }
 268
 269         /* Enable pins by setting IO mux to 0 */
 270         if (plat->flags & IOMUX_PRESENT)
 271                 regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
 272
 273         /* Set slot type based on SD or eMMC */
 274         if (plat->non_removable)
 275                 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
 276
 277         regmap_update_bits(plat->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2);
 278
 279         return 0;
 280 }
 281
 282 static int am654_sdhci_probe(struct udevice *dev)
 283 {
 284         struct am654_driver_data *drv_data =
 285                         (struct am654_driver_data *)dev_get_driver_data(dev);
 286         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
 287         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 288         struct sdhci_host *host = dev_get_priv(dev);
 289         struct mmc_config *cfg = &plat->cfg;
 290         struct clk clk;
 291         unsigned long clock;
 292         int ret;
 293
 294         ret = clk_get_by_name(dev, "clk_xin", &clk);
 295         if (ret) {
 296                 dev_err(dev, "failed to get clock\n");
 297                 return ret;
 298         }
 299
 300         clock = clk_get_rate(&clk);
 301         if (IS_ERR_VALUE(clock)) {
 302                 dev_err(dev, "failed to get rate\n");
 303                 return clock;
 304         }
 305
 306         host->max_clk = clock;
 307         host->mmc = &plat->mmc;
 308         host->mmc->dev = dev;
 309         ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
 310                               AM654_SDHCI_MIN_FREQ);
 311         if (ret)
 312                 return ret;
 313
 314         host->ops = drv_data->ops;
 315         host->mmc->priv = host;
 316         upriv->mmc = host->mmc;
 317
 318         regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1);
 319
 320         am654_sdhci_init(plat);
 321
 322         return sdhci_probe(dev);
 323 }
 324
 325 static int am654_sdhci_ofdata_to_platdata(struct udevice *dev)
 326 {
 327         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
 328         struct sdhci_host *host = dev_get_priv(dev);
 329         struct mmc_config *cfg = &plat->cfg;
 330         u32 drv_strength;
 331         int ret;
 332
 333         host->name = dev->name;
 334         host->ioaddr = (void *)dev_read_addr(dev);
 335         plat->non_removable = dev_read_bool(dev, "non-removable");
 336
 337         ret = dev_read_u32(dev, "ti,otap-del-sel", &plat->otap_del_sel);
 338         if (ret)
 339                 return ret;
 340
 341         if (plat->flags & DLL_PRESENT) {
 342                 ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp);
 343                 if (ret)
 344                         return ret;
 345
 346                 ret = dev_read_u32(dev, "ti,driver-strength-ohm",
 347                                    &drv_strength);
 348                 if (ret)
 349                         return ret;
 350
 351                 switch (drv_strength) {
 352                 case 50:
 353                         plat->drv_strength = DRIVER_STRENGTH_50_OHM;
 354                         break;
 355                 case 33:
 356                         plat->drv_strength = DRIVER_STRENGTH_33_OHM;
 357                         break;
 358                 case 66:
 359                         plat->drv_strength = DRIVER_STRENGTH_66_OHM;
 360                         break;
 361                 case 100:
 362                         plat->drv_strength = DRIVER_STRENGTH_100_OHM;
 363                         break;
 364                 case 40:
 365                         plat->drv_strength = DRIVER_STRENGTH_40_OHM;
 366                         break;
 367                 default:
 368                         dev_err(dev, "Invalid driver strength\n");
 369                         return -EINVAL;
 370                 }
 371         }
 372
 373         ret = mmc_of_parse(dev, cfg);
 374         if (ret)
 375                 return ret;
 376
 377         return 0;
 378 }
 379
 380 static int am654_sdhci_bind(struct udevice *dev)
 381 {
 382         struct am654_driver_data *drv_data =
 383                         (struct am654_driver_data *)dev_get_driver_data(dev);
 384         struct am654_sdhci_plat *plat = dev_get_platdata(dev);
 385
 386         plat->flags = drv_data->flags;
 387
 388         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 389 }
 390
 391 static const struct udevice_id am654_sdhci_ids[] = {
 392         {
 393                 .compatible = "ti,am654-sdhci-5.1",
 394                 .data = (ulong)&am654_drv_data,
 395         },
 396         {
 397                 .compatible = "ti,j721e-sdhci-8bit",
 398                 .data = (ulong)&j721e_8bit_drv_data,
 399         },
 400         {
 401                 .compatible = "ti,j721e-sdhci-4bit",
 402                 .data = (ulong)&j721e_4bit_drv_data,
 403         },
 404         { }
 405 };
 406
 407 U_BOOT_DRIVER(am654_sdhci_drv) = {
 408         .name           = "am654_sdhci",
 409         .id             = UCLASS_MMC,
 410         .of_match       = am654_sdhci_ids,
 411         .ofdata_to_platdata = am654_sdhci_ofdata_to_platdata,
 412         .ops            = &sdhci_ops,
 413         .bind           = am654_sdhci_bind,
 414         .probe          = am654_sdhci_probe,
 415         .priv_auto_alloc_size = sizeof(struct sdhci_host),
 416         .platdata_auto_alloc_size = sizeof(struct am654_sdhci_plat),
 417 };