1 // SPDX-License-Identifier: GPL-2.0+
3 * PCI emulation device which swaps the case of text
5 * Copyright (c) 2014 Google, Inc
6 * Written by Simon Glass <sjg@chromium.org>
14 #include <linux/ctype.h>
17 * struct swap_case_platdata - platform data for this device
19 * @command: Current PCI command value
20 * @bar: Current base address values
22 struct swap_case_platdata {
28 MEM_TEXT_SIZE = 0x100,
37 static struct pci_bar {
41 { PCI_BASE_ADDRESS_SPACE_IO, 1 },
42 { PCI_BASE_ADDRESS_MEM_TYPE_32, MEM_TEXT_SIZE },
49 struct swap_case_priv {
51 char mem_text[MEM_TEXT_SIZE];
54 static int sandbox_swap_case_use_ea(const struct udevice *dev)
56 return !!ofnode_get_property(dev->node, "use-ea", NULL);
59 /* Please keep these macros in sync with ea_regs below */
60 #define PCI_CAP_ID_EA_SIZE (sizeof(ea_regs) + 4)
61 #define PCI_CAP_ID_EA_ENTRY_CNT 4
62 /* Hardcoded EA structure, excluding 1st DW. */
63 static const u32 ea_regs[] = {
64 /* BEI=0, ES=2, BAR0 32b Base + 32b MaxOffset, I/O space */
68 /* BEI=1, ES=2, BAR1 32b Base + 32b MaxOffset */
72 /* BEI=2, ES=3, BAR2 64b Base + 32b MaxOffset */
74 PCI_CAP_EA_BASE_LO2 | PCI_EA_IS_64,
77 /* BEI=4, ES=4, BAR4 64b Base + 64b MaxOffset */
79 PCI_CAP_EA_BASE_LO4 | PCI_EA_IS_64,
80 PCI_CAP_EA_SIZE_LO | PCI_EA_IS_64,
85 static int sandbox_swap_case_read_ea(const struct udevice *emul, uint offset,
86 ulong *valuep, enum pci_size_t size)
90 offset = offset - PCI_CAP_ID_EA_OFFSET - 4;
91 reg = ea_regs[offset >> 2];
92 reg >>= (offset % 4) * 8;
98 static int sandbox_swap_case_read_config(const struct udevice *emul,
99 uint offset, ulong *valuep,
100 enum pci_size_t size)
102 struct swap_case_platdata *plat = dev_get_platdata(emul);
105 * The content of the EA capability structure is handled elsewhere to
106 * keep the switch/case below sane
108 if (offset > PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT &&
109 offset < PCI_CAP_ID_EA_OFFSET + PCI_CAP_ID_EA_SIZE)
110 return sandbox_swap_case_read_ea(emul, offset, valuep, size);
114 *valuep = plat->command;
116 case PCI_HEADER_TYPE:
120 *valuep = SANDBOX_PCI_VENDOR_ID;
123 *valuep = SANDBOX_PCI_SWAP_CASE_EMUL_ID;
125 case PCI_CLASS_DEVICE:
126 if (size == PCI_SIZE_8) {
127 *valuep = SANDBOX_PCI_CLASS_SUB_CODE;
129 *valuep = (SANDBOX_PCI_CLASS_CODE << 8) |
130 SANDBOX_PCI_CLASS_SUB_CODE;
134 *valuep = SANDBOX_PCI_CLASS_CODE;
136 case PCI_BASE_ADDRESS_0:
137 case PCI_BASE_ADDRESS_1:
138 case PCI_BASE_ADDRESS_2:
139 case PCI_BASE_ADDRESS_3:
140 case PCI_BASE_ADDRESS_4:
141 case PCI_BASE_ADDRESS_5: {
145 barnum = pci_offset_to_barnum(offset);
146 bar = &plat->bar[barnum];
148 *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type,
149 barinfo[barnum].size);
152 case PCI_CAPABILITY_LIST:
153 *valuep = PCI_CAP_ID_PM_OFFSET;
155 case PCI_CAP_ID_PM_OFFSET:
156 *valuep = (PCI_CAP_ID_EXP_OFFSET << 8) | PCI_CAP_ID_PM;
158 case PCI_CAP_ID_PM_OFFSET + PCI_CAP_LIST_NEXT:
159 *valuep = PCI_CAP_ID_EXP_OFFSET;
161 case PCI_CAP_ID_EXP_OFFSET:
162 *valuep = (PCI_CAP_ID_MSIX_OFFSET << 8) | PCI_CAP_ID_EXP;
164 case PCI_CAP_ID_EXP_OFFSET + PCI_CAP_LIST_NEXT:
165 *valuep = PCI_CAP_ID_MSIX_OFFSET;
167 case PCI_CAP_ID_MSIX_OFFSET:
168 if (sandbox_swap_case_use_ea(emul))
169 *valuep = (PCI_CAP_ID_EA_OFFSET << 8) | PCI_CAP_ID_MSIX;
171 *valuep = PCI_CAP_ID_MSIX;
173 case PCI_CAP_ID_MSIX_OFFSET + PCI_CAP_LIST_NEXT:
174 if (sandbox_swap_case_use_ea(emul))
175 *valuep = PCI_CAP_ID_EA_OFFSET;
179 case PCI_CAP_ID_EA_OFFSET:
180 *valuep = (PCI_CAP_ID_EA_ENTRY_CNT << 16) | PCI_CAP_ID_EA;
182 case PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT:
185 case PCI_EXT_CAP_ID_ERR_OFFSET:
186 *valuep = (PCI_EXT_CAP_ID_VC_OFFSET << 20) | PCI_EXT_CAP_ID_ERR;
188 case PCI_EXT_CAP_ID_VC_OFFSET:
189 *valuep = (PCI_EXT_CAP_ID_DSN_OFFSET << 20) | PCI_EXT_CAP_ID_VC;
191 case PCI_EXT_CAP_ID_DSN_OFFSET:
192 *valuep = PCI_EXT_CAP_ID_DSN;
199 static int sandbox_swap_case_write_config(struct udevice *emul, uint offset,
200 ulong value, enum pci_size_t size)
202 struct swap_case_platdata *plat = dev_get_platdata(emul);
206 plat->command = value;
208 case PCI_BASE_ADDRESS_0:
209 case PCI_BASE_ADDRESS_1: {
213 barnum = pci_offset_to_barnum(offset);
214 bar = &plat->bar[barnum];
216 debug("w bar %d=%lx\n", barnum, value);
218 /* space indicator (bit#0) is read-only */
219 *bar |= barinfo[barnum].type;
227 static int sandbox_swap_case_find_bar(struct udevice *emul, unsigned int addr,
228 int *barnump, unsigned int *offsetp)
230 struct swap_case_platdata *plat = dev_get_platdata(emul);
233 for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
234 unsigned int size = barinfo[barnum].size;
235 u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE;
237 if (addr >= base && addr < base + size) {
239 *offsetp = addr - base;
248 static void sandbox_swap_case_do_op(enum swap_case_op op, char *str, int len)
250 for (; len > 0; len--, str++) {
253 *str = toupper(*str);
256 *str = tolower(*str);
260 *str = tolower(*str);
262 *str = toupper(*str);
268 static int sandbox_swap_case_read_io(struct udevice *dev, unsigned int addr,
269 ulong *valuep, enum pci_size_t size)
271 struct swap_case_priv *priv = dev_get_priv(dev);
276 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
280 if (barnum == 0 && offset == 0)
281 *valuep = (*valuep & ~0xff) | priv->op;
286 static int sandbox_swap_case_write_io(struct udevice *dev, unsigned int addr,
287 ulong value, enum pci_size_t size)
289 struct swap_case_priv *priv = dev_get_priv(dev);
294 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
297 if (barnum == 0 && offset == 0)
303 static int pci_ea_bar2_magic = PCI_EA_BAR2_MAGIC;
304 static int pci_ea_bar4_magic = PCI_EA_BAR4_MAGIC;
306 static int sandbox_swap_case_map_physmem(struct udevice *dev,
307 phys_addr_t addr, unsigned long *lenp, void **ptrp)
309 struct swap_case_priv *priv = dev_get_priv(dev);
310 unsigned int offset, avail;
314 if (sandbox_swap_case_use_ea(dev)) {
316 * only support mapping base address in EA test for now, we
317 * don't handle mapping an offset inside a BAR. Seems good
318 * enough for the current test.
321 case (phys_addr_t)PCI_CAP_EA_BASE_LO0:
325 case (phys_addr_t)PCI_CAP_EA_BASE_LO1:
326 *ptrp = priv->mem_text;
327 *lenp = barinfo[1].size - 1;
329 case (phys_addr_t)((PCI_CAP_EA_BASE_HI2 << 32) |
330 PCI_CAP_EA_BASE_LO2):
331 *ptrp = &pci_ea_bar2_magic;
332 *lenp = PCI_CAP_EA_SIZE_LO;
334 case (phys_addr_t)((PCI_CAP_EA_BASE_HI4 << 32) |
335 PCI_CAP_EA_BASE_LO4):
336 *ptrp = &pci_ea_bar4_magic;
337 *lenp = (PCI_CAP_EA_SIZE_HI << 32) |
346 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
351 *ptrp = priv->mem_text + offset;
352 avail = barinfo[1].size - offset;
353 if (avail > barinfo[1].size)
356 *lenp = min(*lenp, (ulong)avail);
364 static int sandbox_swap_case_unmap_physmem(struct udevice *dev,
365 const void *vaddr, unsigned long len)
367 struct swap_case_priv *priv = dev_get_priv(dev);
369 sandbox_swap_case_do_op(priv->op, (void *)vaddr, len);
374 static struct dm_pci_emul_ops sandbox_swap_case_emul_ops = {
375 .read_config = sandbox_swap_case_read_config,
376 .write_config = sandbox_swap_case_write_config,
377 .read_io = sandbox_swap_case_read_io,
378 .write_io = sandbox_swap_case_write_io,
379 .map_physmem = sandbox_swap_case_map_physmem,
380 .unmap_physmem = sandbox_swap_case_unmap_physmem,
383 static const struct udevice_id sandbox_swap_case_ids[] = {
384 { .compatible = "sandbox,swap-case" },
388 U_BOOT_DRIVER(sandbox_swap_case_emul) = {
389 .name = "sandbox_swap_case_emul",
390 .id = UCLASS_PCI_EMUL,
391 .of_match = sandbox_swap_case_ids,
392 .ops = &sandbox_swap_case_emul_ops,
393 .priv_auto_alloc_size = sizeof(struct swap_case_priv),
394 .platdata_auto_alloc_size = sizeof(struct swap_case_platdata),
397 static struct pci_device_id sandbox_swap_case_supported[] = {
398 { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_SWAP_CASE_EMUL_ID),
399 SWAP_CASE_DRV_DATA },
403 U_BOOT_PCI_DEVICE(sandbox_swap_case_emul, sandbox_swap_case_supported);