1 // SPDX-License-Identifier: GPL-2.0+
3 * PCI emulation device which swaps the case of text
5 * Copyright (c) 2014 Google, Inc
6 * Written by Simon Glass <sjg@chromium.org>
14 #include <linux/ctype.h>
17 * struct swap_case_platdata - platform data for this device
19 * @command: Current PCI command value
20 * @bar: Current base address values
22 struct swap_case_platdata {
27 #define offset_to_barnum(offset) \
28 (((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32))
31 MEM_TEXT_SIZE = 0x100,
40 static struct pci_bar {
44 { PCI_BASE_ADDRESS_SPACE_IO, 1 },
45 { PCI_BASE_ADDRESS_MEM_TYPE_32, MEM_TEXT_SIZE },
52 struct swap_case_priv {
54 char mem_text[MEM_TEXT_SIZE];
57 static int sandbox_swap_case_get_devfn(struct udevice *dev)
59 struct pci_child_platdata *plat = dev_get_parent_platdata(dev);
64 static int sandbox_swap_case_use_ea(struct udevice *dev)
66 return !!ofnode_get_property(dev->node, "use-ea", NULL);
69 /* Please keep these macros in sync with ea_regs below */
70 #define PCI_CAP_ID_EA_SIZE (sizeof(ea_regs) + 4)
71 #define PCI_CAP_ID_EA_ENTRY_CNT 4
72 /* Hardcoded EA structure, excluding 1st DW. */
73 static const u32 ea_regs[] = {
74 /* BEI=0, ES=2, BAR0 32b Base + 32b MaxOffset, I/O space */
78 /* BEI=1, ES=2, BAR1 32b Base + 32b MaxOffset */
82 /* BEI=2, ES=3, BAR2 64b Base + 32b MaxOffset */
84 PCI_CAP_EA_BASE_LO2 | PCI_EA_IS_64,
87 /* BEI=4, ES=4, BAR4 64b Base + 64b MaxOffset */
89 PCI_CAP_EA_BASE_LO4 | PCI_EA_IS_64,
90 PCI_CAP_EA_SIZE_LO | PCI_EA_IS_64,
95 static int sandbox_swap_case_read_ea(struct udevice *emul, uint offset,
96 ulong *valuep, enum pci_size_t size)
100 offset = offset - PCI_CAP_ID_EA_OFFSET - 4;
101 reg = ea_regs[offset >> 2];
102 reg >>= (offset % 4) * 8;
108 static int sandbox_swap_case_read_config(struct udevice *emul, uint offset,
109 ulong *valuep, enum pci_size_t size)
111 struct swap_case_platdata *plat = dev_get_platdata(emul);
114 * The content of the EA capability structure is handled elsewhere to
115 * keep the switch/case below sane
117 if (offset > PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT &&
118 offset < PCI_CAP_ID_EA_OFFSET + PCI_CAP_ID_EA_SIZE)
119 return sandbox_swap_case_read_ea(emul, offset, valuep, size);
123 *valuep = plat->command;
125 case PCI_HEADER_TYPE:
129 *valuep = SANDBOX_PCI_VENDOR_ID;
132 *valuep = SANDBOX_PCI_SWAP_CASE_EMUL_ID;
134 case PCI_CLASS_DEVICE:
135 if (size == PCI_SIZE_8) {
136 *valuep = SANDBOX_PCI_CLASS_SUB_CODE;
138 *valuep = (SANDBOX_PCI_CLASS_CODE << 8) |
139 SANDBOX_PCI_CLASS_SUB_CODE;
143 *valuep = SANDBOX_PCI_CLASS_CODE;
145 case PCI_BASE_ADDRESS_0:
146 case PCI_BASE_ADDRESS_1:
147 case PCI_BASE_ADDRESS_2:
148 case PCI_BASE_ADDRESS_3:
149 case PCI_BASE_ADDRESS_4:
150 case PCI_BASE_ADDRESS_5: {
154 barnum = offset_to_barnum(offset);
155 bar = &plat->bar[barnum];
158 if (*bar == 0xffffffff) {
159 if (barinfo[barnum].type) {
160 result = (~(barinfo[barnum].size - 1) &
161 PCI_BASE_ADDRESS_IO_MASK) |
162 PCI_BASE_ADDRESS_SPACE_IO;
164 result = (~(barinfo[barnum].size - 1) &
165 PCI_BASE_ADDRESS_MEM_MASK) |
166 PCI_BASE_ADDRESS_MEM_TYPE_32;
169 debug("r bar %d=%x\n", barnum, result);
173 case PCI_CAPABILITY_LIST:
174 *valuep = PCI_CAP_ID_PM_OFFSET;
176 case PCI_CAP_ID_PM_OFFSET:
177 *valuep = (PCI_CAP_ID_EXP_OFFSET << 8) | PCI_CAP_ID_PM;
179 case PCI_CAP_ID_PM_OFFSET + PCI_CAP_LIST_NEXT:
180 *valuep = PCI_CAP_ID_EXP_OFFSET;
182 case PCI_CAP_ID_EXP_OFFSET:
183 *valuep = (PCI_CAP_ID_MSIX_OFFSET << 8) | PCI_CAP_ID_EXP;
185 case PCI_CAP_ID_EXP_OFFSET + PCI_CAP_LIST_NEXT:
186 *valuep = PCI_CAP_ID_MSIX_OFFSET;
188 case PCI_CAP_ID_MSIX_OFFSET:
189 if (sandbox_swap_case_use_ea(emul))
190 *valuep = (PCI_CAP_ID_EA_OFFSET << 8) | PCI_CAP_ID_MSIX;
192 *valuep = PCI_CAP_ID_MSIX;
194 case PCI_CAP_ID_MSIX_OFFSET + PCI_CAP_LIST_NEXT:
195 if (sandbox_swap_case_use_ea(emul))
196 *valuep = PCI_CAP_ID_EA_OFFSET;
200 case PCI_CAP_ID_EA_OFFSET:
201 *valuep = (PCI_CAP_ID_EA_ENTRY_CNT << 16) | PCI_CAP_ID_EA;
203 case PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT:
206 case PCI_EXT_CAP_ID_ERR_OFFSET:
207 *valuep = (PCI_EXT_CAP_ID_VC_OFFSET << 20) | PCI_EXT_CAP_ID_ERR;
209 case PCI_EXT_CAP_ID_VC_OFFSET:
210 *valuep = (PCI_EXT_CAP_ID_DSN_OFFSET << 20) | PCI_EXT_CAP_ID_VC;
212 case PCI_EXT_CAP_ID_DSN_OFFSET:
213 *valuep = PCI_EXT_CAP_ID_DSN;
220 static int sandbox_swap_case_write_config(struct udevice *emul, uint offset,
221 ulong value, enum pci_size_t size)
223 struct swap_case_platdata *plat = dev_get_platdata(emul);
227 plat->command = value;
229 case PCI_BASE_ADDRESS_0:
230 case PCI_BASE_ADDRESS_1: {
234 barnum = offset_to_barnum(offset);
235 bar = &plat->bar[barnum];
237 debug("w bar %d=%lx\n", barnum, value);
239 /* space indicator (bit#0) is read-only */
240 *bar |= barinfo[barnum].type;
248 static int sandbox_swap_case_find_bar(struct udevice *emul, unsigned int addr,
249 int *barnump, unsigned int *offsetp)
251 struct swap_case_platdata *plat = dev_get_platdata(emul);
254 for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
255 unsigned int size = barinfo[barnum].size;
256 u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE;
258 if (addr >= base && addr < base + size) {
260 *offsetp = addr - base;
269 static void sandbox_swap_case_do_op(enum swap_case_op op, char *str, int len)
271 for (; len > 0; len--, str++) {
274 *str = toupper(*str);
277 *str = tolower(*str);
281 *str = tolower(*str);
283 *str = toupper(*str);
289 int sandbox_swap_case_read_io(struct udevice *dev, unsigned int addr,
290 ulong *valuep, enum pci_size_t size)
292 struct swap_case_priv *priv = dev_get_priv(dev);
297 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
301 if (barnum == 0 && offset == 0)
302 *valuep = (*valuep & ~0xff) | priv->op;
307 int sandbox_swap_case_write_io(struct udevice *dev, unsigned int addr,
308 ulong value, enum pci_size_t size)
310 struct swap_case_priv *priv = dev_get_priv(dev);
315 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
318 if (barnum == 0 && offset == 0)
324 static int pci_ea_bar2_magic = PCI_EA_BAR2_MAGIC;
325 static int pci_ea_bar4_magic = PCI_EA_BAR4_MAGIC;
327 static int sandbox_swap_case_map_physmem(struct udevice *dev,
328 phys_addr_t addr, unsigned long *lenp, void **ptrp)
330 struct swap_case_priv *priv = dev_get_priv(dev);
331 unsigned int offset, avail;
335 if (sandbox_swap_case_use_ea(dev)) {
337 * only support mapping base address in EA test for now, we
338 * don't handle mapping an offset inside a BAR. Seems good
339 * enough for the current test.
342 case (phys_addr_t)PCI_CAP_EA_BASE_LO0:
346 case (phys_addr_t)PCI_CAP_EA_BASE_LO1:
347 *ptrp = priv->mem_text;
348 *lenp = barinfo[1].size - 1;
350 case (phys_addr_t)((PCI_CAP_EA_BASE_HI2 << 32) |
351 PCI_CAP_EA_BASE_LO2):
352 *ptrp = &pci_ea_bar2_magic;
353 *lenp = PCI_CAP_EA_SIZE_LO;
355 case (phys_addr_t)((PCI_CAP_EA_BASE_HI4 << 32) |
356 PCI_CAP_EA_BASE_LO4):
357 *ptrp = &pci_ea_bar4_magic;
358 *lenp = (PCI_CAP_EA_SIZE_HI << 32) |
367 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
372 *ptrp = priv->mem_text + offset;
373 avail = barinfo[1].size - offset;
374 if (avail > barinfo[1].size)
377 *lenp = min(*lenp, (ulong)avail);
385 static int sandbox_swap_case_unmap_physmem(struct udevice *dev,
386 const void *vaddr, unsigned long len)
388 struct swap_case_priv *priv = dev_get_priv(dev);
390 sandbox_swap_case_do_op(priv->op, (void *)vaddr, len);
395 struct dm_pci_emul_ops sandbox_swap_case_emul_ops = {
396 .get_devfn = sandbox_swap_case_get_devfn,
397 .read_config = sandbox_swap_case_read_config,
398 .write_config = sandbox_swap_case_write_config,
399 .read_io = sandbox_swap_case_read_io,
400 .write_io = sandbox_swap_case_write_io,
401 .map_physmem = sandbox_swap_case_map_physmem,
402 .unmap_physmem = sandbox_swap_case_unmap_physmem,
405 static const struct udevice_id sandbox_swap_case_ids[] = {
406 { .compatible = "sandbox,swap-case" },
410 U_BOOT_DRIVER(sandbox_swap_case_emul) = {
411 .name = "sandbox_swap_case_emul",
412 .id = UCLASS_PCI_EMUL,
413 .of_match = sandbox_swap_case_ids,
414 .ops = &sandbox_swap_case_emul_ops,
415 .priv_auto_alloc_size = sizeof(struct swap_case_priv),
416 .platdata_auto_alloc_size = sizeof(struct swap_case_platdata),
419 static struct pci_device_id sandbox_swap_case_supported[] = {
420 { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_SWAP_CASE_EMUL_ID),
421 SWAP_CASE_DRV_DATA },
425 U_BOOT_PCI_DEVICE(sandbox_swap_case_emul, sandbox_swap_case_supported);