1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2017 IBM Corp.
4 #include <asm/pnv-ocxl.h>
5 #include <misc/ocxl-config.h>
6 #include "ocxl_internal.h"
8 #define EXTRACT_BIT(val, bit) (!!(val & BIT(bit)))
9 #define EXTRACT_BITS(val, s, e) ((val & GENMASK(e, s)) >> s)
11 #define OCXL_DVSEC_AFU_IDX_MASK GENMASK(5, 0)
12 #define OCXL_DVSEC_ACTAG_MASK GENMASK(11, 0)
13 #define OCXL_DVSEC_PASID_MASK GENMASK(19, 0)
14 #define OCXL_DVSEC_PASID_LOG_MASK GENMASK(4, 0)
16 #define OCXL_DVSEC_TEMPL_VERSION 0x0
17 #define OCXL_DVSEC_TEMPL_NAME 0x4
18 #define OCXL_DVSEC_TEMPL_AFU_VERSION 0x1C
19 #define OCXL_DVSEC_TEMPL_MMIO_GLOBAL 0x20
20 #define OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ 0x28
21 #define OCXL_DVSEC_TEMPL_MMIO_PP 0x30
22 #define OCXL_DVSEC_TEMPL_MMIO_PP_SZ 0x38
23 #define OCXL_DVSEC_TEMPL_ALL_MEM_SZ 0x3C
24 #define OCXL_DVSEC_TEMPL_LPC_MEM_START 0x40
25 #define OCXL_DVSEC_TEMPL_WWID 0x48
26 #define OCXL_DVSEC_TEMPL_LPC_MEM_SZ 0x58
28 #define OCXL_MAX_AFU_PER_FUNCTION 64
29 #define OCXL_TEMPL_LEN_1_0 0x58
30 #define OCXL_TEMPL_LEN_1_1 0x60
31 #define OCXL_TEMPL_NAME_LEN 24
32 #define OCXL_CFG_TIMEOUT 3
34 static int find_dvsec(struct pci_dev *dev, int dvsec_id)
39 while ((vsec = pci_find_next_ext_capability(dev, vsec,
40 OCXL_EXT_CAP_ID_DVSEC))) {
41 pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
43 pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
44 if (vendor == PCI_VENDOR_ID_IBM && id == dvsec_id)
50 static int find_dvsec_afu_ctrl(struct pci_dev *dev, u8 afu_idx)
56 while ((vsec = pci_find_next_ext_capability(dev, vsec,
57 OCXL_EXT_CAP_ID_DVSEC))) {
58 pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
60 pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
62 if (vendor == PCI_VENDOR_ID_IBM &&
63 id == OCXL_DVSEC_AFU_CTRL_ID) {
64 pci_read_config_byte(dev,
65 vsec + OCXL_DVSEC_AFU_CTRL_AFU_IDX,
74 static void read_pasid(struct pci_dev *dev, struct ocxl_fn_config *fn)
79 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PASID);
82 * PASID capability is not mandatory, but there
83 * shouldn't be any AFU
85 dev_dbg(&dev->dev, "Function doesn't require any PASID\n");
86 fn->max_pasid_log = -1;
89 pci_read_config_word(dev, pos + PCI_PASID_CAP, &val);
90 fn->max_pasid_log = EXTRACT_BITS(val, 8, 12);
93 dev_dbg(&dev->dev, "PASID capability:\n");
94 dev_dbg(&dev->dev, " Max PASID log = %d\n", fn->max_pasid_log);
97 static int read_dvsec_tl(struct pci_dev *dev, struct ocxl_fn_config *fn)
101 pos = find_dvsec(dev, OCXL_DVSEC_TL_ID);
102 if (!pos && PCI_FUNC(dev->devfn) == 0) {
103 dev_err(&dev->dev, "Can't find TL DVSEC\n");
106 if (pos && PCI_FUNC(dev->devfn) != 0) {
107 dev_err(&dev->dev, "TL DVSEC is only allowed on function 0\n");
110 fn->dvsec_tl_pos = pos;
114 static int read_dvsec_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
116 int pos, afu_present;
119 pos = find_dvsec(dev, OCXL_DVSEC_FUNC_ID);
121 dev_err(&dev->dev, "Can't find function DVSEC\n");
124 fn->dvsec_function_pos = pos;
126 pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val);
127 afu_present = EXTRACT_BIT(val, 31);
129 fn->max_afu_index = -1;
130 dev_dbg(&dev->dev, "Function doesn't define any AFU\n");
133 fn->max_afu_index = EXTRACT_BITS(val, 24, 29);
136 dev_dbg(&dev->dev, "Function DVSEC:\n");
137 dev_dbg(&dev->dev, " Max AFU index = %d\n", fn->max_afu_index);
141 static int read_dvsec_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn)
145 if (fn->max_afu_index < 0) {
146 fn->dvsec_afu_info_pos = -1;
150 pos = find_dvsec(dev, OCXL_DVSEC_AFU_INFO_ID);
152 dev_err(&dev->dev, "Can't find AFU information DVSEC\n");
155 fn->dvsec_afu_info_pos = pos;
159 static int read_dvsec_vendor(struct pci_dev *dev)
165 * vendor specific DVSEC is optional
167 * It's currently only used on function 0 to specify the
168 * version of some logic blocks. Some older images may not
169 * even have it so we ignore any errors
171 if (PCI_FUNC(dev->devfn) != 0)
174 pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID);
178 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_CFG_VERS, &cfg);
179 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_TLX_VERS, &tlx);
180 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_DLX_VERS, &dlx);
182 dev_dbg(&dev->dev, "Vendor specific DVSEC:\n");
183 dev_dbg(&dev->dev, " CFG version = 0x%x\n", cfg);
184 dev_dbg(&dev->dev, " TLX version = 0x%x\n", tlx);
185 dev_dbg(&dev->dev, " DLX version = 0x%x\n", dlx);
189 static int validate_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
191 if (fn->max_pasid_log == -1 && fn->max_afu_index >= 0) {
193 "AFUs are defined but no PASIDs are requested\n");
197 if (fn->max_afu_index > OCXL_MAX_AFU_PER_FUNCTION) {
199 "Max AFU index out of architectural limit (%d vs %d)\n",
200 fn->max_afu_index, OCXL_MAX_AFU_PER_FUNCTION);
206 int ocxl_config_read_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
212 rc = read_dvsec_tl(dev, fn);
215 "Invalid Transaction Layer DVSEC configuration: %d\n",
220 rc = read_dvsec_function(dev, fn);
223 "Invalid Function DVSEC configuration: %d\n", rc);
227 rc = read_dvsec_afu_info(dev, fn);
229 dev_err(&dev->dev, "Invalid AFU configuration: %d\n", rc);
233 rc = read_dvsec_vendor(dev);
236 "Invalid vendor specific DVSEC configuration: %d\n",
241 rc = validate_function(dev, fn);
244 EXPORT_SYMBOL_GPL(ocxl_config_read_function);
246 static int read_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn,
247 int offset, u32 *data)
250 unsigned long timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT);
251 int pos = fn->dvsec_afu_info_pos;
253 /* Protect 'data valid' bit */
254 if (EXTRACT_BIT(offset, 31)) {
255 dev_err(&dev->dev, "Invalid offset in AFU info DVSEC\n");
259 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, offset);
260 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
261 while (!EXTRACT_BIT(val, 31)) {
262 if (time_after_eq(jiffies, timeout)) {
264 "Timeout while reading AFU info DVSEC (offset=%d)\n",
269 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
271 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_DATA, data);
276 * Read the template version from the AFU
277 * dev: the device for the AFU
278 * fn: the AFU offsets
279 * len: outputs the template length
280 * version: outputs the major<<8,minor version
282 * Returns 0 on success, negative on failure
284 static int read_template_version(struct pci_dev *dev, struct ocxl_fn_config *fn,
285 u16 *len, u16 *version)
291 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_VERSION, &val32);
295 *len = EXTRACT_BITS(val32, 16, 31);
296 major = EXTRACT_BITS(val32, 8, 15);
297 minor = EXTRACT_BITS(val32, 0, 7);
298 *version = (major << 8) + minor;
302 int ocxl_config_check_afu_index(struct pci_dev *dev,
303 struct ocxl_fn_config *fn, int afu_idx)
307 u16 len, expected_len;
309 pci_write_config_byte(dev,
310 fn->dvsec_afu_info_pos + OCXL_DVSEC_AFU_INFO_AFU_IDX,
313 rc = read_template_version(dev, fn, &len, &templ_version);
317 /* AFU index map can have holes, in which case we read all 0's */
318 if (!templ_version && !len)
321 dev_dbg(&dev->dev, "AFU descriptor template version %d.%d\n",
322 templ_version >> 8, templ_version & 0xFF);
324 switch (templ_version) {
325 case 0x0005: // v0.5 was used prior to the spec approval
327 expected_len = OCXL_TEMPL_LEN_1_0;
330 expected_len = OCXL_TEMPL_LEN_1_1;
333 dev_warn(&dev->dev, "Unknown AFU template version %#x\n",
337 if (len != expected_len)
339 "Unexpected template length %#x in AFU information, expected %#x for version %#x\n",
340 len, expected_len, templ_version);
344 static int read_afu_name(struct pci_dev *dev, struct ocxl_fn_config *fn,
345 struct ocxl_afu_config *afu)
350 BUILD_BUG_ON(OCXL_AFU_NAME_SZ < OCXL_TEMPL_NAME_LEN);
351 for (i = 0; i < OCXL_TEMPL_NAME_LEN; i += 4) {
352 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_NAME + i, &val);
355 ptr = (u32 *) &afu->name[i];
356 *ptr = le32_to_cpu((__force __le32) val);
358 afu->name[OCXL_AFU_NAME_SZ - 1] = '\0'; /* play safe */
362 static int read_afu_mmio(struct pci_dev *dev, struct ocxl_fn_config *fn,
363 struct ocxl_afu_config *afu)
371 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL, &val);
374 afu->global_mmio_bar = EXTRACT_BITS(val, 0, 2);
375 afu->global_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
377 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL + 4, &val);
380 afu->global_mmio_offset += (u64) val << 32;
382 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ, &val);
385 afu->global_mmio_size = val;
390 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP, &val);
393 afu->pp_mmio_bar = EXTRACT_BITS(val, 0, 2);
394 afu->pp_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
396 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP + 4, &val);
399 afu->pp_mmio_offset += (u64) val << 32;
401 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP_SZ, &val);
404 afu->pp_mmio_stride = val;
409 static int read_afu_control(struct pci_dev *dev, struct ocxl_afu_config *afu)
415 pos = find_dvsec_afu_ctrl(dev, afu->idx);
417 dev_err(&dev->dev, "Can't find AFU control DVSEC for AFU %d\n",
421 afu->dvsec_afu_control_pos = pos;
423 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_SUP, &val8);
424 afu->pasid_supported_log = EXTRACT_BITS(val8, 0, 4);
426 pci_read_config_word(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_SUP, &val16);
427 afu->actag_supported = EXTRACT_BITS(val16, 0, 11);
431 static bool char_allowed(int c)
434 * Permitted Characters : Alphanumeric, hyphen, underscore, comma
436 if ((c >= 0x30 && c <= 0x39) /* digits */ ||
437 (c >= 0x41 && c <= 0x5A) /* upper case */ ||
438 (c >= 0x61 && c <= 0x7A) /* lower case */ ||
447 static int validate_afu(struct pci_dev *dev, struct ocxl_afu_config *afu)
452 dev_err(&dev->dev, "Empty AFU name\n");
455 for (i = 0; i < OCXL_TEMPL_NAME_LEN; i++) {
456 if (!char_allowed(afu->name[i])) {
458 "Invalid character in AFU name\n");
463 if (afu->global_mmio_bar != 0 &&
464 afu->global_mmio_bar != 2 &&
465 afu->global_mmio_bar != 4) {
466 dev_err(&dev->dev, "Invalid global MMIO bar number\n");
469 if (afu->pp_mmio_bar != 0 &&
470 afu->pp_mmio_bar != 2 &&
471 afu->pp_mmio_bar != 4) {
472 dev_err(&dev->dev, "Invalid per-process MMIO bar number\n");
479 * Populate AFU metadata regarding LPC memory
480 * dev: the device for the AFU
481 * fn: the AFU offsets
482 * afu: the AFU struct to populate the LPC metadata into
484 * Returns 0 on success, negative on failure
486 static int read_afu_lpc_memory_info(struct pci_dev *dev,
487 struct ocxl_fn_config *fn,
488 struct ocxl_afu_config *afu)
494 u64 total_mem_size = 0;
495 u64 lpc_mem_size = 0;
497 afu->lpc_mem_offset = 0;
498 afu->lpc_mem_size = 0;
499 afu->special_purpose_mem_offset = 0;
500 afu->special_purpose_mem_size = 0;
502 * For AFUs following template v1.0, the LPC memory covers the
503 * total memory. Its size is a power of 2.
505 * For AFUs with template >= v1.01, the total memory size is
506 * still a power of 2, but it is split in 2 parts:
507 * - the LPC memory, whose size can now be anything
508 * - the remainder memory is a special purpose memory, whose
509 * definition is AFU-dependent. It is not accessible through
510 * the usual commands for LPC memory
512 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_ALL_MEM_SZ, &val32);
516 val32 = EXTRACT_BITS(val32, 0, 7);
518 return 0; /* No LPC memory */
521 * The configuration space spec allows for a memory size of up
524 * Current generation hardware uses 56-bit physical addresses,
525 * but we won't be able to get near close to that, as we won't
526 * have a hole big enough in the memory map. Let it pass in
527 * the driver for now. We'll get an error from the firmware
528 * when trying to configure something too big.
530 total_mem_size = 1ull << val32;
532 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START, &val32);
536 afu->lpc_mem_offset = val32;
538 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START + 4, &val32);
542 afu->lpc_mem_offset |= (u64) val32 << 32;
544 rc = read_template_version(dev, fn, &templ_len, &templ_version);
548 if (templ_version >= 0x0101) {
549 rc = read_afu_info(dev, fn,
550 OCXL_DVSEC_TEMPL_LPC_MEM_SZ, &val32);
553 lpc_mem_size = val32;
555 rc = read_afu_info(dev, fn,
556 OCXL_DVSEC_TEMPL_LPC_MEM_SZ + 4, &val32);
559 lpc_mem_size |= (u64) val32 << 32;
561 lpc_mem_size = total_mem_size;
563 afu->lpc_mem_size = lpc_mem_size;
565 if (lpc_mem_size < total_mem_size) {
566 afu->special_purpose_mem_offset =
567 afu->lpc_mem_offset + lpc_mem_size;
568 afu->special_purpose_mem_size =
569 total_mem_size - lpc_mem_size;
574 int ocxl_config_read_afu(struct pci_dev *dev, struct ocxl_fn_config *fn,
575 struct ocxl_afu_config *afu, u8 afu_idx)
581 * First, we need to write the AFU idx for the AFU we want to
584 WARN_ON((afu_idx & OCXL_DVSEC_AFU_IDX_MASK) != afu_idx);
586 pci_write_config_byte(dev,
587 fn->dvsec_afu_info_pos + OCXL_DVSEC_AFU_INFO_AFU_IDX,
590 rc = read_afu_name(dev, fn, afu);
594 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_AFU_VERSION, &val32);
597 afu->version_major = EXTRACT_BITS(val32, 24, 31);
598 afu->version_minor = EXTRACT_BITS(val32, 16, 23);
599 afu->afuc_type = EXTRACT_BITS(val32, 14, 15);
600 afu->afum_type = EXTRACT_BITS(val32, 12, 13);
601 afu->profile = EXTRACT_BITS(val32, 0, 7);
603 rc = read_afu_mmio(dev, fn, afu);
607 rc = read_afu_lpc_memory_info(dev, fn, afu);
611 rc = read_afu_control(dev, afu);
615 dev_dbg(&dev->dev, "AFU configuration:\n");
616 dev_dbg(&dev->dev, " name = %s\n", afu->name);
617 dev_dbg(&dev->dev, " version = %d.%d\n", afu->version_major,
619 dev_dbg(&dev->dev, " global mmio bar = %hhu\n", afu->global_mmio_bar);
620 dev_dbg(&dev->dev, " global mmio offset = %#llx\n",
621 afu->global_mmio_offset);
622 dev_dbg(&dev->dev, " global mmio size = %#x\n", afu->global_mmio_size);
623 dev_dbg(&dev->dev, " pp mmio bar = %hhu\n", afu->pp_mmio_bar);
624 dev_dbg(&dev->dev, " pp mmio offset = %#llx\n", afu->pp_mmio_offset);
625 dev_dbg(&dev->dev, " pp mmio stride = %#x\n", afu->pp_mmio_stride);
626 dev_dbg(&dev->dev, " lpc_mem offset = %#llx\n", afu->lpc_mem_offset);
627 dev_dbg(&dev->dev, " lpc_mem size = %#llx\n", afu->lpc_mem_size);
628 dev_dbg(&dev->dev, " special purpose mem offset = %#llx\n",
629 afu->special_purpose_mem_offset);
630 dev_dbg(&dev->dev, " special purpose mem size = %#llx\n",
631 afu->special_purpose_mem_size);
632 dev_dbg(&dev->dev, " pasid supported (log) = %u\n",
633 afu->pasid_supported_log);
634 dev_dbg(&dev->dev, " actag supported = %u\n",
635 afu->actag_supported);
637 rc = validate_afu(dev, afu);
640 EXPORT_SYMBOL_GPL(ocxl_config_read_afu);
642 int ocxl_config_get_actag_info(struct pci_dev *dev, u16 *base, u16 *enabled,
648 * This is really a simple wrapper for the kernel API, to
649 * avoid an external driver using ocxl as a library to call
650 * platform-dependent code
652 rc = pnv_ocxl_get_actag(dev, base, enabled, supported);
654 dev_err(&dev->dev, "Can't get actag for device: %d\n", rc);
659 EXPORT_SYMBOL_GPL(ocxl_config_get_actag_info);
661 void ocxl_config_set_afu_actag(struct pci_dev *dev, int pos, int actag_base,
666 val = actag_count & OCXL_DVSEC_ACTAG_MASK;
667 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_EN, val);
669 val = actag_base & OCXL_DVSEC_ACTAG_MASK;
670 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_BASE, val);
672 EXPORT_SYMBOL_GPL(ocxl_config_set_afu_actag);
674 int ocxl_config_get_pasid_info(struct pci_dev *dev, int *count)
676 return pnv_ocxl_get_pasid_count(dev, count);
679 void ocxl_config_set_afu_pasid(struct pci_dev *dev, int pos, int pasid_base,
685 val8 = pasid_count_log & OCXL_DVSEC_PASID_LOG_MASK;
686 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_EN, val8);
688 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
690 val32 &= ~OCXL_DVSEC_PASID_MASK;
691 val32 |= pasid_base & OCXL_DVSEC_PASID_MASK;
692 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
695 EXPORT_SYMBOL_GPL(ocxl_config_set_afu_pasid);
697 void ocxl_config_set_afu_state(struct pci_dev *dev, int pos, int enable)
701 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, &val);
706 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, val);
708 EXPORT_SYMBOL_GPL(ocxl_config_set_afu_state);
710 int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec)
720 * Skip on function != 0, as the TL can only be defined on 0
722 if (PCI_FUNC(dev->devfn) != 0)
725 recv_rate = kzalloc(PNV_OCXL_TL_RATE_BUF_SIZE, GFP_KERNEL);
729 * The spec defines 64 templates for messages in the
730 * Transaction Layer (TL).
732 * The host and device each support a subset, so we need to
733 * configure the transmitters on each side to send only
734 * templates the receiver understands, at a rate the receiver
735 * can process. Per the spec, template 0 must be supported by
736 * everybody. That's the template which has been used by the
737 * host and device so far.
739 * The sending rate limit must be set before the template is
746 rc = pnv_ocxl_get_tl_cap(dev, &recv_cap, recv_rate,
747 PNV_OCXL_TL_RATE_BUF_SIZE);
751 for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) {
752 be32ptr = (__be32 *) &recv_rate[i];
753 pci_write_config_dword(dev,
754 tl_dvsec + OCXL_DVSEC_TL_SEND_RATE + i,
755 be32_to_cpu(*be32ptr));
757 val = recv_cap >> 32;
758 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP, val);
759 val = recv_cap & GENMASK(31, 0);
760 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP + 4, val);
765 for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) {
766 pci_read_config_dword(dev,
767 tl_dvsec + OCXL_DVSEC_TL_RECV_RATE + i,
769 be32ptr = (__be32 *) &recv_rate[i];
770 *be32ptr = cpu_to_be32(val);
772 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP, &val);
773 recv_cap = (long) val << 32;
774 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP + 4, &val);
777 rc = pnv_ocxl_set_tl_conf(dev, recv_cap, __pa(recv_rate),
778 PNV_OCXL_TL_RATE_BUF_SIZE);
783 * Opencapi commands needing to be retried are classified per
784 * the TL in 2 groups: short and long commands.
786 * The short back off timer it not used for now. It will be
789 * The long back off timer is typically used when an AFU hits
790 * a page fault but the NPU is already processing one. So the
791 * AFU needs to wait before it can resubmit. Having a value
792 * too low doesn't break anything, but can generate extra
793 * traffic on the link.
794 * We set it to 1.6 us for now. It's shorter than, but in the
795 * same order of magnitude as the time spent to process a page
798 timers = 0x2 << 4; /* long timer = 1.6 us */
799 pci_write_config_byte(dev, tl_dvsec + OCXL_DVSEC_TL_BACKOFF_TIMERS,
807 EXPORT_SYMBOL_GPL(ocxl_config_set_TL);
809 int ocxl_config_terminate_pasid(struct pci_dev *dev, int afu_control, int pasid)
812 unsigned long timeout;
814 pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
816 if (EXTRACT_BIT(val, 20)) {
818 "Can't terminate PASID %#x, previous termination didn't complete\n",
823 val &= ~OCXL_DVSEC_PASID_MASK;
824 val |= pasid & OCXL_DVSEC_PASID_MASK;
826 pci_write_config_dword(dev,
827 afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
830 timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT);
831 pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
833 while (EXTRACT_BIT(val, 20)) {
834 if (time_after_eq(jiffies, timeout)) {
836 "Timeout while waiting for AFU to terminate PASID %#x\n",
841 pci_read_config_dword(dev,
842 afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
847 EXPORT_SYMBOL_GPL(ocxl_config_terminate_pasid);
849 void ocxl_config_set_actag(struct pci_dev *dev, int func_dvsec, u32 tag_first,
854 val = (tag_first & OCXL_DVSEC_ACTAG_MASK) << 16;
855 val |= tag_count & OCXL_DVSEC_ACTAG_MASK;
856 pci_write_config_dword(dev, func_dvsec + OCXL_DVSEC_FUNC_OFF_ACTAG,
859 EXPORT_SYMBOL_GPL(ocxl_config_set_actag);