2 * (C) Copyright 2013 ADVANSEE
3 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
5 * Based on Dirk Behme's
6 * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
7 * which is based on Freescale's
8 * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
10 * Copyright (C) 2011 Freescale Semiconductor, Inc.
12 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/errno.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/mach-imx/sys_proto.h>
23 #define BO_CTRL_WR_UNLOCK 16
24 #define BM_CTRL_WR_UNLOCK 0xffff0000
25 #define BV_CTRL_WR_UNLOCK_KEY 0x3e77
26 #define BM_CTRL_ERROR 0x00000200
27 #define BM_CTRL_BUSY 0x00000100
28 #define BO_CTRL_ADDR 0
30 #define BM_CTRL_ADDR 0x0000000f
31 #define BM_CTRL_RELOAD 0x00000400
32 #elif defined(CONFIG_MX7ULP)
33 #define BM_CTRL_ADDR 0x000000FF
34 #define BM_CTRL_RELOAD 0x00000400
35 #define BM_OUT_STATUS_DED 0x00000400
36 #define BM_OUT_STATUS_LOCKED 0x00000800
37 #define BM_OUT_STATUS_PROGFAIL 0x00001000
38 #elif defined(CONFIG_MX8M)
39 #define BM_CTRL_ADDR 0x000000ff
41 #define BM_CTRL_ADDR 0x0000007f
45 #define BO_TIMING_FSOURCE 12
46 #define BM_TIMING_FSOURCE 0x0007f000
47 #define BV_TIMING_FSOURCE_NS 1001
48 #define BO_TIMING_PROG 0
49 #define BM_TIMING_PROG 0x00000fff
50 #define BV_TIMING_PROG_US 10
52 #define BO_TIMING_STROBE_READ 16
53 #define BM_TIMING_STROBE_READ 0x003f0000
54 #define BV_TIMING_STROBE_READ_NS 37
55 #define BO_TIMING_RELAX 12
56 #define BM_TIMING_RELAX 0x0000f000
57 #define BV_TIMING_RELAX_NS 17
58 #define BO_TIMING_STROBE_PROG 0
59 #define BM_TIMING_STROBE_PROG 0x00000fff
60 #define BV_TIMING_STROBE_PROG_US 10
63 #define BM_READ_CTRL_READ_FUSE 0x00000001
65 #define BF(value, field) (((value) << BO_##field) & BM_##field)
67 #define WRITE_POSTAMBLE_US 2
69 #if defined(CONFIG_MX6) || defined(CONFIG_VF610)
70 #define FUSE_BANK_SIZE 0x80
73 #elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
78 #elif defined CONFIG_MX7
79 #define FUSE_BANK_SIZE 0x40
81 #elif defined(CONFIG_MX7ULP)
82 #define FUSE_BANK_SIZE 0x80
84 #elif defined(CONFIG_MX8M)
85 #define FUSE_BANK_SIZE 0x40
88 #error "Unsupported architecture\n"
91 #if defined(CONFIG_MX6)
94 * There is a hole in shadow registers address map of size 0x100
95 * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX,
96 * iMX6UL, i.MX6ULL and i.MX6SLL.
97 * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
98 * we should account for this hole in address space.
100 * Similar hole exists between bank 14 and bank 15 of size
101 * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
102 * Note: iMX6SL has only 0-7 banks and there is no hole.
103 * Note: iMX6UL doesn't have this one.
105 * This function is to covert user input to physical bank index.
106 * Only needed when read fuse, because we use register offset, so
107 * need to calculate real register offset.
108 * When write, no need to consider hole, always use the bank/word
109 * index from fuse map.
111 u32 fuse_bank_physical(int index)
115 if (is_mx6sl() || is_mx7ulp()) {
117 } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
118 if ((is_mx6ull() || is_mx6sll()) && index == 8)
122 phy_index = fuse_bank_physical(5) + (index - 6) + 3;
127 phy_index = fuse_bank_physical(14) + (index - 15) + 2;
129 phy_index = fuse_bank_physical(5) + (index - 6) + 3;
136 u32 fuse_word_physical(u32 bank, u32 word_index)
138 if (is_mx6ull() || is_mx6sll()) {
140 word_index = word_index + 4;
146 u32 fuse_bank_physical(int index)
151 u32 fuse_word_physical(u32 bank, u32 word_index)
158 static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
160 while (readl(®s->ctrl) & BM_CTRL_BUSY)
164 static void clear_error(struct ocotp_regs *regs)
166 writel(BM_CTRL_ERROR, ®s->ctrl_clr);
169 static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
170 int assert, const char *caller)
172 *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
174 if (bank >= FUSE_BANKS ||
175 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
177 printf("mxc_ocotp %s(): Invalid argument\n", caller);
181 if (is_mx6ull() || is_mx6sll()) {
182 if ((bank == 7 || bank == 8) &&
183 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) {
184 printf("mxc_ocotp %s(): Invalid argument\n", caller);
197 static int finish_access(struct ocotp_regs *regs, const char *caller)
201 err = !!(readl(®s->ctrl) & BM_CTRL_ERROR);
205 /* Need to power down the OTP memory */
206 writel(1, ®s->pdn);
209 printf("mxc_ocotp %s(): Access protect error\n", caller);
216 static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
219 return prepare_access(regs, bank, word, val != NULL, caller);
222 int fuse_read(u32 bank, u32 word, u32 *val)
224 struct ocotp_regs *regs;
229 ret = prepare_read(®s, bank, word, val, __func__);
233 phy_bank = fuse_bank_physical(bank);
234 phy_word = fuse_word_physical(bank, word);
236 *val = readl(®s->bank[phy_bank].fuse_regs[phy_word << 2]);
239 if (readl(®s->out_status) & BM_OUT_STATUS_DED) {
240 writel(BM_OUT_STATUS_DED, ®s->out_status_clr);
241 printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
245 return finish_access(regs, __func__);
249 static void set_timing(struct ocotp_regs *regs)
255 ipg_clk = mxc_get_clock(MXC_IPG_CLK);
257 fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS,
259 prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1;
261 timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG);
263 clrsetbits_le32(®s->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG,
266 #elif defined(CONFIG_MX7ULP)
267 static void set_timing(struct ocotp_regs *regs)
269 /* No timing set for MX7ULP */
273 static void set_timing(struct ocotp_regs *regs)
276 u32 relax, strobe_read, strobe_prog;
279 ipg_clk = mxc_get_clock(MXC_IPG_CLK);
281 relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
282 strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
283 1000000000) + 2 * (relax + 1) - 1;
284 strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US,
285 1000000) + 2 * (relax + 1) - 1;
287 timing = BF(strobe_read, TIMING_STROBE_READ) |
288 BF(relax, TIMING_RELAX) |
289 BF(strobe_prog, TIMING_STROBE_PROG);
291 clrsetbits_le32(®s->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
292 BM_TIMING_STROBE_PROG, timing);
296 static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
299 u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
302 #elif defined CONFIG_MX8M
303 u32 addr = bank << 2 | word;
306 /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
307 if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) {
311 addr = bank << 3 | word;
315 clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
316 BF(wr_unlock, CTRL_WR_UNLOCK) |
317 BF(addr, CTRL_ADDR));
320 int fuse_sense(u32 bank, u32 word, u32 *val)
322 struct ocotp_regs *regs;
325 ret = prepare_read(®s, bank, word, val, __func__);
329 setup_direct_access(regs, bank, word, false);
330 writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl);
333 *val = readl((®s->read_fuse_data0) + (word << 2));
335 *val = readl(®s->read_fuse_data);
339 if (readl(®s->out_status) & BM_OUT_STATUS_DED) {
340 writel(BM_OUT_STATUS_DED, ®s->out_status_clr);
341 printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
346 return finish_access(regs, __func__);
349 static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
356 /* Only bank 0 and 1 are redundancy mode, others are ECC mode */
357 if (bank != 0 && bank != 1) {
358 ret = fuse_sense(bank, word, &val);
363 printf("mxc_ocotp: The word has been programmed, no more write\n");
369 return prepare_access(regs, bank, word, true, caller);
372 int fuse_prog(u32 bank, u32 word, u32 val)
374 struct ocotp_regs *regs;
377 ret = prepare_write(®s, bank, word, __func__);
381 setup_direct_access(regs, bank, word, true);
385 writel(0, ®s->data1);
386 writel(0, ®s->data2);
387 writel(0, ®s->data3);
388 writel(val, ®s->data0);
391 writel(val, ®s->data1);
392 writel(0, ®s->data2);
393 writel(0, ®s->data3);
394 writel(0, ®s->data0);
397 writel(0, ®s->data1);
398 writel(val, ®s->data2);
399 writel(0, ®s->data3);
400 writel(0, ®s->data0);
403 writel(0, ®s->data1);
404 writel(0, ®s->data2);
405 writel(val, ®s->data3);
406 writel(0, ®s->data0);
409 wait_busy(regs, BV_TIMING_PROG_US);
411 writel(val, ®s->data);
412 wait_busy(regs, BV_TIMING_STROBE_PROG_US);
414 udelay(WRITE_POSTAMBLE_US);
417 if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
418 writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr);
419 printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
424 return finish_access(regs, __func__);
427 int fuse_override(u32 bank, u32 word, u32 val)
429 struct ocotp_regs *regs;
434 ret = prepare_write(®s, bank, word, __func__);
438 phy_bank = fuse_bank_physical(bank);
439 phy_word = fuse_word_physical(bank, word);
441 writel(val, ®s->bank[phy_bank].fuse_regs[phy_word << 2]);
444 if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
445 writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr);
446 printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
451 return finish_access(regs, __func__);