drivers/misc/mxc_ocotp.c

   1 /*
   2  * (C) Copyright 2013 ADVANSEE
   3  * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
   4  *
   5  * Based on Dirk Behme's
   6  * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
   7  * which is based on Freescale's
   8  * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
   9  * which is:
  10  * Copyright (C) 2011 Freescale Semiconductor, Inc.
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #include <common.h>
  16 #include <fuse.h>
  17 #include <linux/errno.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/imx-regs.h>
  21 #include <asm/imx-common/sys_proto.h>
  22
  23 #define BO_CTRL_WR_UNLOCK               16
  24 #define BM_CTRL_WR_UNLOCK               0xffff0000
  25 #define BV_CTRL_WR_UNLOCK_KEY           0x3e77
  26 #define BM_CTRL_ERROR                   0x00000200
  27 #define BM_CTRL_BUSY                    0x00000100
  28 #define BO_CTRL_ADDR                    0
  29 #ifdef CONFIG_MX7
  30 #define BM_CTRL_ADDR                    0x0000000f
  31 #define BM_CTRL_RELOAD                  0x00000400
  32 #else
  33 #define BM_CTRL_ADDR                    0x0000007f
  34 #endif
  35
  36 #ifdef CONFIG_MX7
  37 #define BO_TIMING_FSOURCE               12
  38 #define BM_TIMING_FSOURCE               0x0007f000
  39 #define BV_TIMING_FSOURCE_NS            1001
  40 #define BO_TIMING_PROG                  0
  41 #define BM_TIMING_PROG                  0x00000fff
  42 #define BV_TIMING_PROG_US               10
  43 #else
  44 #define BO_TIMING_STROBE_READ           16
  45 #define BM_TIMING_STROBE_READ           0x003f0000
  46 #define BV_TIMING_STROBE_READ_NS        37
  47 #define BO_TIMING_RELAX                 12
  48 #define BM_TIMING_RELAX                 0x0000f000
  49 #define BV_TIMING_RELAX_NS              17
  50 #define BO_TIMING_STROBE_PROG           0
  51 #define BM_TIMING_STROBE_PROG           0x00000fff
  52 #define BV_TIMING_STROBE_PROG_US        10
  53 #endif
  54
  55 #define BM_READ_CTRL_READ_FUSE          0x00000001
  56
  57 #define BF(value, field)                (((value) << BO_##field) & BM_##field)
  58
  59 #define WRITE_POSTAMBLE_US              2
  60
  61 #if defined(CONFIG_MX6) || defined(CONFIG_VF610)
  62 #define FUSE_BANK_SIZE  0x80
  63 #ifdef CONFIG_MX6SL
  64 #define FUSE_BANKS      8
  65 #elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
  66 #define FUSE_BANKS      9
  67 #else
  68 #define FUSE_BANKS      16
  69 #endif
  70 #elif defined CONFIG_MX7
  71 #define FUSE_BANK_SIZE  0x40
  72 #define FUSE_BANKS      16
  73 #else
  74 #error "Unsupported architecture\n"
  75 #endif
  76
  77 #if defined(CONFIG_MX6)
  78
  79 /*
  80  * There is a hole in shadow registers address map of size 0x100
  81  * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX,
  82  * iMX6UL, i.MX6ULL and i.MX6SLL.
  83  * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
  84  * we should account for this hole in address space.
  85  *
  86  * Similar hole exists between bank 14 and bank 15 of size
  87  * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
  88  * Note: iMX6SL has only 0-7 banks and there is no hole.
  89  * Note: iMX6UL doesn't have this one.
  90  *
  91  * This function is to covert user input to physical bank index.
  92  * Only needed when read fuse, because we use register offset, so
  93  * need to calculate real register offset.
  94  * When write, no need to consider hole, always use the bank/word
  95  * index from fuse map.
  96  */
  97 u32 fuse_bank_physical(int index)
  98 {
  99         u32 phy_index;
 100
 101         if (is_mx6sl()) {
 102                 phy_index = index;
 103         } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
 104                 if ((is_mx6ull() || is_mx6sll()) && index == 8)
 105                         index = 7;
 106
 107                 if (index >= 6)
 108                         phy_index = fuse_bank_physical(5) + (index - 6) + 3;
 109                 else
 110                         phy_index = index;
 111         } else {
 112                 if (index >= 15)
 113                         phy_index = fuse_bank_physical(14) + (index - 15) + 2;
 114                 else if (index >= 6)
 115                         phy_index = fuse_bank_physical(5) + (index - 6) + 3;
 116                 else
 117                         phy_index = index;
 118         }
 119         return phy_index;
 120 }
 121
 122 u32 fuse_word_physical(u32 bank, u32 word_index)
 123 {
 124         if (is_mx6ull() || is_mx6sll()) {
 125                 if (bank == 8)
 126                         word_index = word_index + 4;
 127         }
 128
 129         return word_index;
 130 }
 131 #else
 132 u32 fuse_bank_physical(int index)
 133 {
 134         return index;
 135 }
 136
 137 u32 fuse_word_physical(u32 bank, u32 word_index)
 138 {
 139         return word_index;
 140 }
 141
 142 #endif
 143
 144 static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
 145 {
 146         while (readl(&regs->ctrl) & BM_CTRL_BUSY)
 147                 udelay(delay_us);
 148 }
 149
 150 static void clear_error(struct ocotp_regs *regs)
 151 {
 152         writel(BM_CTRL_ERROR, &regs->ctrl_clr);
 153 }
 154
 155 static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
 156                                 int assert, const char *caller)
 157 {
 158         *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 159
 160         if (bank >= FUSE_BANKS ||
 161             word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
 162             !assert) {
 163                 printf("mxc_ocotp %s(): Invalid argument\n", caller);
 164                 return -EINVAL;
 165         }
 166
 167         if (is_mx6ull() || is_mx6sll()) {
 168                 if ((bank == 7 || bank == 8) &&
 169                     word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) {
 170                         printf("mxc_ocotp %s(): Invalid argument\n", caller);
 171                         return -EINVAL;
 172                 }
 173         }
 174
 175         enable_ocotp_clk(1);
 176
 177         wait_busy(*regs, 1);
 178         clear_error(*regs);
 179
 180         return 0;
 181 }
 182
 183 static int finish_access(struct ocotp_regs *regs, const char *caller)
 184 {
 185         u32 err;
 186
 187         err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
 188         clear_error(regs);
 189
 190         if (err) {
 191                 printf("mxc_ocotp %s(): Access protect error\n", caller);
 192                 return -EIO;
 193         }
 194
 195         return 0;
 196 }
 197
 198 static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
 199                         const char *caller)
 200 {
 201         return prepare_access(regs, bank, word, val != NULL, caller);
 202 }
 203
 204 int fuse_read(u32 bank, u32 word, u32 *val)
 205 {
 206         struct ocotp_regs *regs;
 207         int ret;
 208         u32 phy_bank;
 209         u32 phy_word;
 210
 211         ret = prepare_read(&regs, bank, word, val, __func__);
 212         if (ret)
 213                 return ret;
 214
 215         phy_bank = fuse_bank_physical(bank);
 216         phy_word = fuse_word_physical(bank, word);
 217
 218         *val = readl(&regs->bank[phy_bank].fuse_regs[phy_word << 2]);
 219
 220         return finish_access(regs, __func__);
 221 }
 222
 223 #ifdef CONFIG_MX7
 224 static void set_timing(struct ocotp_regs *regs)
 225 {
 226         u32 ipg_clk;
 227         u32 fsource, prog;
 228         u32 timing;
 229
 230         ipg_clk = mxc_get_clock(MXC_IPG_CLK);
 231
 232         fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS,
 233                         +       1000000) + 1;
 234         prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1;
 235
 236         timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG);
 237
 238         clrsetbits_le32(&regs->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG,
 239                         timing);
 240 }
 241 #else
 242 static void set_timing(struct ocotp_regs *regs)
 243 {
 244         u32 ipg_clk;
 245         u32 relax, strobe_read, strobe_prog;
 246         u32 timing;
 247
 248         ipg_clk = mxc_get_clock(MXC_IPG_CLK);
 249
 250         relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
 251         strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
 252                                         1000000000) + 2 * (relax + 1) - 1;
 253         strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US,
 254                                                 1000000) + 2 * (relax + 1) - 1;
 255
 256         timing = BF(strobe_read, TIMING_STROBE_READ) |
 257                         BF(relax, TIMING_RELAX) |
 258                         BF(strobe_prog, TIMING_STROBE_PROG);
 259
 260         clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
 261                         BM_TIMING_STROBE_PROG, timing);
 262 }
 263 #endif
 264
 265 static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
 266                                 int write)
 267 {
 268         u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
 269 #ifdef CONFIG_MX7
 270         u32 addr = bank;
 271 #else
 272         u32 addr;
 273         /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
 274         if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) {
 275                 bank = bank - 1;
 276                 word += 4;
 277         }
 278         addr = bank << 3 | word;
 279 #endif
 280
 281         set_timing(regs);
 282         clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
 283                         BF(wr_unlock, CTRL_WR_UNLOCK) |
 284                         BF(addr, CTRL_ADDR));
 285 }
 286
 287 int fuse_sense(u32 bank, u32 word, u32 *val)
 288 {
 289         struct ocotp_regs *regs;
 290         int ret;
 291
 292         ret = prepare_read(&regs, bank, word, val, __func__);
 293         if (ret)
 294                 return ret;
 295
 296         setup_direct_access(regs, bank, word, false);
 297         writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl);
 298         wait_busy(regs, 1);
 299 #ifdef CONFIG_MX7
 300         *val = readl((&regs->read_fuse_data0) + (word << 2));
 301 #else
 302         *val = readl(&regs->read_fuse_data);
 303 #endif
 304
 305         return finish_access(regs, __func__);
 306 }
 307
 308 static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
 309                                 const char *caller)
 310 {
 311         return prepare_access(regs, bank, word, true, caller);
 312 }
 313
 314 int fuse_prog(u32 bank, u32 word, u32 val)
 315 {
 316         struct ocotp_regs *regs;
 317         int ret;
 318
 319         ret = prepare_write(&regs, bank, word, __func__);
 320         if (ret)
 321                 return ret;
 322
 323         setup_direct_access(regs, bank, word, true);
 324 #ifdef CONFIG_MX7
 325         switch (word) {
 326         case 0:
 327                 writel(0, &regs->data1);
 328                 writel(0, &regs->data2);
 329                 writel(0, &regs->data3);
 330                 writel(val, &regs->data0);
 331                 break;
 332         case 1:
 333                 writel(val, &regs->data1);
 334                 writel(0, &regs->data2);
 335                 writel(0, &regs->data3);
 336                 writel(0, &regs->data0);
 337                 break;
 338         case 2:
 339                 writel(0, &regs->data1);
 340                 writel(val, &regs->data2);
 341                 writel(0, &regs->data3);
 342                 writel(0, &regs->data0);
 343                 break;
 344         case 3:
 345                 writel(0, &regs->data1);
 346                 writel(0, &regs->data2);
 347                 writel(val, &regs->data3);
 348                 writel(0, &regs->data0);
 349                 break;
 350         }
 351         wait_busy(regs, BV_TIMING_PROG_US);
 352 #else
 353         writel(val, &regs->data);
 354         wait_busy(regs, BV_TIMING_STROBE_PROG_US);
 355 #endif
 356         udelay(WRITE_POSTAMBLE_US);
 357
 358         return finish_access(regs, __func__);
 359 }
 360
 361 int fuse_override(u32 bank, u32 word, u32 val)
 362 {
 363         struct ocotp_regs *regs;
 364         int ret;
 365         u32 phy_bank;
 366         u32 phy_word;
 367
 368         ret = prepare_write(&regs, bank, word, __func__);
 369         if (ret)
 370                 return ret;
 371
 372         phy_bank = fuse_bank_physical(bank);
 373         phy_word = fuse_word_physical(bank, word);
 374
 375         writel(val, &regs->bank[phy_bank].fuse_regs[phy_word << 2]);
 376
 377         return finish_access(regs, __func__);
 378 }