2 * (C) Copyright 2013 ADVANSEE
3 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
5 * Based on Dirk Behme's
6 * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
7 * which is based on Freescale's
8 * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
10 * Copyright (C) 2011 Freescale Semiconductor, Inc.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/errno.h>
35 #include <asm/arch/clock.h>
36 #include <asm/arch/imx-regs.h>
38 #define BO_CTRL_WR_UNLOCK 16
39 #define BM_CTRL_WR_UNLOCK 0xffff0000
40 #define BV_CTRL_WR_UNLOCK_KEY 0x3e77
41 #define BM_CTRL_ERROR 0x00000200
42 #define BM_CTRL_BUSY 0x00000100
43 #define BO_CTRL_ADDR 0
44 #define BM_CTRL_ADDR 0x0000007f
46 #define BO_TIMING_STROBE_READ 16
47 #define BM_TIMING_STROBE_READ 0x003f0000
48 #define BV_TIMING_STROBE_READ_NS 37
49 #define BO_TIMING_RELAX 12
50 #define BM_TIMING_RELAX 0x0000f000
51 #define BV_TIMING_RELAX_NS 17
52 #define BO_TIMING_STROBE_PROG 0
53 #define BM_TIMING_STROBE_PROG 0x00000fff
54 #define BV_TIMING_STROBE_PROG_US 10
56 #define BM_READ_CTRL_READ_FUSE 0x00000001
58 #define BF(value, field) (((value) << BO_##field) & BM_##field)
60 #define WRITE_POSTAMBLE_US 2
62 static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
64 while (readl(®s->ctrl) & BM_CTRL_BUSY)
68 static void clear_error(struct ocotp_regs *regs)
70 writel(BM_CTRL_ERROR, ®s->ctrl_clr);
73 static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
74 int assert, const char *caller)
76 *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
78 if (bank >= ARRAY_SIZE((*regs)->bank) ||
79 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
81 printf("mxc_ocotp %s(): Invalid argument\n", caller);
93 static int finish_access(struct ocotp_regs *regs, const char *caller)
97 err = !!(readl(®s->ctrl) & BM_CTRL_ERROR);
103 printf("mxc_ocotp %s(): Access protect error\n", caller);
110 static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
113 return prepare_access(regs, bank, word, val != NULL, caller);
116 int fuse_read(u32 bank, u32 word, u32 *val)
118 struct ocotp_regs *regs;
121 ret = prepare_read(®s, bank, word, val, __func__);
125 *val = readl(®s->bank[bank].fuse_regs[word << 2]);
127 return finish_access(regs, __func__);
130 static void set_timing(struct ocotp_regs *regs)
133 u32 relax, strobe_read, strobe_prog;
136 ipg_clk = mxc_get_clock(MXC_IPG_CLK);
138 relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
139 strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
140 1000000000) + 2 * (relax + 1) - 1;
141 strobe_prog = DIV_ROUND(ipg_clk * BV_TIMING_STROBE_PROG_US, 1000000) +
144 timing = BF(strobe_read, TIMING_STROBE_READ) |
145 BF(relax, TIMING_RELAX) |
146 BF(strobe_prog, TIMING_STROBE_PROG);
148 clrsetbits_le32(®s->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
149 BM_TIMING_STROBE_PROG, timing);
152 static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
155 u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
156 u32 addr = bank << 3 | word;
159 clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
160 BF(wr_unlock, CTRL_WR_UNLOCK) |
161 BF(addr, CTRL_ADDR));
164 int fuse_sense(u32 bank, u32 word, u32 *val)
166 struct ocotp_regs *regs;
169 ret = prepare_read(®s, bank, word, val, __func__);
173 setup_direct_access(regs, bank, word, false);
174 writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl);
176 *val = readl(®s->read_fuse_data);
178 return finish_access(regs, __func__);
181 static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
184 return prepare_access(regs, bank, word, true, caller);
187 int fuse_prog(u32 bank, u32 word, u32 val)
189 struct ocotp_regs *regs;
192 ret = prepare_write(®s, bank, word, __func__);
196 setup_direct_access(regs, bank, word, true);
197 writel(val, ®s->data);
198 wait_busy(regs, BV_TIMING_STROBE_PROG_US);
199 udelay(WRITE_POSTAMBLE_US);
201 return finish_access(regs, __func__);
204 int fuse_override(u32 bank, u32 word, u32 val)
206 struct ocotp_regs *regs;
209 ret = prepare_write(®s, bank, word, __func__);
213 writel(val, ®s->bank[bank].fuse_regs[word << 2]);
215 return finish_access(regs, __func__);