drivers/misc/mei/pci-me.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2003-2019, Intel Corporation. All rights reserved.
   4  * Intel Management Engine Interface (Intel MEI) Linux driver
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/moduleparam.h>
   9 #include <linux/kernel.h>
  10 #include <linux/device.h>
  11 #include <linux/fs.h>
  12 #include <linux/errno.h>
  13 #include <linux/types.h>
  14 #include <linux/fcntl.h>
  15 #include <linux/pci.h>
  16 #include <linux/poll.h>
  17 #include <linux/ioctl.h>
  18 #include <linux/cdev.h>
  19 #include <linux/sched.h>
  20 #include <linux/uuid.h>
  21 #include <linux/compat.h>
  22 #include <linux/jiffies.h>
  23 #include <linux/interrupt.h>
  24
  25 #include <linux/pm_domain.h>
  26 #include <linux/pm_runtime.h>
  27
  28 #include <linux/mei.h>
  29
  30 #include "mei_dev.h"
  31 #include "client.h"
  32 #include "hw-me-regs.h"
  33 #include "hw-me.h"
  34
  35 /* mei_pci_tbl - PCI Device ID Table */
  36 static const struct pci_device_id mei_me_pci_tbl[] = {
  37         {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
  38         {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
  39         {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
  40         {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
  41         {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
  42         {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
  43         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
  44         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
  45         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
  46         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
  47         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
  48
  49         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
  50         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
  51         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
  52         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
  53         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
  54         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
  55         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
  56         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
  57         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
  58
  59         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
  60         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
  61         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
  62         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
  63
  64         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
  65         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
  66         {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
  67         {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
  68         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
  69         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
  70         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
  71         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)},
  72         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)},
  73         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
  74         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)},
  75         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
  76         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
  77
  78         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
  79         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
  80         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
  81         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
  82         {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)},
  83
  84         {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
  85         {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
  86
  87         {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
  88
  89         {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
  90
  91         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
  92         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
  93
  94         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
  95         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)},
  96         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)},
  97         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)},
  98
  99         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
 100         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)},
 101
 102         {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
 103
 104         {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH12_CFG)},
 105
 106         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH12_CFG)},
 107         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
 108
 109         /* required last entry */
 110         {0, }
 111 };
 112
 113 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
 114
 115 #ifdef CONFIG_PM
 116 static inline void mei_me_set_pm_domain(struct mei_device *dev);
 117 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
 118 #else
 119 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
 120 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
 121 #endif /* CONFIG_PM */
 122
 123 /**
 124  * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 125  *
 126  * @pdev: PCI device structure
 127  * @cfg: per generation config
 128  *
 129  * Return: true if ME Interface is valid, false otherwise
 130  */
 131 static bool mei_me_quirk_probe(struct pci_dev *pdev,
 132                                 const struct mei_cfg *cfg)
 133 {
 134         if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
 135                 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
 136                 return false;
 137         }
 138
 139         return true;
 140 }
 141
 142 /**
 143  * mei_me_probe - Device Initialization Routine
 144  *
 145  * @pdev: PCI device structure
 146  * @ent: entry in kcs_pci_tbl
 147  *
 148  * Return: 0 on success, <0 on failure.
 149  */
 150 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 151 {
 152         const struct mei_cfg *cfg;
 153         struct mei_device *dev;
 154         struct mei_me_hw *hw;
 155         unsigned int irqflags;
 156         int err;
 157
 158         cfg = mei_me_get_cfg(ent->driver_data);
 159         if (!cfg)
 160                 return -ENODEV;
 161
 162         if (!mei_me_quirk_probe(pdev, cfg))
 163                 return -ENODEV;
 164
 165         /* enable pci dev */
 166         err = pcim_enable_device(pdev);
 167         if (err) {
 168                 dev_err(&pdev->dev, "failed to enable pci device.\n");
 169                 goto end;
 170         }
 171         /* set PCI host mastering  */
 172         pci_set_master(pdev);
 173         /* pci request regions and mapping IO device memory for mei driver */
 174         err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
 175         if (err) {
 176                 dev_err(&pdev->dev, "failed to get pci regions.\n");
 177                 goto end;
 178         }
 179
 180         if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
 181             dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
 182
 183                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
 184                 if (err)
 185                         err = dma_set_coherent_mask(&pdev->dev,
 186                                                     DMA_BIT_MASK(32));
 187         }
 188         if (err) {
 189                 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
 190                 goto end;
 191         }
 192
 193         /* allocates and initializes the mei dev structure */
 194         dev = mei_me_dev_init(pdev, cfg);
 195         if (!dev) {
 196                 err = -ENOMEM;
 197                 goto end;
 198         }
 199         hw = to_me_hw(dev);
 200         hw->mem_addr = pcim_iomap_table(pdev)[0];
 201
 202         pci_enable_msi(pdev);
 203
 204          /* request and enable interrupt */
 205         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 206
 207         err = request_threaded_irq(pdev->irq,
 208                         mei_me_irq_quick_handler,
 209                         mei_me_irq_thread_handler,
 210                         irqflags, KBUILD_MODNAME, dev);
 211         if (err) {
 212                 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
 213                        pdev->irq);
 214                 goto end;
 215         }
 216
 217         if (mei_start(dev)) {
 218                 dev_err(&pdev->dev, "init hw failure.\n");
 219                 err = -ENODEV;
 220                 goto release_irq;
 221         }
 222
 223         pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
 224         pm_runtime_use_autosuspend(&pdev->dev);
 225
 226         err = mei_register(dev, &pdev->dev);
 227         if (err)
 228                 goto stop;
 229
 230         pci_set_drvdata(pdev, dev);
 231
 232         /*
 233          * MEI requires to resume from runtime suspend mode
 234          * in order to perform link reset flow upon system suspend.
 235          */
 236         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
 237
 238         /*
 239          * ME maps runtime suspend/resume to D0i states,
 240          * hence we need to go around native PCI runtime service which
 241          * eventually brings the device into D3cold/hot state,
 242          * but the mei device cannot wake up from D3 unlike from D0i3.
 243          * To get around the PCI device native runtime pm,
 244          * ME uses runtime pm domain handlers which take precedence
 245          * over the driver's pm handlers.
 246          */
 247         mei_me_set_pm_domain(dev);
 248
 249         if (mei_pg_is_enabled(dev)) {
 250                 pm_runtime_put_noidle(&pdev->dev);
 251                 if (hw->d0i3_supported)
 252                         pm_runtime_allow(&pdev->dev);
 253         }
 254
 255         dev_dbg(&pdev->dev, "initialization successful.\n");
 256
 257         return 0;
 258
 259 stop:
 260         mei_stop(dev);
 261 release_irq:
 262         mei_cancel_work(dev);
 263         mei_disable_interrupts(dev);
 264         free_irq(pdev->irq, dev);
 265 end:
 266         dev_err(&pdev->dev, "initialization failed.\n");
 267         return err;
 268 }
 269
 270 /**
 271  * mei_me_shutdown - Device Removal Routine
 272  *
 273  * @pdev: PCI device structure
 274  *
 275  * mei_me_shutdown is called from the reboot notifier
 276  * it's a simplified version of remove so we go down
 277  * faster.
 278  */
 279 static void mei_me_shutdown(struct pci_dev *pdev)
 280 {
 281         struct mei_device *dev;
 282
 283         dev = pci_get_drvdata(pdev);
 284         if (!dev)
 285                 return;
 286
 287         dev_dbg(&pdev->dev, "shutdown\n");
 288         mei_stop(dev);
 289
 290         mei_me_unset_pm_domain(dev);
 291
 292         mei_disable_interrupts(dev);
 293         free_irq(pdev->irq, dev);
 294 }
 295
 296 /**
 297  * mei_me_remove - Device Removal Routine
 298  *
 299  * @pdev: PCI device structure
 300  *
 301  * mei_me_remove is called by the PCI subsystem to alert the driver
 302  * that it should release a PCI device.
 303  */
 304 static void mei_me_remove(struct pci_dev *pdev)
 305 {
 306         struct mei_device *dev;
 307
 308         dev = pci_get_drvdata(pdev);
 309         if (!dev)
 310                 return;
 311
 312         if (mei_pg_is_enabled(dev))
 313                 pm_runtime_get_noresume(&pdev->dev);
 314
 315         dev_dbg(&pdev->dev, "stop\n");
 316         mei_stop(dev);
 317
 318         mei_me_unset_pm_domain(dev);
 319
 320         mei_disable_interrupts(dev);
 321
 322         free_irq(pdev->irq, dev);
 323
 324         mei_deregister(dev);
 325 }
 326
 327 #ifdef CONFIG_PM_SLEEP
 328 static int mei_me_pci_suspend(struct device *device)
 329 {
 330         struct pci_dev *pdev = to_pci_dev(device);
 331         struct mei_device *dev = pci_get_drvdata(pdev);
 332
 333         if (!dev)
 334                 return -ENODEV;
 335
 336         dev_dbg(&pdev->dev, "suspend\n");
 337
 338         mei_stop(dev);
 339
 340         mei_disable_interrupts(dev);
 341
 342         free_irq(pdev->irq, dev);
 343         pci_disable_msi(pdev);
 344
 345         return 0;
 346 }
 347
 348 static int mei_me_pci_resume(struct device *device)
 349 {
 350         struct pci_dev *pdev = to_pci_dev(device);
 351         struct mei_device *dev;
 352         unsigned int irqflags;
 353         int err;
 354
 355         dev = pci_get_drvdata(pdev);
 356         if (!dev)
 357                 return -ENODEV;
 358
 359         pci_enable_msi(pdev);
 360
 361         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 362
 363         /* request and enable interrupt */
 364         err = request_threaded_irq(pdev->irq,
 365                         mei_me_irq_quick_handler,
 366                         mei_me_irq_thread_handler,
 367                         irqflags, KBUILD_MODNAME, dev);
 368
 369         if (err) {
 370                 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
 371                                 pdev->irq);
 372                 return err;
 373         }
 374
 375         err = mei_restart(dev);
 376         if (err)
 377                 return err;
 378
 379         /* Start timer if stopped in suspend */
 380         schedule_delayed_work(&dev->timer_work, HZ);
 381
 382         return 0;
 383 }
 384 #endif /* CONFIG_PM_SLEEP */
 385
 386 #ifdef CONFIG_PM
 387 static int mei_me_pm_runtime_idle(struct device *device)
 388 {
 389         struct pci_dev *pdev = to_pci_dev(device);
 390         struct mei_device *dev;
 391
 392         dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
 393
 394         dev = pci_get_drvdata(pdev);
 395         if (!dev)
 396                 return -ENODEV;
 397         if (mei_write_is_idle(dev))
 398                 pm_runtime_autosuspend(device);
 399
 400         return -EBUSY;
 401 }
 402
 403 static int mei_me_pm_runtime_suspend(struct device *device)
 404 {
 405         struct pci_dev *pdev = to_pci_dev(device);
 406         struct mei_device *dev;
 407         int ret;
 408
 409         dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
 410
 411         dev = pci_get_drvdata(pdev);
 412         if (!dev)
 413                 return -ENODEV;
 414
 415         mutex_lock(&dev->device_lock);
 416
 417         if (mei_write_is_idle(dev))
 418                 ret = mei_me_pg_enter_sync(dev);
 419         else
 420                 ret = -EAGAIN;
 421
 422         mutex_unlock(&dev->device_lock);
 423
 424         dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
 425
 426         if (ret && ret != -EAGAIN)
 427                 schedule_work(&dev->reset_work);
 428
 429         return ret;
 430 }
 431
 432 static int mei_me_pm_runtime_resume(struct device *device)
 433 {
 434         struct pci_dev *pdev = to_pci_dev(device);
 435         struct mei_device *dev;
 436         int ret;
 437
 438         dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
 439
 440         dev = pci_get_drvdata(pdev);
 441         if (!dev)
 442                 return -ENODEV;
 443
 444         mutex_lock(&dev->device_lock);
 445
 446         ret = mei_me_pg_exit_sync(dev);
 447
 448         mutex_unlock(&dev->device_lock);
 449
 450         dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
 451
 452         if (ret)
 453                 schedule_work(&dev->reset_work);
 454
 455         return ret;
 456 }
 457
 458 /**
 459  * mei_me_set_pm_domain - fill and set pm domain structure for device
 460  *
 461  * @dev: mei_device
 462  */
 463 static inline void mei_me_set_pm_domain(struct mei_device *dev)
 464 {
 465         struct pci_dev *pdev  = to_pci_dev(dev->dev);
 466
 467         if (pdev->dev.bus && pdev->dev.bus->pm) {
 468                 dev->pg_domain.ops = *pdev->dev.bus->pm;
 469
 470                 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
 471                 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
 472                 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
 473
 474                 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
 475         }
 476 }
 477
 478 /**
 479  * mei_me_unset_pm_domain - clean pm domain structure for device
 480  *
 481  * @dev: mei_device
 482  */
 483 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
 484 {
 485         /* stop using pm callbacks if any */
 486         dev_pm_domain_set(dev->dev, NULL);
 487 }
 488
 489 static const struct dev_pm_ops mei_me_pm_ops = {
 490         SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
 491                                 mei_me_pci_resume)
 492         SET_RUNTIME_PM_OPS(
 493                 mei_me_pm_runtime_suspend,
 494                 mei_me_pm_runtime_resume,
 495                 mei_me_pm_runtime_idle)
 496 };
 497
 498 #define MEI_ME_PM_OPS   (&mei_me_pm_ops)
 499 #else
 500 #define MEI_ME_PM_OPS   NULL
 501 #endif /* CONFIG_PM */
 502 /*
 503  *  PCI driver structure
 504  */
 505 static struct pci_driver mei_me_driver = {
 506         .name = KBUILD_MODNAME,
 507         .id_table = mei_me_pci_tbl,
 508         .probe = mei_me_probe,
 509         .remove = mei_me_remove,
 510         .shutdown = mei_me_shutdown,
 511         .driver.pm = MEI_ME_PM_OPS,
 512         .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 513 };
 514
 515 module_pci_driver(mei_me_driver);
 516
 517 MODULE_AUTHOR("Intel Corporation");
 518 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
 519 MODULE_LICENSE("GPL v2");