drivers/misc/habanalabs/include/goya/asic_reg/tpc5_qm_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2016-2018 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 /************************************
   9  ** This is an auto-generated file **
  10  **       DO NOT EDIT BELOW        **
  11  ************************************/
  12
  13 #ifndef ASIC_REG_TPC5_QM_REGS_H_
  14 #define ASIC_REG_TPC5_QM_REGS_H_
  15
  16 /*
  17  *****************************************
  18  *   TPC5_QM (Prototype: QMAN)
  19  *****************************************
  20  */
  21
  22 #define mmTPC5_QM_GLBL_CFG0                                          0xF48000
  23
  24 #define mmTPC5_QM_GLBL_CFG1                                          0xF48004
  25
  26 #define mmTPC5_QM_GLBL_PROT                                          0xF48008
  27
  28 #define mmTPC5_QM_GLBL_ERR_CFG                                       0xF4800C
  29
  30 #define mmTPC5_QM_GLBL_ERR_ADDR_LO                                   0xF48010
  31
  32 #define mmTPC5_QM_GLBL_ERR_ADDR_HI                                   0xF48014
  33
  34 #define mmTPC5_QM_GLBL_ERR_WDATA                                     0xF48018
  35
  36 #define mmTPC5_QM_GLBL_SECURE_PROPS                                  0xF4801C
  37
  38 #define mmTPC5_QM_GLBL_NON_SECURE_PROPS                              0xF48020
  39
  40 #define mmTPC5_QM_GLBL_STS0                                          0xF48024
  41
  42 #define mmTPC5_QM_GLBL_STS1                                          0xF48028
  43
  44 #define mmTPC5_QM_PQ_BASE_LO                                         0xF48060
  45
  46 #define mmTPC5_QM_PQ_BASE_HI                                         0xF48064
  47
  48 #define mmTPC5_QM_PQ_SIZE                                            0xF48068
  49
  50 #define mmTPC5_QM_PQ_PI                                              0xF4806C
  51
  52 #define mmTPC5_QM_PQ_CI                                              0xF48070
  53
  54 #define mmTPC5_QM_PQ_CFG0                                            0xF48074
  55
  56 #define mmTPC5_QM_PQ_CFG1                                            0xF48078
  57
  58 #define mmTPC5_QM_PQ_ARUSER                                          0xF4807C
  59
  60 #define mmTPC5_QM_PQ_PUSH0                                           0xF48080
  61
  62 #define mmTPC5_QM_PQ_PUSH1                                           0xF48084
  63
  64 #define mmTPC5_QM_PQ_PUSH2                                           0xF48088
  65
  66 #define mmTPC5_QM_PQ_PUSH3                                           0xF4808C
  67
  68 #define mmTPC5_QM_PQ_STS0                                            0xF48090
  69
  70 #define mmTPC5_QM_PQ_STS1                                            0xF48094
  71
  72 #define mmTPC5_QM_PQ_RD_RATE_LIM_EN                                  0xF480A0
  73
  74 #define mmTPC5_QM_PQ_RD_RATE_LIM_RST_TOKEN                           0xF480A4
  75
  76 #define mmTPC5_QM_PQ_RD_RATE_LIM_SAT                                 0xF480A8
  77
  78 #define mmTPC5_QM_PQ_RD_RATE_LIM_TOUT                                0xF480AC
  79
  80 #define mmTPC5_QM_CQ_CFG0                                            0xF480B0
  81
  82 #define mmTPC5_QM_CQ_CFG1                                            0xF480B4
  83
  84 #define mmTPC5_QM_CQ_ARUSER                                          0xF480B8
  85
  86 #define mmTPC5_QM_CQ_PTR_LO                                          0xF480C0
  87
  88 #define mmTPC5_QM_CQ_PTR_HI                                          0xF480C4
  89
  90 #define mmTPC5_QM_CQ_TSIZE                                           0xF480C8
  91
  92 #define mmTPC5_QM_CQ_CTL                                             0xF480CC
  93
  94 #define mmTPC5_QM_CQ_PTR_LO_STS                                      0xF480D4
  95
  96 #define mmTPC5_QM_CQ_PTR_HI_STS                                      0xF480D8
  97
  98 #define mmTPC5_QM_CQ_TSIZE_STS                                       0xF480DC
  99
 100 #define mmTPC5_QM_CQ_CTL_STS                                         0xF480E0
 101
 102 #define mmTPC5_QM_CQ_STS0                                            0xF480E4
 103
 104 #define mmTPC5_QM_CQ_STS1                                            0xF480E8
 105
 106 #define mmTPC5_QM_CQ_RD_RATE_LIM_EN                                  0xF480F0
 107
 108 #define mmTPC5_QM_CQ_RD_RATE_LIM_RST_TOKEN                           0xF480F4
 109
 110 #define mmTPC5_QM_CQ_RD_RATE_LIM_SAT                                 0xF480F8
 111
 112 #define mmTPC5_QM_CQ_RD_RATE_LIM_TOUT                                0xF480FC
 113
 114 #define mmTPC5_QM_CQ_IFIFO_CNT                                       0xF48108
 115
 116 #define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO                               0xF48120
 117
 118 #define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI                               0xF48124
 119
 120 #define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO                               0xF48128
 121
 122 #define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI                               0xF4812C
 123
 124 #define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO                               0xF48130
 125
 126 #define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI                               0xF48134
 127
 128 #define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO                               0xF48138
 129
 130 #define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI                               0xF4813C
 131
 132 #define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET                               0xF48140
 133
 134 #define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET                         0xF48144
 135
 136 #define mmTPC5_QM_CP_LDMA_SRC_BASE_HI_OFFSET                         0xF48148
 137
 138 #define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET                         0xF4814C
 139
 140 #define mmTPC5_QM_CP_LDMA_DST_BASE_HI_OFFSET                         0xF48150
 141
 142 #define mmTPC5_QM_CP_LDMA_COMMIT_OFFSET                              0xF48154
 143
 144 #define mmTPC5_QM_CP_FENCE0_RDATA                                    0xF48158
 145
 146 #define mmTPC5_QM_CP_FENCE1_RDATA                                    0xF4815C
 147
 148 #define mmTPC5_QM_CP_FENCE2_RDATA                                    0xF48160
 149
 150 #define mmTPC5_QM_CP_FENCE3_RDATA                                    0xF48164
 151
 152 #define mmTPC5_QM_CP_FENCE0_CNT                                      0xF48168
 153
 154 #define mmTPC5_QM_CP_FENCE1_CNT                                      0xF4816C
 155
 156 #define mmTPC5_QM_CP_FENCE2_CNT                                      0xF48170
 157
 158 #define mmTPC5_QM_CP_FENCE3_CNT                                      0xF48174
 159
 160 #define mmTPC5_QM_CP_STS                                             0xF48178
 161
 162 #define mmTPC5_QM_CP_CURRENT_INST_LO                                 0xF4817C
 163
 164 #define mmTPC5_QM_CP_CURRENT_INST_HI                                 0xF48180
 165
 166 #define mmTPC5_QM_CP_BARRIER_CFG                                     0xF48184
 167
 168 #define mmTPC5_QM_CP_DBG_0                                           0xF48188
 169
 170 #define mmTPC5_QM_PQ_BUF_ADDR                                        0xF48300
 171
 172 #define mmTPC5_QM_PQ_BUF_RDATA                                       0xF48304
 173
 174 #define mmTPC5_QM_CQ_BUF_ADDR                                        0xF48308
 175
 176 #define mmTPC5_QM_CQ_BUF_RDATA                                       0xF4830C
 177
 178 #endif /* ASIC_REG_TPC5_QM_REGS_H_ */