Linux-libre 5.3.12-gnu
[librecmc/linux-libre.git] / drivers / misc / habanalabs / include / goya / asic_reg / tpc1_rtr_regs.h
1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2018 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12
13 #ifndef ASIC_REG_TPC1_RTR_REGS_H_
14 #define ASIC_REG_TPC1_RTR_REGS_H_
15
16 /*
17  *****************************************
18  *   TPC1_RTR (Prototype: TPC_RTR)
19  *****************************************
20  */
21
22 #define mmTPC1_RTR_HBW_RD_RQ_E_ARB                                   0xE40100
23
24 #define mmTPC1_RTR_HBW_RD_RQ_W_ARB                                   0xE40104
25
26 #define mmTPC1_RTR_HBW_RD_RQ_N_ARB                                   0xE40108
27
28 #define mmTPC1_RTR_HBW_RD_RQ_S_ARB                                   0xE4010C
29
30 #define mmTPC1_RTR_HBW_RD_RQ_L_ARB                                   0xE40110
31
32 #define mmTPC1_RTR_HBW_E_ARB_MAX                                     0xE40120
33
34 #define mmTPC1_RTR_HBW_W_ARB_MAX                                     0xE40124
35
36 #define mmTPC1_RTR_HBW_N_ARB_MAX                                     0xE40128
37
38 #define mmTPC1_RTR_HBW_S_ARB_MAX                                     0xE4012C
39
40 #define mmTPC1_RTR_HBW_L_ARB_MAX                                     0xE40130
41
42 #define mmTPC1_RTR_HBW_RD_RS_E_ARB                                   0xE40140
43
44 #define mmTPC1_RTR_HBW_RD_RS_W_ARB                                   0xE40144
45
46 #define mmTPC1_RTR_HBW_RD_RS_N_ARB                                   0xE40148
47
48 #define mmTPC1_RTR_HBW_RD_RS_S_ARB                                   0xE4014C
49
50 #define mmTPC1_RTR_HBW_RD_RS_L_ARB                                   0xE40150
51
52 #define mmTPC1_RTR_HBW_WR_RQ_E_ARB                                   0xE40170
53
54 #define mmTPC1_RTR_HBW_WR_RQ_W_ARB                                   0xE40174
55
56 #define mmTPC1_RTR_HBW_WR_RQ_N_ARB                                   0xE40178
57
58 #define mmTPC1_RTR_HBW_WR_RQ_S_ARB                                   0xE4017C
59
60 #define mmTPC1_RTR_HBW_WR_RQ_L_ARB                                   0xE40180
61
62 #define mmTPC1_RTR_HBW_WR_RS_E_ARB                                   0xE40190
63
64 #define mmTPC1_RTR_HBW_WR_RS_W_ARB                                   0xE40194
65
66 #define mmTPC1_RTR_HBW_WR_RS_N_ARB                                   0xE40198
67
68 #define mmTPC1_RTR_HBW_WR_RS_S_ARB                                   0xE4019C
69
70 #define mmTPC1_RTR_HBW_WR_RS_L_ARB                                   0xE401A0
71
72 #define mmTPC1_RTR_LBW_RD_RQ_E_ARB                                   0xE40200
73
74 #define mmTPC1_RTR_LBW_RD_RQ_W_ARB                                   0xE40204
75
76 #define mmTPC1_RTR_LBW_RD_RQ_N_ARB                                   0xE40208
77
78 #define mmTPC1_RTR_LBW_RD_RQ_S_ARB                                   0xE4020C
79
80 #define mmTPC1_RTR_LBW_RD_RQ_L_ARB                                   0xE40210
81
82 #define mmTPC1_RTR_LBW_E_ARB_MAX                                     0xE40220
83
84 #define mmTPC1_RTR_LBW_W_ARB_MAX                                     0xE40224
85
86 #define mmTPC1_RTR_LBW_N_ARB_MAX                                     0xE40228
87
88 #define mmTPC1_RTR_LBW_S_ARB_MAX                                     0xE4022C
89
90 #define mmTPC1_RTR_LBW_L_ARB_MAX                                     0xE40230
91
92 #define mmTPC1_RTR_LBW_RD_RS_E_ARB                                   0xE40250
93
94 #define mmTPC1_RTR_LBW_RD_RS_W_ARB                                   0xE40254
95
96 #define mmTPC1_RTR_LBW_RD_RS_N_ARB                                   0xE40258
97
98 #define mmTPC1_RTR_LBW_RD_RS_S_ARB                                   0xE4025C
99
100 #define mmTPC1_RTR_LBW_RD_RS_L_ARB                                   0xE40260
101
102 #define mmTPC1_RTR_LBW_WR_RQ_E_ARB                                   0xE40270
103
104 #define mmTPC1_RTR_LBW_WR_RQ_W_ARB                                   0xE40274
105
106 #define mmTPC1_RTR_LBW_WR_RQ_N_ARB                                   0xE40278
107
108 #define mmTPC1_RTR_LBW_WR_RQ_S_ARB                                   0xE4027C
109
110 #define mmTPC1_RTR_LBW_WR_RQ_L_ARB                                   0xE40280
111
112 #define mmTPC1_RTR_LBW_WR_RS_E_ARB                                   0xE40290
113
114 #define mmTPC1_RTR_LBW_WR_RS_W_ARB                                   0xE40294
115
116 #define mmTPC1_RTR_LBW_WR_RS_N_ARB                                   0xE40298
117
118 #define mmTPC1_RTR_LBW_WR_RS_S_ARB                                   0xE4029C
119
120 #define mmTPC1_RTR_LBW_WR_RS_L_ARB                                   0xE402A0
121
122 #define mmTPC1_RTR_DBG_E_ARB                                         0xE40300
123
124 #define mmTPC1_RTR_DBG_W_ARB                                         0xE40304
125
126 #define mmTPC1_RTR_DBG_N_ARB                                         0xE40308
127
128 #define mmTPC1_RTR_DBG_S_ARB                                         0xE4030C
129
130 #define mmTPC1_RTR_DBG_L_ARB                                         0xE40310
131
132 #define mmTPC1_RTR_DBG_E_ARB_MAX                                     0xE40320
133
134 #define mmTPC1_RTR_DBG_W_ARB_MAX                                     0xE40324
135
136 #define mmTPC1_RTR_DBG_N_ARB_MAX                                     0xE40328
137
138 #define mmTPC1_RTR_DBG_S_ARB_MAX                                     0xE4032C
139
140 #define mmTPC1_RTR_DBG_L_ARB_MAX                                     0xE40330
141
142 #define mmTPC1_RTR_SPLIT_COEF_0                                      0xE40400
143
144 #define mmTPC1_RTR_SPLIT_COEF_1                                      0xE40404
145
146 #define mmTPC1_RTR_SPLIT_COEF_2                                      0xE40408
147
148 #define mmTPC1_RTR_SPLIT_COEF_3                                      0xE4040C
149
150 #define mmTPC1_RTR_SPLIT_COEF_4                                      0xE40410
151
152 #define mmTPC1_RTR_SPLIT_COEF_5                                      0xE40414
153
154 #define mmTPC1_RTR_SPLIT_COEF_6                                      0xE40418
155
156 #define mmTPC1_RTR_SPLIT_COEF_7                                      0xE4041C
157
158 #define mmTPC1_RTR_SPLIT_COEF_8                                      0xE40420
159
160 #define mmTPC1_RTR_SPLIT_COEF_9                                      0xE40424
161
162 #define mmTPC1_RTR_SPLIT_CFG                                         0xE40440
163
164 #define mmTPC1_RTR_SPLIT_RD_SAT                                      0xE40444
165
166 #define mmTPC1_RTR_SPLIT_RD_RST_TOKEN                                0xE40448
167
168 #define mmTPC1_RTR_SPLIT_RD_TIMEOUT_0                                0xE4044C
169
170 #define mmTPC1_RTR_SPLIT_RD_TIMEOUT_1                                0xE40450
171
172 #define mmTPC1_RTR_SPLIT_WR_SAT                                      0xE40454
173
174 #define mmTPC1_RTR_WPLIT_WR_TST_TOLEN                                0xE40458
175
176 #define mmTPC1_RTR_SPLIT_WR_TIMEOUT_0                                0xE4045C
177
178 #define mmTPC1_RTR_SPLIT_WR_TIMEOUT_1                                0xE40460
179
180 #define mmTPC1_RTR_HBW_RANGE_HIT                                     0xE40470
181
182 #define mmTPC1_RTR_HBW_RANGE_MASK_L_0                                0xE40480
183
184 #define mmTPC1_RTR_HBW_RANGE_MASK_L_1                                0xE40484
185
186 #define mmTPC1_RTR_HBW_RANGE_MASK_L_2                                0xE40488
187
188 #define mmTPC1_RTR_HBW_RANGE_MASK_L_3                                0xE4048C
189
190 #define mmTPC1_RTR_HBW_RANGE_MASK_L_4                                0xE40490
191
192 #define mmTPC1_RTR_HBW_RANGE_MASK_L_5                                0xE40494
193
194 #define mmTPC1_RTR_HBW_RANGE_MASK_L_6                                0xE40498
195
196 #define mmTPC1_RTR_HBW_RANGE_MASK_L_7                                0xE4049C
197
198 #define mmTPC1_RTR_HBW_RANGE_MASK_H_0                                0xE404A0
199
200 #define mmTPC1_RTR_HBW_RANGE_MASK_H_1                                0xE404A4
201
202 #define mmTPC1_RTR_HBW_RANGE_MASK_H_2                                0xE404A8
203
204 #define mmTPC1_RTR_HBW_RANGE_MASK_H_3                                0xE404AC
205
206 #define mmTPC1_RTR_HBW_RANGE_MASK_H_4                                0xE404B0
207
208 #define mmTPC1_RTR_HBW_RANGE_MASK_H_5                                0xE404B4
209
210 #define mmTPC1_RTR_HBW_RANGE_MASK_H_6                                0xE404B8
211
212 #define mmTPC1_RTR_HBW_RANGE_MASK_H_7                                0xE404BC
213
214 #define mmTPC1_RTR_HBW_RANGE_BASE_L_0                                0xE404C0
215
216 #define mmTPC1_RTR_HBW_RANGE_BASE_L_1                                0xE404C4
217
218 #define mmTPC1_RTR_HBW_RANGE_BASE_L_2                                0xE404C8
219
220 #define mmTPC1_RTR_HBW_RANGE_BASE_L_3                                0xE404CC
221
222 #define mmTPC1_RTR_HBW_RANGE_BASE_L_4                                0xE404D0
223
224 #define mmTPC1_RTR_HBW_RANGE_BASE_L_5                                0xE404D4
225
226 #define mmTPC1_RTR_HBW_RANGE_BASE_L_6                                0xE404D8
227
228 #define mmTPC1_RTR_HBW_RANGE_BASE_L_7                                0xE404DC
229
230 #define mmTPC1_RTR_HBW_RANGE_BASE_H_0                                0xE404E0
231
232 #define mmTPC1_RTR_HBW_RANGE_BASE_H_1                                0xE404E4
233
234 #define mmTPC1_RTR_HBW_RANGE_BASE_H_2                                0xE404E8
235
236 #define mmTPC1_RTR_HBW_RANGE_BASE_H_3                                0xE404EC
237
238 #define mmTPC1_RTR_HBW_RANGE_BASE_H_4                                0xE404F0
239
240 #define mmTPC1_RTR_HBW_RANGE_BASE_H_5                                0xE404F4
241
242 #define mmTPC1_RTR_HBW_RANGE_BASE_H_6                                0xE404F8
243
244 #define mmTPC1_RTR_HBW_RANGE_BASE_H_7                                0xE404FC
245
246 #define mmTPC1_RTR_LBW_RANGE_HIT                                     0xE40500
247
248 #define mmTPC1_RTR_LBW_RANGE_MASK_0                                  0xE40510
249
250 #define mmTPC1_RTR_LBW_RANGE_MASK_1                                  0xE40514
251
252 #define mmTPC1_RTR_LBW_RANGE_MASK_2                                  0xE40518
253
254 #define mmTPC1_RTR_LBW_RANGE_MASK_3                                  0xE4051C
255
256 #define mmTPC1_RTR_LBW_RANGE_MASK_4                                  0xE40520
257
258 #define mmTPC1_RTR_LBW_RANGE_MASK_5                                  0xE40524
259
260 #define mmTPC1_RTR_LBW_RANGE_MASK_6                                  0xE40528
261
262 #define mmTPC1_RTR_LBW_RANGE_MASK_7                                  0xE4052C
263
264 #define mmTPC1_RTR_LBW_RANGE_MASK_8                                  0xE40530
265
266 #define mmTPC1_RTR_LBW_RANGE_MASK_9                                  0xE40534
267
268 #define mmTPC1_RTR_LBW_RANGE_MASK_10                                 0xE40538
269
270 #define mmTPC1_RTR_LBW_RANGE_MASK_11                                 0xE4053C
271
272 #define mmTPC1_RTR_LBW_RANGE_MASK_12                                 0xE40540
273
274 #define mmTPC1_RTR_LBW_RANGE_MASK_13                                 0xE40544
275
276 #define mmTPC1_RTR_LBW_RANGE_MASK_14                                 0xE40548
277
278 #define mmTPC1_RTR_LBW_RANGE_MASK_15                                 0xE4054C
279
280 #define mmTPC1_RTR_LBW_RANGE_BASE_0                                  0xE40550
281
282 #define mmTPC1_RTR_LBW_RANGE_BASE_1                                  0xE40554
283
284 #define mmTPC1_RTR_LBW_RANGE_BASE_2                                  0xE40558
285
286 #define mmTPC1_RTR_LBW_RANGE_BASE_3                                  0xE4055C
287
288 #define mmTPC1_RTR_LBW_RANGE_BASE_4                                  0xE40560
289
290 #define mmTPC1_RTR_LBW_RANGE_BASE_5                                  0xE40564
291
292 #define mmTPC1_RTR_LBW_RANGE_BASE_6                                  0xE40568
293
294 #define mmTPC1_RTR_LBW_RANGE_BASE_7                                  0xE4056C
295
296 #define mmTPC1_RTR_LBW_RANGE_BASE_8                                  0xE40570
297
298 #define mmTPC1_RTR_LBW_RANGE_BASE_9                                  0xE40574
299
300 #define mmTPC1_RTR_LBW_RANGE_BASE_10                                 0xE40578
301
302 #define mmTPC1_RTR_LBW_RANGE_BASE_11                                 0xE4057C
303
304 #define mmTPC1_RTR_LBW_RANGE_BASE_12                                 0xE40580
305
306 #define mmTPC1_RTR_LBW_RANGE_BASE_13                                 0xE40584
307
308 #define mmTPC1_RTR_LBW_RANGE_BASE_14                                 0xE40588
309
310 #define mmTPC1_RTR_LBW_RANGE_BASE_15                                 0xE4058C
311
312 #define mmTPC1_RTR_RGLTR                                             0xE40590
313
314 #define mmTPC1_RTR_RGLTR_WR_RESULT                                   0xE40594
315
316 #define mmTPC1_RTR_RGLTR_RD_RESULT                                   0xE40598
317
318 #define mmTPC1_RTR_SCRAMB_EN                                         0xE40600
319
320 #define mmTPC1_RTR_NON_LIN_SCRAMB                                    0xE40604
321
322 #endif /* ASIC_REG_TPC1_RTR_REGS_H_ */