1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2018 HabanaLabs, Ltd.
8 /************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
13 #ifndef ASIC_REG_PSOC_MME_PLL_REGS_H_
14 #define ASIC_REG_PSOC_MME_PLL_REGS_H_
17 *****************************************
18 * PSOC_MME_PLL (Prototype: PLL)
19 *****************************************
22 #define mmPSOC_MME_PLL_NR 0xC71100
24 #define mmPSOC_MME_PLL_NF 0xC71104
26 #define mmPSOC_MME_PLL_OD 0xC71108
28 #define mmPSOC_MME_PLL_NB 0xC7110C
30 #define mmPSOC_MME_PLL_CFG 0xC71110
32 #define mmPSOC_MME_PLL_LOSE_MASK 0xC71120
34 #define mmPSOC_MME_PLL_LOCK_INTR 0xC71128
36 #define mmPSOC_MME_PLL_LOCK_BYPASS 0xC7112C
38 #define mmPSOC_MME_PLL_DATA_CHNG 0xC71130
40 #define mmPSOC_MME_PLL_RST 0xC71134
42 #define mmPSOC_MME_PLL_SLIP_WD_CNTR 0xC71150
44 #define mmPSOC_MME_PLL_DIV_FACTOR_0 0xC71200
46 #define mmPSOC_MME_PLL_DIV_FACTOR_1 0xC71204
48 #define mmPSOC_MME_PLL_DIV_FACTOR_2 0xC71208
50 #define mmPSOC_MME_PLL_DIV_FACTOR_3 0xC7120C
52 #define mmPSOC_MME_PLL_DIV_FACTOR_CMD_0 0xC71220
54 #define mmPSOC_MME_PLL_DIV_FACTOR_CMD_1 0xC71224
56 #define mmPSOC_MME_PLL_DIV_FACTOR_CMD_2 0xC71228
58 #define mmPSOC_MME_PLL_DIV_FACTOR_CMD_3 0xC7122C
60 #define mmPSOC_MME_PLL_DIV_SEL_0 0xC71280
62 #define mmPSOC_MME_PLL_DIV_SEL_1 0xC71284
64 #define mmPSOC_MME_PLL_DIV_SEL_2 0xC71288
66 #define mmPSOC_MME_PLL_DIV_SEL_3 0xC7128C
68 #define mmPSOC_MME_PLL_DIV_EN_0 0xC712A0
70 #define mmPSOC_MME_PLL_DIV_EN_1 0xC712A4
72 #define mmPSOC_MME_PLL_DIV_EN_2 0xC712A8
74 #define mmPSOC_MME_PLL_DIV_EN_3 0xC712AC
76 #define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_0 0xC712C0
78 #define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_1 0xC712C4
80 #define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_2 0xC712C8
82 #define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_3 0xC712CC
84 #define mmPSOC_MME_PLL_CLK_GATER 0xC71300
86 #define mmPSOC_MME_PLL_CLK_RLX_0 0xC71310
88 #define mmPSOC_MME_PLL_CLK_RLX_1 0xC71314
90 #define mmPSOC_MME_PLL_CLK_RLX_2 0xC71318
92 #define mmPSOC_MME_PLL_CLK_RLX_3 0xC7131C
94 #define mmPSOC_MME_PLL_REF_CNTR_PERIOD 0xC71400
96 #define mmPSOC_MME_PLL_REF_LOW_THRESHOLD 0xC71410
98 #define mmPSOC_MME_PLL_REF_HIGH_THRESHOLD 0xC71420
100 #define mmPSOC_MME_PLL_PLL_NOT_STABLE 0xC71430
102 #define mmPSOC_MME_PLL_FREQ_CALC_EN 0xC71440
104 #endif /* ASIC_REG_PSOC_MME_PLL_REGS_H_ */