1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2018 HabanaLabs, Ltd.
8 /************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
13 #ifndef ASIC_REG_DMA_QM_4_REGS_H_
14 #define ASIC_REG_DMA_QM_4_REGS_H_
17 *****************************************
18 * DMA_QM_4 (Prototype: QMAN)
19 *****************************************
22 #define mmDMA_QM_4_GLBL_CFG0 0x420000
24 #define mmDMA_QM_4_GLBL_CFG1 0x420004
26 #define mmDMA_QM_4_GLBL_PROT 0x420008
28 #define mmDMA_QM_4_GLBL_ERR_CFG 0x42000C
30 #define mmDMA_QM_4_GLBL_ERR_ADDR_LO 0x420010
32 #define mmDMA_QM_4_GLBL_ERR_ADDR_HI 0x420014
34 #define mmDMA_QM_4_GLBL_ERR_WDATA 0x420018
36 #define mmDMA_QM_4_GLBL_SECURE_PROPS 0x42001C
38 #define mmDMA_QM_4_GLBL_NON_SECURE_PROPS 0x420020
40 #define mmDMA_QM_4_GLBL_STS0 0x420024
42 #define mmDMA_QM_4_GLBL_STS1 0x420028
44 #define mmDMA_QM_4_PQ_BASE_LO 0x420060
46 #define mmDMA_QM_4_PQ_BASE_HI 0x420064
48 #define mmDMA_QM_4_PQ_SIZE 0x420068
50 #define mmDMA_QM_4_PQ_PI 0x42006C
52 #define mmDMA_QM_4_PQ_CI 0x420070
54 #define mmDMA_QM_4_PQ_CFG0 0x420074
56 #define mmDMA_QM_4_PQ_CFG1 0x420078
58 #define mmDMA_QM_4_PQ_ARUSER 0x42007C
60 #define mmDMA_QM_4_PQ_PUSH0 0x420080
62 #define mmDMA_QM_4_PQ_PUSH1 0x420084
64 #define mmDMA_QM_4_PQ_PUSH2 0x420088
66 #define mmDMA_QM_4_PQ_PUSH3 0x42008C
68 #define mmDMA_QM_4_PQ_STS0 0x420090
70 #define mmDMA_QM_4_PQ_STS1 0x420094
72 #define mmDMA_QM_4_PQ_RD_RATE_LIM_EN 0x4200A0
74 #define mmDMA_QM_4_PQ_RD_RATE_LIM_RST_TOKEN 0x4200A4
76 #define mmDMA_QM_4_PQ_RD_RATE_LIM_SAT 0x4200A8
78 #define mmDMA_QM_4_PQ_RD_RATE_LIM_TOUT 0x4200AC
80 #define mmDMA_QM_4_CQ_CFG0 0x4200B0
82 #define mmDMA_QM_4_CQ_CFG1 0x4200B4
84 #define mmDMA_QM_4_CQ_ARUSER 0x4200B8
86 #define mmDMA_QM_4_CQ_PTR_LO 0x4200C0
88 #define mmDMA_QM_4_CQ_PTR_HI 0x4200C4
90 #define mmDMA_QM_4_CQ_TSIZE 0x4200C8
92 #define mmDMA_QM_4_CQ_CTL 0x4200CC
94 #define mmDMA_QM_4_CQ_PTR_LO_STS 0x4200D4
96 #define mmDMA_QM_4_CQ_PTR_HI_STS 0x4200D8
98 #define mmDMA_QM_4_CQ_TSIZE_STS 0x4200DC
100 #define mmDMA_QM_4_CQ_CTL_STS 0x4200E0
102 #define mmDMA_QM_4_CQ_STS0 0x4200E4
104 #define mmDMA_QM_4_CQ_STS1 0x4200E8
106 #define mmDMA_QM_4_CQ_RD_RATE_LIM_EN 0x4200F0
108 #define mmDMA_QM_4_CQ_RD_RATE_LIM_RST_TOKEN 0x4200F4
110 #define mmDMA_QM_4_CQ_RD_RATE_LIM_SAT 0x4200F8
112 #define mmDMA_QM_4_CQ_RD_RATE_LIM_TOUT 0x4200FC
114 #define mmDMA_QM_4_CQ_IFIFO_CNT 0x420108
116 #define mmDMA_QM_4_CP_MSG_BASE0_ADDR_LO 0x420120
118 #define mmDMA_QM_4_CP_MSG_BASE0_ADDR_HI 0x420124
120 #define mmDMA_QM_4_CP_MSG_BASE1_ADDR_LO 0x420128
122 #define mmDMA_QM_4_CP_MSG_BASE1_ADDR_HI 0x42012C
124 #define mmDMA_QM_4_CP_MSG_BASE2_ADDR_LO 0x420130
126 #define mmDMA_QM_4_CP_MSG_BASE2_ADDR_HI 0x420134
128 #define mmDMA_QM_4_CP_MSG_BASE3_ADDR_LO 0x420138
130 #define mmDMA_QM_4_CP_MSG_BASE3_ADDR_HI 0x42013C
132 #define mmDMA_QM_4_CP_LDMA_TSIZE_OFFSET 0x420140
134 #define mmDMA_QM_4_CP_LDMA_SRC_BASE_LO_OFFSET 0x420144
136 #define mmDMA_QM_4_CP_LDMA_SRC_BASE_HI_OFFSET 0x420148
138 #define mmDMA_QM_4_CP_LDMA_DST_BASE_LO_OFFSET 0x42014C
140 #define mmDMA_QM_4_CP_LDMA_DST_BASE_HI_OFFSET 0x420150
142 #define mmDMA_QM_4_CP_LDMA_COMMIT_OFFSET 0x420154
144 #define mmDMA_QM_4_CP_FENCE0_RDATA 0x420158
146 #define mmDMA_QM_4_CP_FENCE1_RDATA 0x42015C
148 #define mmDMA_QM_4_CP_FENCE2_RDATA 0x420160
150 #define mmDMA_QM_4_CP_FENCE3_RDATA 0x420164
152 #define mmDMA_QM_4_CP_FENCE0_CNT 0x420168
154 #define mmDMA_QM_4_CP_FENCE1_CNT 0x42016C
156 #define mmDMA_QM_4_CP_FENCE2_CNT 0x420170
158 #define mmDMA_QM_4_CP_FENCE3_CNT 0x420174
160 #define mmDMA_QM_4_CP_STS 0x420178
162 #define mmDMA_QM_4_CP_CURRENT_INST_LO 0x42017C
164 #define mmDMA_QM_4_CP_CURRENT_INST_HI 0x420180
166 #define mmDMA_QM_4_CP_BARRIER_CFG 0x420184
168 #define mmDMA_QM_4_CP_DBG_0 0x420188
170 #define mmDMA_QM_4_PQ_BUF_ADDR 0x420300
172 #define mmDMA_QM_4_PQ_BUF_RDATA 0x420304
174 #define mmDMA_QM_4_CQ_BUF_ADDR 0x420308
176 #define mmDMA_QM_4_CQ_BUF_RDATA 0x42030C
178 #endif /* ASIC_REG_DMA_QM_4_REGS_H_ */