drivers/misc/habanalabs/include/goya/asic_reg/dma_ch_0_masks.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2016-2018 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 /************************************
   9  ** This is an auto-generated file **
  10  **       DO NOT EDIT BELOW        **
  11  ************************************/
  12
  13 #ifndef ASIC_REG_DMA_CH_0_MASKS_H_
  14 #define ASIC_REG_DMA_CH_0_MASKS_H_
  15
  16 /*
  17  *****************************************
  18  *   DMA_CH_0 (Prototype: DMA_CH)
  19  *****************************************
  20  */
  21
  22 /* DMA_CH_0_CFG0 */
  23 #define DMA_CH_0_CFG0_RD_MAX_OUTSTAND_SHIFT                          0
  24 #define DMA_CH_0_CFG0_RD_MAX_OUTSTAND_MASK                           0x3FF
  25 #define DMA_CH_0_CFG0_WR_MAX_OUTSTAND_SHIFT                          16
  26 #define DMA_CH_0_CFG0_WR_MAX_OUTSTAND_MASK                           0xFFF0000
  27
  28 /* DMA_CH_0_CFG1 */
  29 #define DMA_CH_0_CFG1_RD_BUF_MAX_SIZE_SHIFT                          0
  30 #define DMA_CH_0_CFG1_RD_BUF_MAX_SIZE_MASK                           0x3FF
  31
  32 /* DMA_CH_0_ERRMSG_ADDR_LO */
  33 #define DMA_CH_0_ERRMSG_ADDR_LO_VAL_SHIFT                            0
  34 #define DMA_CH_0_ERRMSG_ADDR_LO_VAL_MASK                             0xFFFFFFFF
  35
  36 /* DMA_CH_0_ERRMSG_ADDR_HI */
  37 #define DMA_CH_0_ERRMSG_ADDR_HI_VAL_SHIFT                            0
  38 #define DMA_CH_0_ERRMSG_ADDR_HI_VAL_MASK                             0xFFFFFFFF
  39
  40 /* DMA_CH_0_ERRMSG_WDATA */
  41 #define DMA_CH_0_ERRMSG_WDATA_VAL_SHIFT                              0
  42 #define DMA_CH_0_ERRMSG_WDATA_VAL_MASK                               0xFFFFFFFF
  43
  44 /* DMA_CH_0_RD_COMP_ADDR_LO */
  45 #define DMA_CH_0_RD_COMP_ADDR_LO_VAL_SHIFT                           0
  46 #define DMA_CH_0_RD_COMP_ADDR_LO_VAL_MASK                            0xFFFFFFFF
  47
  48 /* DMA_CH_0_RD_COMP_ADDR_HI */
  49 #define DMA_CH_0_RD_COMP_ADDR_HI_VAL_SHIFT                           0
  50 #define DMA_CH_0_RD_COMP_ADDR_HI_VAL_MASK                            0xFFFFFFFF
  51
  52 /* DMA_CH_0_RD_COMP_WDATA */
  53 #define DMA_CH_0_RD_COMP_WDATA_VAL_SHIFT                             0
  54 #define DMA_CH_0_RD_COMP_WDATA_VAL_MASK                              0xFFFFFFFF
  55
  56 /* DMA_CH_0_WR_COMP_ADDR_LO */
  57 #define DMA_CH_0_WR_COMP_ADDR_LO_VAL_SHIFT                           0
  58 #define DMA_CH_0_WR_COMP_ADDR_LO_VAL_MASK                            0xFFFFFFFF
  59
  60 /* DMA_CH_0_WR_COMP_ADDR_HI */
  61 #define DMA_CH_0_WR_COMP_ADDR_HI_VAL_SHIFT                           0
  62 #define DMA_CH_0_WR_COMP_ADDR_HI_VAL_MASK                            0xFFFFFFFF
  63
  64 /* DMA_CH_0_WR_COMP_WDATA */
  65 #define DMA_CH_0_WR_COMP_WDATA_VAL_SHIFT                             0
  66 #define DMA_CH_0_WR_COMP_WDATA_VAL_MASK                              0xFFFFFFFF
  67
  68 /* DMA_CH_0_LDMA_SRC_ADDR_LO */
  69 #define DMA_CH_0_LDMA_SRC_ADDR_LO_VAL_SHIFT                          0
  70 #define DMA_CH_0_LDMA_SRC_ADDR_LO_VAL_MASK                           0xFFFFFFFF
  71
  72 /* DMA_CH_0_LDMA_SRC_ADDR_HI */
  73 #define DMA_CH_0_LDMA_SRC_ADDR_HI_VAL_SHIFT                          0
  74 #define DMA_CH_0_LDMA_SRC_ADDR_HI_VAL_MASK                           0xFFFFFFFF
  75
  76 /* DMA_CH_0_LDMA_DST_ADDR_LO */
  77 #define DMA_CH_0_LDMA_DST_ADDR_LO_VAL_SHIFT                          0
  78 #define DMA_CH_0_LDMA_DST_ADDR_LO_VAL_MASK                           0xFFFFFFFF
  79
  80 /* DMA_CH_0_LDMA_DST_ADDR_HI */
  81 #define DMA_CH_0_LDMA_DST_ADDR_HI_VAL_SHIFT                          0
  82 #define DMA_CH_0_LDMA_DST_ADDR_HI_VAL_MASK                           0xFFFFFFFF
  83
  84 /* DMA_CH_0_LDMA_TSIZE */
  85 #define DMA_CH_0_LDMA_TSIZE_VAL_SHIFT                                0
  86 #define DMA_CH_0_LDMA_TSIZE_VAL_MASK                                 0xFFFFFFFF
  87
  88 /* DMA_CH_0_COMIT_TRANSFER */
  89 #define DMA_CH_0_COMIT_TRANSFER_PCI_UPS_WKORDR_SHIFT                 0
  90 #define DMA_CH_0_COMIT_TRANSFER_PCI_UPS_WKORDR_MASK                  0x1
  91 #define DMA_CH_0_COMIT_TRANSFER_RD_COMP_EN_SHIFT                     1
  92 #define DMA_CH_0_COMIT_TRANSFER_RD_COMP_EN_MASK                      0x2
  93 #define DMA_CH_0_COMIT_TRANSFER_WR_COMP_EN_SHIFT                     2
  94 #define DMA_CH_0_COMIT_TRANSFER_WR_COMP_EN_MASK                      0x4
  95 #define DMA_CH_0_COMIT_TRANSFER_NOSNOOP_SHIFT                        3
  96 #define DMA_CH_0_COMIT_TRANSFER_NOSNOOP_MASK                         0x8
  97 #define DMA_CH_0_COMIT_TRANSFER_SRC_ADDR_INC_DIS_SHIFT               4
  98 #define DMA_CH_0_COMIT_TRANSFER_SRC_ADDR_INC_DIS_MASK                0x10
  99 #define DMA_CH_0_COMIT_TRANSFER_DST_ADDR_INC_DIS_SHIFT               5
 100 #define DMA_CH_0_COMIT_TRANSFER_DST_ADDR_INC_DIS_MASK                0x20
 101 #define DMA_CH_0_COMIT_TRANSFER_MEM_SET_SHIFT                        6
 102 #define DMA_CH_0_COMIT_TRANSFER_MEM_SET_MASK                         0x40
 103 #define DMA_CH_0_COMIT_TRANSFER_MOD_TENSOR_SHIFT                     15
 104 #define DMA_CH_0_COMIT_TRANSFER_MOD_TENSOR_MASK                      0x8000
 105 #define DMA_CH_0_COMIT_TRANSFER_CTL_SHIFT                            16
 106 #define DMA_CH_0_COMIT_TRANSFER_CTL_MASK                             0xFFFF0000
 107
 108 /* DMA_CH_0_STS0 */
 109 #define DMA_CH_0_STS0_DMA_BUSY_SHIFT                                 0
 110 #define DMA_CH_0_STS0_DMA_BUSY_MASK                                  0x1
 111 #define DMA_CH_0_STS0_RD_STS_CTX_FULL_SHIFT                          1
 112 #define DMA_CH_0_STS0_RD_STS_CTX_FULL_MASK                           0x2
 113 #define DMA_CH_0_STS0_WR_STS_CTX_FULL_SHIFT                          2
 114 #define DMA_CH_0_STS0_WR_STS_CTX_FULL_MASK                           0x4
 115
 116 /* DMA_CH_0_STS1 */
 117 #define DMA_CH_0_STS1_RD_STS_CTX_CNT_SHIFT                           0
 118 #define DMA_CH_0_STS1_RD_STS_CTX_CNT_MASK                            0xFFFFFFFF
 119
 120 /* DMA_CH_0_STS2 */
 121 #define DMA_CH_0_STS2_WR_STS_CTX_CNT_SHIFT                           0
 122 #define DMA_CH_0_STS2_WR_STS_CTX_CNT_MASK                            0xFFFFFFFF
 123
 124 /* DMA_CH_0_STS3 */
 125 #define DMA_CH_0_STS3_RD_STS_TRN_CNT_SHIFT                           0
 126 #define DMA_CH_0_STS3_RD_STS_TRN_CNT_MASK                            0xFFFFFFFF
 127
 128 /* DMA_CH_0_STS4 */
 129 #define DMA_CH_0_STS4_WR_STS_TRN_CNT_SHIFT                           0
 130 #define DMA_CH_0_STS4_WR_STS_TRN_CNT_MASK                            0xFFFFFFFF
 131
 132 /* DMA_CH_0_SRC_ADDR_LO_STS */
 133 #define DMA_CH_0_SRC_ADDR_LO_STS_VAL_SHIFT                           0
 134 #define DMA_CH_0_SRC_ADDR_LO_STS_VAL_MASK                            0xFFFFFFFF
 135
 136 /* DMA_CH_0_SRC_ADDR_HI_STS */
 137 #define DMA_CH_0_SRC_ADDR_HI_STS_VAL_SHIFT                           0
 138 #define DMA_CH_0_SRC_ADDR_HI_STS_VAL_MASK                            0xFFFFFFFF
 139
 140 /* DMA_CH_0_SRC_TSIZE_STS */
 141 #define DMA_CH_0_SRC_TSIZE_STS_VAL_SHIFT                             0
 142 #define DMA_CH_0_SRC_TSIZE_STS_VAL_MASK                              0xFFFFFFFF
 143
 144 /* DMA_CH_0_DST_ADDR_LO_STS */
 145 #define DMA_CH_0_DST_ADDR_LO_STS_VAL_SHIFT                           0
 146 #define DMA_CH_0_DST_ADDR_LO_STS_VAL_MASK                            0xFFFFFFFF
 147
 148 /* DMA_CH_0_DST_ADDR_HI_STS */
 149 #define DMA_CH_0_DST_ADDR_HI_STS_VAL_SHIFT                           0
 150 #define DMA_CH_0_DST_ADDR_HI_STS_VAL_MASK                            0xFFFFFFFF
 151
 152 /* DMA_CH_0_DST_TSIZE_STS */
 153 #define DMA_CH_0_DST_TSIZE_STS_VAL_SHIFT                             0
 154 #define DMA_CH_0_DST_TSIZE_STS_VAL_MASK                              0xFFFFFFFF
 155
 156 /* DMA_CH_0_RD_RATE_LIM_EN */
 157 #define DMA_CH_0_RD_RATE_LIM_EN_VAL_SHIFT                            0
 158 #define DMA_CH_0_RD_RATE_LIM_EN_VAL_MASK                             0x1
 159
 160 /* DMA_CH_0_RD_RATE_LIM_RST_TOKEN */
 161 #define DMA_CH_0_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT                     0
 162 #define DMA_CH_0_RD_RATE_LIM_RST_TOKEN_VAL_MASK                      0xFFFF
 163
 164 /* DMA_CH_0_RD_RATE_LIM_SAT */
 165 #define DMA_CH_0_RD_RATE_LIM_SAT_VAL_SHIFT                           0
 166 #define DMA_CH_0_RD_RATE_LIM_SAT_VAL_MASK                            0xFFFF
 167
 168 /* DMA_CH_0_RD_RATE_LIM_TOUT */
 169 #define DMA_CH_0_RD_RATE_LIM_TOUT_VAL_SHIFT                          0
 170 #define DMA_CH_0_RD_RATE_LIM_TOUT_VAL_MASK                           0x7FFFFFFF
 171
 172 /* DMA_CH_0_WR_RATE_LIM_EN */
 173 #define DMA_CH_0_WR_RATE_LIM_EN_VAL_SHIFT                            0
 174 #define DMA_CH_0_WR_RATE_LIM_EN_VAL_MASK                             0x1
 175
 176 /* DMA_CH_0_WR_RATE_LIM_RST_TOKEN */
 177 #define DMA_CH_0_WR_RATE_LIM_RST_TOKEN_VAL_SHIFT                     0
 178 #define DMA_CH_0_WR_RATE_LIM_RST_TOKEN_VAL_MASK                      0xFFFF
 179
 180 /* DMA_CH_0_WR_RATE_LIM_SAT */
 181 #define DMA_CH_0_WR_RATE_LIM_SAT_VAL_SHIFT                           0
 182 #define DMA_CH_0_WR_RATE_LIM_SAT_VAL_MASK                            0xFFFF
 183
 184 /* DMA_CH_0_WR_RATE_LIM_TOUT */
 185 #define DMA_CH_0_WR_RATE_LIM_TOUT_VAL_SHIFT                          0
 186 #define DMA_CH_0_WR_RATE_LIM_TOUT_VAL_MASK                           0x7FFFFFFF
 187
 188 /* DMA_CH_0_CFG2 */
 189 #define DMA_CH_0_CFG2_FORCE_WORD_SHIFT                               0
 190 #define DMA_CH_0_CFG2_FORCE_WORD_MASK                                0x1
 191
 192 /* DMA_CH_0_TDMA_CTL */
 193 #define DMA_CH_0_TDMA_CTL_DTYPE_SHIFT                                0
 194 #define DMA_CH_0_TDMA_CTL_DTYPE_MASK                                 0x7
 195
 196 /* DMA_CH_0_TDMA_SRC_BASE_ADDR_LO */
 197 #define DMA_CH_0_TDMA_SRC_BASE_ADDR_LO_VAL_SHIFT                     0
 198 #define DMA_CH_0_TDMA_SRC_BASE_ADDR_LO_VAL_MASK                      0xFFFFFFFF
 199
 200 /* DMA_CH_0_TDMA_SRC_BASE_ADDR_HI */
 201 #define DMA_CH_0_TDMA_SRC_BASE_ADDR_HI_VAL_SHIFT                     0
 202 #define DMA_CH_0_TDMA_SRC_BASE_ADDR_HI_VAL_MASK                      0xFFFFFFFF
 203
 204 /* DMA_CH_0_TDMA_SRC_ROI_BASE_0 */
 205 #define DMA_CH_0_TDMA_SRC_ROI_BASE_0_VAL_SHIFT                       0
 206 #define DMA_CH_0_TDMA_SRC_ROI_BASE_0_VAL_MASK                        0xFFFFFFFF
 207
 208 /* DMA_CH_0_TDMA_SRC_ROI_SIZE_0 */
 209 #define DMA_CH_0_TDMA_SRC_ROI_SIZE_0_VAL_SHIFT                       0
 210 #define DMA_CH_0_TDMA_SRC_ROI_SIZE_0_VAL_MASK                        0xFFFFFFFF
 211
 212 /* DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_0 */
 213 #define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_0_VAL_SHIFT                 0
 214 #define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_0_VAL_MASK                  0xFFFFFFFF
 215
 216 /* DMA_CH_0_TDMA_SRC_START_OFFSET_0 */
 217 #define DMA_CH_0_TDMA_SRC_START_OFFSET_0_VAL_SHIFT                   0
 218 #define DMA_CH_0_TDMA_SRC_START_OFFSET_0_VAL_MASK                    0xFFFFFFFF
 219
 220 /* DMA_CH_0_TDMA_SRC_STRIDE_0 */
 221 #define DMA_CH_0_TDMA_SRC_STRIDE_0_VAL_SHIFT                         0
 222 #define DMA_CH_0_TDMA_SRC_STRIDE_0_VAL_MASK                          0xFFFFFFFF
 223
 224 /* DMA_CH_0_TDMA_SRC_ROI_BASE_1 */
 225 #define DMA_CH_0_TDMA_SRC_ROI_BASE_1_VAL_SHIFT                       0
 226 #define DMA_CH_0_TDMA_SRC_ROI_BASE_1_VAL_MASK                        0xFFFFFFFF
 227
 228 /* DMA_CH_0_TDMA_SRC_ROI_SIZE_1 */
 229 #define DMA_CH_0_TDMA_SRC_ROI_SIZE_1_VAL_SHIFT                       0
 230 #define DMA_CH_0_TDMA_SRC_ROI_SIZE_1_VAL_MASK                        0xFFFFFFFF
 231
 232 /* DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_1 */
 233 #define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_1_VAL_SHIFT                 0
 234 #define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_1_VAL_MASK                  0xFFFFFFFF
 235
 236 /* DMA_CH_0_TDMA_SRC_START_OFFSET_1 */
 237 #define DMA_CH_0_TDMA_SRC_START_OFFSET_1_VAL_SHIFT                   0
 238 #define DMA_CH_0_TDMA_SRC_START_OFFSET_1_VAL_MASK                    0xFFFFFFFF
 239
 240 /* DMA_CH_0_TDMA_SRC_STRIDE_1 */
 241 #define DMA_CH_0_TDMA_SRC_STRIDE_1_VAL_SHIFT                         0
 242 #define DMA_CH_0_TDMA_SRC_STRIDE_1_VAL_MASK                          0xFFFFFFFF
 243
 244 /* DMA_CH_0_TDMA_SRC_ROI_BASE_2 */
 245 #define DMA_CH_0_TDMA_SRC_ROI_BASE_2_VAL_SHIFT                       0
 246 #define DMA_CH_0_TDMA_SRC_ROI_BASE_2_VAL_MASK                        0xFFFFFFFF
 247
 248 /* DMA_CH_0_TDMA_SRC_ROI_SIZE_2 */
 249 #define DMA_CH_0_TDMA_SRC_ROI_SIZE_2_VAL_SHIFT                       0
 250 #define DMA_CH_0_TDMA_SRC_ROI_SIZE_2_VAL_MASK                        0xFFFFFFFF
 251
 252 /* DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_2 */
 253 #define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_2_VAL_SHIFT                 0
 254 #define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_2_VAL_MASK                  0xFFFFFFFF
 255
 256 /* DMA_CH_0_TDMA_SRC_START_OFFSET_2 */
 257 #define DMA_CH_0_TDMA_SRC_START_OFFSET_2_VAL_SHIFT                   0
 258 #define DMA_CH_0_TDMA_SRC_START_OFFSET_2_VAL_MASK                    0xFFFFFFFF
 259
 260 /* DMA_CH_0_TDMA_SRC_STRIDE_2 */
 261 #define DMA_CH_0_TDMA_SRC_STRIDE_2_VAL_SHIFT                         0
 262 #define DMA_CH_0_TDMA_SRC_STRIDE_2_VAL_MASK                          0xFFFFFFFF
 263
 264 /* DMA_CH_0_TDMA_SRC_ROI_BASE_3 */
 265 #define DMA_CH_0_TDMA_SRC_ROI_BASE_3_VAL_SHIFT                       0
 266 #define DMA_CH_0_TDMA_SRC_ROI_BASE_3_VAL_MASK                        0xFFFFFFFF
 267
 268 /* DMA_CH_0_TDMA_SRC_ROI_SIZE_3 */
 269 #define DMA_CH_0_TDMA_SRC_ROI_SIZE_3_VAL_SHIFT                       0
 270 #define DMA_CH_0_TDMA_SRC_ROI_SIZE_3_VAL_MASK                        0xFFFFFFFF
 271
 272 /* DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_3 */
 273 #define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_3_VAL_SHIFT                 0
 274 #define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_3_VAL_MASK                  0xFFFFFFFF
 275
 276 /* DMA_CH_0_TDMA_SRC_START_OFFSET_3 */
 277 #define DMA_CH_0_TDMA_SRC_START_OFFSET_3_VAL_SHIFT                   0
 278 #define DMA_CH_0_TDMA_SRC_START_OFFSET_3_VAL_MASK                    0xFFFFFFFF
 279
 280 /* DMA_CH_0_TDMA_SRC_STRIDE_3 */
 281 #define DMA_CH_0_TDMA_SRC_STRIDE_3_VAL_SHIFT                         0
 282 #define DMA_CH_0_TDMA_SRC_STRIDE_3_VAL_MASK                          0xFFFFFFFF
 283
 284 /* DMA_CH_0_TDMA_SRC_ROI_BASE_4 */
 285 #define DMA_CH_0_TDMA_SRC_ROI_BASE_4_VAL_SHIFT                       0
 286 #define DMA_CH_0_TDMA_SRC_ROI_BASE_4_VAL_MASK                        0xFFFFFFFF
 287
 288 /* DMA_CH_0_TDMA_SRC_ROI_SIZE_4 */
 289 #define DMA_CH_0_TDMA_SRC_ROI_SIZE_4_VAL_SHIFT                       0
 290 #define DMA_CH_0_TDMA_SRC_ROI_SIZE_4_VAL_MASK                        0xFFFFFFFF
 291
 292 /* DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_4 */
 293 #define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_4_VAL_SHIFT                 0
 294 #define DMA_CH_0_TDMA_SRC_VALID_ELEMENTS_4_VAL_MASK                  0xFFFFFFFF
 295
 296 /* DMA_CH_0_TDMA_SRC_START_OFFSET_4 */
 297 #define DMA_CH_0_TDMA_SRC_START_OFFSET_4_VAL_SHIFT                   0
 298 #define DMA_CH_0_TDMA_SRC_START_OFFSET_4_VAL_MASK                    0xFFFFFFFF
 299
 300 /* DMA_CH_0_TDMA_SRC_STRIDE_4 */
 301 #define DMA_CH_0_TDMA_SRC_STRIDE_4_VAL_SHIFT                         0
 302 #define DMA_CH_0_TDMA_SRC_STRIDE_4_VAL_MASK                          0xFFFFFFFF
 303
 304 /* DMA_CH_0_TDMA_DST_BASE_ADDR_LO */
 305 #define DMA_CH_0_TDMA_DST_BASE_ADDR_LO_VAL_SHIFT                     0
 306 #define DMA_CH_0_TDMA_DST_BASE_ADDR_LO_VAL_MASK                      0xFFFFFFFF
 307
 308 /* DMA_CH_0_TDMA_DST_BASE_ADDR_HI */
 309 #define DMA_CH_0_TDMA_DST_BASE_ADDR_HI_VAL_SHIFT                     0
 310 #define DMA_CH_0_TDMA_DST_BASE_ADDR_HI_VAL_MASK                      0xFFFFFFFF
 311
 312 /* DMA_CH_0_TDMA_DST_ROI_BASE_0 */
 313 #define DMA_CH_0_TDMA_DST_ROI_BASE_0_VAL_SHIFT                       0
 314 #define DMA_CH_0_TDMA_DST_ROI_BASE_0_VAL_MASK                        0xFFFFFFFF
 315
 316 /* DMA_CH_0_TDMA_DST_ROI_SIZE_0 */
 317 #define DMA_CH_0_TDMA_DST_ROI_SIZE_0_VAL_SHIFT                       0
 318 #define DMA_CH_0_TDMA_DST_ROI_SIZE_0_VAL_MASK                        0xFFFFFFFF
 319
 320 /* DMA_CH_0_TDMA_DST_VALID_ELEMENTS_0 */
 321 #define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_0_VAL_SHIFT                 0
 322 #define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_0_VAL_MASK                  0xFFFFFFFF
 323
 324 /* DMA_CH_0_TDMA_DST_START_OFFSET_0 */
 325 #define DMA_CH_0_TDMA_DST_START_OFFSET_0_VAL_SHIFT                   0
 326 #define DMA_CH_0_TDMA_DST_START_OFFSET_0_VAL_MASK                    0xFFFFFFFF
 327
 328 /* DMA_CH_0_TDMA_DST_STRIDE_0 */
 329 #define DMA_CH_0_TDMA_DST_STRIDE_0_VAL_SHIFT                         0
 330 #define DMA_CH_0_TDMA_DST_STRIDE_0_VAL_MASK                          0xFFFFFFFF
 331
 332 /* DMA_CH_0_TDMA_DST_ROI_BASE_1 */
 333 #define DMA_CH_0_TDMA_DST_ROI_BASE_1_VAL_SHIFT                       0
 334 #define DMA_CH_0_TDMA_DST_ROI_BASE_1_VAL_MASK                        0xFFFFFFFF
 335
 336 /* DMA_CH_0_TDMA_DST_ROI_SIZE_1 */
 337 #define DMA_CH_0_TDMA_DST_ROI_SIZE_1_VAL_SHIFT                       0
 338 #define DMA_CH_0_TDMA_DST_ROI_SIZE_1_VAL_MASK                        0xFFFFFFFF
 339
 340 /* DMA_CH_0_TDMA_DST_VALID_ELEMENTS_1 */
 341 #define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_1_VAL_SHIFT                 0
 342 #define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_1_VAL_MASK                  0xFFFFFFFF
 343
 344 /* DMA_CH_0_TDMA_DST_START_OFFSET_1 */
 345 #define DMA_CH_0_TDMA_DST_START_OFFSET_1_VAL_SHIFT                   0
 346 #define DMA_CH_0_TDMA_DST_START_OFFSET_1_VAL_MASK                    0xFFFFFFFF
 347
 348 /* DMA_CH_0_TDMA_DST_STRIDE_1 */
 349 #define DMA_CH_0_TDMA_DST_STRIDE_1_VAL_SHIFT                         0
 350 #define DMA_CH_0_TDMA_DST_STRIDE_1_VAL_MASK                          0xFFFFFFFF
 351
 352 /* DMA_CH_0_TDMA_DST_ROI_BASE_2 */
 353 #define DMA_CH_0_TDMA_DST_ROI_BASE_2_VAL_SHIFT                       0
 354 #define DMA_CH_0_TDMA_DST_ROI_BASE_2_VAL_MASK                        0xFFFFFFFF
 355
 356 /* DMA_CH_0_TDMA_DST_ROI_SIZE_2 */
 357 #define DMA_CH_0_TDMA_DST_ROI_SIZE_2_VAL_SHIFT                       0
 358 #define DMA_CH_0_TDMA_DST_ROI_SIZE_2_VAL_MASK                        0xFFFFFFFF
 359
 360 /* DMA_CH_0_TDMA_DST_VALID_ELEMENTS_2 */
 361 #define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_2_VAL_SHIFT                 0
 362 #define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_2_VAL_MASK                  0xFFFFFFFF
 363
 364 /* DMA_CH_0_TDMA_DST_START_OFFSET_2 */
 365 #define DMA_CH_0_TDMA_DST_START_OFFSET_2_VAL_SHIFT                   0
 366 #define DMA_CH_0_TDMA_DST_START_OFFSET_2_VAL_MASK                    0xFFFFFFFF
 367
 368 /* DMA_CH_0_TDMA_DST_STRIDE_2 */
 369 #define DMA_CH_0_TDMA_DST_STRIDE_2_VAL_SHIFT                         0
 370 #define DMA_CH_0_TDMA_DST_STRIDE_2_VAL_MASK                          0xFFFFFFFF
 371
 372 /* DMA_CH_0_TDMA_DST_ROI_BASE_3 */
 373 #define DMA_CH_0_TDMA_DST_ROI_BASE_3_VAL_SHIFT                       0
 374 #define DMA_CH_0_TDMA_DST_ROI_BASE_3_VAL_MASK                        0xFFFFFFFF
 375
 376 /* DMA_CH_0_TDMA_DST_ROI_SIZE_3 */
 377 #define DMA_CH_0_TDMA_DST_ROI_SIZE_3_VAL_SHIFT                       0
 378 #define DMA_CH_0_TDMA_DST_ROI_SIZE_3_VAL_MASK                        0xFFFFFFFF
 379
 380 /* DMA_CH_0_TDMA_DST_VALID_ELEMENTS_3 */
 381 #define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_3_VAL_SHIFT                 0
 382 #define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_3_VAL_MASK                  0xFFFFFFFF
 383
 384 /* DMA_CH_0_TDMA_DST_START_OFFSET_3 */
 385 #define DMA_CH_0_TDMA_DST_START_OFFSET_3_VAL_SHIFT                   0
 386 #define DMA_CH_0_TDMA_DST_START_OFFSET_3_VAL_MASK                    0xFFFFFFFF
 387
 388 /* DMA_CH_0_TDMA_DST_STRIDE_3 */
 389 #define DMA_CH_0_TDMA_DST_STRIDE_3_VAL_SHIFT                         0
 390 #define DMA_CH_0_TDMA_DST_STRIDE_3_VAL_MASK                          0xFFFFFFFF
 391
 392 /* DMA_CH_0_TDMA_DST_ROI_BASE_4 */
 393 #define DMA_CH_0_TDMA_DST_ROI_BASE_4_VAL_SHIFT                       0
 394 #define DMA_CH_0_TDMA_DST_ROI_BASE_4_VAL_MASK                        0xFFFFFFFF
 395
 396 /* DMA_CH_0_TDMA_DST_ROI_SIZE_4 */
 397 #define DMA_CH_0_TDMA_DST_ROI_SIZE_4_VAL_SHIFT                       0
 398 #define DMA_CH_0_TDMA_DST_ROI_SIZE_4_VAL_MASK                        0xFFFFFFFF
 399
 400 /* DMA_CH_0_TDMA_DST_VALID_ELEMENTS_4 */
 401 #define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_4_VAL_SHIFT                 0
 402 #define DMA_CH_0_TDMA_DST_VALID_ELEMENTS_4_VAL_MASK                  0xFFFFFFFF
 403
 404 /* DMA_CH_0_TDMA_DST_START_OFFSET_4 */
 405 #define DMA_CH_0_TDMA_DST_START_OFFSET_4_VAL_SHIFT                   0
 406 #define DMA_CH_0_TDMA_DST_START_OFFSET_4_VAL_MASK                    0xFFFFFFFF
 407
 408 /* DMA_CH_0_TDMA_DST_STRIDE_4 */
 409 #define DMA_CH_0_TDMA_DST_STRIDE_4_VAL_SHIFT                         0
 410 #define DMA_CH_0_TDMA_DST_STRIDE_4_VAL_MASK                          0xFFFFFFFF
 411
 412 /* DMA_CH_0_MEM_INIT_BUSY */
 413 #define DMA_CH_0_MEM_INIT_BUSY_SBC_DATA_SHIFT                        0
 414 #define DMA_CH_0_MEM_INIT_BUSY_SBC_DATA_MASK                         0xFF
 415 #define DMA_CH_0_MEM_INIT_BUSY_SBC_MD_SHIFT                          8
 416 #define DMA_CH_0_MEM_INIT_BUSY_SBC_MD_MASK                           0x100
 417
 418 #endif /* ASIC_REG_DMA_CH_0_MASKS_H_ */