drivers/misc/cardreader/rts5260.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Driver for Realtek PCI-Express card reader
   3  *
   4  * Copyright(c) 2016-2017 Realtek Semiconductor Corp. All rights reserved.
   5  *
   6  * Author:
   7  *   Steven FENG <steven_feng@realsil.com.cn>
   8  *   Rui FENG <rui_feng@realsil.com.cn>
   9  *   Wei WANG <wei_wang@realsil.com.cn>
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/delay.h>
  14 #include <linux/rtsx_pci.h>
  15
  16 #include "rts5260.h"
  17 #include "rtsx_pcr.h"
  18
  19 static u8 rts5260_get_ic_version(struct rtsx_pcr *pcr)
  20 {
  21         u8 val;
  22
  23         rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  24         return val & IC_VERSION_MASK;
  25 }
  26
  27 static void rts5260_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  28 {
  29         u8 driving_3v3[6][3] = {
  30                 {0x94, 0x94, 0x94},
  31                 {0x11, 0x11, 0x18},
  32                 {0x55, 0x55, 0x5C},
  33                 {0x94, 0x94, 0x94},
  34                 {0x94, 0x94, 0x94},
  35                 {0xFF, 0xFF, 0xFF},
  36         };
  37         u8 driving_1v8[6][3] = {
  38                 {0x9A, 0x89, 0x89},
  39                 {0xC4, 0xC4, 0xC4},
  40                 {0x3C, 0x3C, 0x3C},
  41                 {0x9B, 0x99, 0x99},
  42                 {0x9A, 0x89, 0x89},
  43                 {0xFE, 0xFE, 0xFE},
  44         };
  45         u8 (*driving)[3], drive_sel;
  46
  47         if (voltage == OUTPUT_3V3) {
  48                 driving = driving_3v3;
  49                 drive_sel = pcr->sd30_drive_sel_3v3;
  50         } else {
  51                 driving = driving_1v8;
  52                 drive_sel = pcr->sd30_drive_sel_1v8;
  53         }
  54
  55         rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
  56                          0xFF, driving[drive_sel][0]);
  57
  58         rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
  59                          0xFF, driving[drive_sel][1]);
  60
  61         rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
  62                          0xFF, driving[drive_sel][2]);
  63 }
  64
  65 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
  66 {
  67         u32 reg;
  68
  69         rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
  70         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  71
  72         if (!rtsx_vendor_setting_valid(reg)) {
  73                 pcr_dbg(pcr, "skip fetch vendor setting\n");
  74                 return;
  75         }
  76
  77         pcr->aspm_en = rtsx_reg_to_aspm(reg);
  78         pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  79         pcr->card_drive_sel &= 0x3F;
  80         pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  81
  82         rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
  83         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  84         pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  85         if (rtsx_reg_check_reverse_socket(reg))
  86                 pcr->flags |= PCR_REVERSE_SOCKET;
  87 }
  88
  89 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
  90 {
  91         /* Set relink_time to 0 */
  92         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
  93         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
  94         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
  95                                 RELINK_TIME_MASK, 0);
  96
  97         if (pm_state == HOST_ENTER_S3)
  98                 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
  99                                         D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
 100
 101         rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
 102 }
 103
 104 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
 105 {
 106         return rtsx_pci_write_register(pcr, OLT_LED_CTL,
 107                 LED_SHINE_MASK, LED_SHINE_EN);
 108 }
 109
 110 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
 111 {
 112         return rtsx_pci_write_register(pcr, OLT_LED_CTL,
 113                 LED_SHINE_MASK, LED_SHINE_DISABLE);
 114 }
 115
 116 static int rts5260_turn_on_led(struct rtsx_pcr *pcr)
 117 {
 118         return rtsx_pci_write_register(pcr, RTS5260_REG_GPIO_CTL0,
 119                 RTS5260_REG_GPIO_MASK, RTS5260_REG_GPIO_ON);
 120 }
 121
 122 static int rts5260_turn_off_led(struct rtsx_pcr *pcr)
 123 {
 124         return rtsx_pci_write_register(pcr, RTS5260_REG_GPIO_CTL0,
 125                 RTS5260_REG_GPIO_MASK, RTS5260_REG_GPIO_OFF);
 126 }
 127
 128 /* SD Pull Control Enable:
 129  *     SD_DAT[3:0] ==> pull up
 130  *     SD_CD       ==> pull up
 131  *     SD_WP       ==> pull up
 132  *     SD_CMD      ==> pull up
 133  *     SD_CLK      ==> pull down
 134  */
 135 static const u32 rts5260_sd_pull_ctl_enable_tbl[] = {
 136         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 137         RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
 138         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
 139         RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
 140         0,
 141 };
 142
 143 /* SD Pull Control Disable:
 144  *     SD_DAT[3:0] ==> pull down
 145  *     SD_CD       ==> pull up
 146  *     SD_WP       ==> pull down
 147  *     SD_CMD      ==> pull down
 148  *     SD_CLK      ==> pull down
 149  */
 150 static const u32 rts5260_sd_pull_ctl_disable_tbl[] = {
 151         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 152         RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
 153         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
 154         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 155         0,
 156 };
 157
 158 /* MS Pull Control Enable:
 159  *     MS CD       ==> pull up
 160  *     others      ==> pull down
 161  */
 162 static const u32 rts5260_ms_pull_ctl_enable_tbl[] = {
 163         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 164         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 165         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 166         0,
 167 };
 168
 169 /* MS Pull Control Disable:
 170  *     MS CD       ==> pull up
 171  *     others      ==> pull down
 172  */
 173 static const u32 rts5260_ms_pull_ctl_disable_tbl[] = {
 174         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 175         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 176         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 177         0,
 178 };
 179
 180 static int sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
 181 {
 182         rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
 183                 | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
 184         rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
 185         rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
 186                         CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 187         rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
 188
 189         return 0;
 190 }
 191
 192 static int rts5260_card_power_on(struct rtsx_pcr *pcr, int card)
 193 {
 194         int err = 0;
 195         struct rtsx_cr_option *option = &pcr->option;
 196
 197         if (option->ocp_en)
 198                 rtsx_pci_enable_ocp(pcr);
 199
 200
 201         rtsx_pci_write_register(pcr, LDO_CONFIG2, DV331812_VDD1, DV331812_VDD1);
 202         rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
 203                          RTS5260_DVCC_TUNE_MASK, RTS5260_DVCC_33);
 204
 205         rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_POW_SDVDD1_MASK,
 206                         LDO_POW_SDVDD1_ON);
 207
 208         rtsx_pci_write_register(pcr, LDO_CONFIG2,
 209                          DV331812_POWERON, DV331812_POWERON);
 210         msleep(20);
 211
 212         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
 213             pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
 214                 sd_set_sample_push_timing_sd30(pcr);
 215
 216         /* Initialize SD_CFG1 register */
 217         rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
 218                                 SD_CLK_DIVIDE_128 | SD_20_MODE);
 219
 220         rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
 221                                 0xFF, SD20_RX_POS_EDGE);
 222         rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
 223         rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
 224                                 SD_STOP | SD_CLR_ERR);
 225
 226         /* Reset SD_CFG3 register */
 227         rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
 228         rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
 229                         SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
 230                         SD30_CLK_STOP_CFG0, 0);
 231
 232         rtsx_pci_write_register(pcr, REG_PRE_RW_MODE, EN_INFINITE_MODE, 0);
 233
 234         return err;
 235 }
 236
 237 static int rts5260_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 238 {
 239         switch (voltage) {
 240         case OUTPUT_3V3:
 241                 rtsx_pci_write_register(pcr, LDO_CONFIG2,
 242                                         DV331812_VDD1, DV331812_VDD1);
 243                 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
 244                                         DV331812_MASK, DV331812_33);
 245                 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
 246                 break;
 247         case OUTPUT_1V8:
 248                 rtsx_pci_write_register(pcr, LDO_CONFIG2,
 249                                         DV331812_VDD1, DV331812_VDD1);
 250                 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
 251                                         DV331812_MASK, DV331812_17);
 252                 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
 253                                         SD_IO_USING_1V8);
 254                 break;
 255         default:
 256                 return -EINVAL;
 257         }
 258
 259         /* set pad drive */
 260         rts5260_fill_driving(pcr, voltage);
 261
 262         return 0;
 263 }
 264
 265 static void rts5260_stop_cmd(struct rtsx_pcr *pcr)
 266 {
 267         rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
 268         rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
 269         rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
 270                                 RTS5260_DMA_RST | RTS5260_ADMA3_RST,
 271                                 RTS5260_DMA_RST | RTS5260_ADMA3_RST);
 272         rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
 273 }
 274
 275 static void rts5260_card_before_power_off(struct rtsx_pcr *pcr)
 276 {
 277         rts5260_stop_cmd(pcr);
 278         rts5260_switch_output_voltage(pcr, OUTPUT_3V3);
 279
 280 }
 281
 282 static int rts5260_card_power_off(struct rtsx_pcr *pcr, int card)
 283 {
 284         int err = 0;
 285
 286         rts5260_card_before_power_off(pcr);
 287         err = rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
 288                          LDO_POW_SDVDD1_MASK, LDO_POW_SDVDD1_OFF);
 289         err = rtsx_pci_write_register(pcr, LDO_CONFIG2,
 290                          DV331812_POWERON, DV331812_POWEROFF);
 291         if (pcr->option.ocp_en)
 292                 rtsx_pci_disable_ocp(pcr);
 293
 294         return err;
 295 }
 296
 297 static void rts5260_init_ocp(struct rtsx_pcr *pcr)
 298 {
 299         struct rtsx_cr_option *option = &pcr->option;
 300
 301         if (option->ocp_en) {
 302                 u8 mask, val;
 303
 304
 305                 rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
 306                                 RTS5260_DVCC_OCP_THD_MASK,
 307                                 option->sd_800mA_ocp_thd);
 308
 309                 rtsx_pci_write_register(pcr, RTS5260_DV331812_CFG,
 310                                 RTS5260_DV331812_OCP_THD_MASK,
 311                                 RTS5260_DV331812_OCP_THD_270);
 312
 313                 mask = SD_OCP_GLITCH_MASK;
 314                 val = pcr->hw_param.ocp_glitch;
 315                 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
 316                 rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
 317                                         RTS5260_DVCC_OCP_EN |
 318                                         RTS5260_DVCC_OCP_CL_EN,
 319                                         RTS5260_DVCC_OCP_EN |
 320                                         RTS5260_DVCC_OCP_CL_EN);
 321
 322                 rtsx_pci_enable_ocp(pcr);
 323         } else {
 324                 rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
 325                                         RTS5260_DVCC_OCP_EN |
 326                                         RTS5260_DVCC_OCP_CL_EN, 0);
 327         }
 328 }
 329
 330 static void rts5260_enable_ocp(struct rtsx_pcr *pcr)
 331 {
 332         u8 val = 0;
 333
 334         val = SD_OCP_INT_EN | SD_DETECT_EN;
 335         rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
 336
 337 }
 338
 339 static void rts5260_disable_ocp(struct rtsx_pcr *pcr)
 340 {
 341         u8 mask = 0;
 342
 343         mask = SD_OCP_INT_EN | SD_DETECT_EN;
 344         rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
 345
 346 }
 347
 348
 349 static int rts5260_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
 350 {
 351         return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
 352 }
 353
 354 static int rts5260_get_ocpstat2(struct rtsx_pcr *pcr, u8 *val)
 355 {
 356         return rtsx_pci_read_register(pcr, REG_DV3318_OCPSTAT, val);
 357 }
 358
 359 static void rts5260_clear_ocpstat(struct rtsx_pcr *pcr)
 360 {
 361         u8 mask = 0;
 362         u8 val = 0;
 363
 364         mask = SD_OCP_INT_CLR | SD_OC_CLR;
 365         val = SD_OCP_INT_CLR | SD_OC_CLR;
 366
 367         rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
 368         rtsx_pci_write_register(pcr, REG_DV3318_OCPCTL,
 369                                 DV3318_OCP_INT_CLR | DV3318_OCP_CLR,
 370                                 DV3318_OCP_INT_CLR | DV3318_OCP_CLR);
 371         udelay(10);
 372         rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
 373         rtsx_pci_write_register(pcr, REG_DV3318_OCPCTL,
 374                                 DV3318_OCP_INT_CLR | DV3318_OCP_CLR, 0);
 375 }
 376
 377 static void rts5260_process_ocp(struct rtsx_pcr *pcr)
 378 {
 379         if (!pcr->option.ocp_en)
 380                 return;
 381
 382         rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
 383         rts5260_get_ocpstat2(pcr, &pcr->ocp_stat2);
 384
 385         if ((pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) ||
 386                 (pcr->ocp_stat2 & (DV3318_OCP_NOW | DV3318_OCP_EVER))) {
 387                 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
 388                 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
 389                 rtsx_pci_clear_ocpstat(pcr);
 390                 pcr->ocp_stat = 0;
 391                 pcr->ocp_stat2 = 0;
 392         }
 393
 394 }
 395
 396 static int rts5260_init_hw(struct rtsx_pcr *pcr)
 397 {
 398         int err;
 399
 400         rtsx_pci_init_cmd(pcr);
 401
 402         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG1,
 403                          AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
 404         /* Rest L1SUB Config */
 405         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
 406         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CLK_FORCE_CTL,
 407                          CLK_PM_EN, CLK_PM_EN);
 408         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWD_SUSPEND_EN, 0xFF, 0xFF);
 409         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 410                          PWR_GATE_EN, PWR_GATE_EN);
 411         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, REG_VREF,
 412                          PWD_SUSPND_EN, PWD_SUSPND_EN);
 413         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RBCTL,
 414                          U_AUTO_DMA_EN_MASK, U_AUTO_DMA_DISABLE);
 415
 416         if (pcr->flags & PCR_REVERSE_SOCKET)
 417                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
 418         else
 419                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
 420
 421         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG,
 422                          OBFF_EN_MASK, OBFF_DISABLE);
 423
 424         err = rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
 425         if (err < 0)
 426                 return err;
 427
 428         rtsx_pci_init_ocp(pcr);
 429
 430         return 0;
 431 }
 432
 433 static void rts5260_pwr_saving_setting(struct rtsx_pcr *pcr)
 434 {
 435         int lss_l1_1, lss_l1_2;
 436
 437         lss_l1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN)
 438                         | rtsx_check_dev_flag(pcr, PM_L1_1_EN);
 439         lss_l1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN)
 440                         | rtsx_check_dev_flag(pcr, PM_L1_2_EN);
 441
 442         rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
 443         if (lss_l1_2) {
 444                 pcr_dbg(pcr, "Set parameters for L1.2.");
 445                 rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
 446                                         0xFF, PCIE_L1_2_EN);
 447                 rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
 448                                         RTS5260_DVCC_OCP_EN |
 449                                         RTS5260_DVCC_OCP_CL_EN,
 450                                         RTS5260_DVCC_OCP_EN |
 451                                         RTS5260_DVCC_OCP_CL_EN);
 452
 453                 rtsx_pci_write_register(pcr, PWR_FE_CTL,
 454                                         0xFF, PCIE_L1_2_PD_FE_EN);
 455         } else if (lss_l1_1) {
 456                 pcr_dbg(pcr, "Set parameters for L1.1.");
 457                 rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
 458                                         0xFF, PCIE_L1_1_EN);
 459                 rtsx_pci_write_register(pcr, PWR_FE_CTL,
 460                                         0xFF, PCIE_L1_1_PD_FE_EN);
 461         } else {
 462                 pcr_dbg(pcr, "Set parameters for L1.");
 463                 rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
 464                                         0xFF, PCIE_L1_0_EN);
 465                 rtsx_pci_write_register(pcr, PWR_FE_CTL,
 466                                         0xFF, PCIE_L1_0_PD_FE_EN);
 467         }
 468
 469         rtsx_pci_write_register(pcr, CFG_L1_0_PCIE_DPHY_RET_VALUE,
 470                                 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
 471         rtsx_pci_write_register(pcr, CFG_L1_0_PCIE_MAC_RET_VALUE,
 472                                 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
 473         rtsx_pci_write_register(pcr, CFG_L1_0_CRC_SD30_RET_VALUE,
 474                                 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
 475         rtsx_pci_write_register(pcr, CFG_L1_0_CRC_SD40_RET_VALUE,
 476                                 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
 477         rtsx_pci_write_register(pcr, CFG_L1_0_SYS_RET_VALUE,
 478                                 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
 479         /*Option cut APHY*/
 480         rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_0,
 481                                 0xFF, CFG_PCIE_APHY_OFF_0_DEFAULT);
 482         rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_1,
 483                                 0xFF, CFG_PCIE_APHY_OFF_1_DEFAULT);
 484         rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_2,
 485                                 0xFF, CFG_PCIE_APHY_OFF_2_DEFAULT);
 486         rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_3,
 487                                 0xFF, CFG_PCIE_APHY_OFF_3_DEFAULT);
 488         /*CDR DEC*/
 489         rtsx_pci_write_register(pcr, PWC_CDR, 0xFF, PWC_CDR_DEFAULT);
 490         /*PWMPFM*/
 491         rtsx_pci_write_register(pcr, CFG_LP_FPWM_VALUE,
 492                                 0xFF, CFG_LP_FPWM_VALUE_DEFAULT);
 493         /*No Power Saving WA*/
 494         rtsx_pci_write_register(pcr, CFG_L1_0_CRC_MISC_RET_VALUE,
 495                                 0xFF, CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT);
 496 }
 497
 498 static void rts5260_init_from_cfg(struct rtsx_pcr *pcr)
 499 {
 500         struct rtsx_cr_option *option = &pcr->option;
 501         u32 lval;
 502
 503         rtsx_pci_read_config_dword(pcr, PCR_ASPM_SETTING_5260, &lval);
 504
 505         if (lval & ASPM_L1_1_EN_MASK)
 506                 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
 507
 508         if (lval & ASPM_L1_2_EN_MASK)
 509                 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
 510
 511         if (lval & PM_L1_1_EN_MASK)
 512                 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
 513
 514         if (lval & PM_L1_2_EN_MASK)
 515                 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
 516
 517         rts5260_pwr_saving_setting(pcr);
 518
 519         if (option->ltr_en) {
 520                 u16 val;
 521
 522                 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
 523                 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
 524                         option->ltr_enabled = true;
 525                         option->ltr_active = true;
 526                         rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
 527                 } else {
 528                         option->ltr_enabled = false;
 529                 }
 530         }
 531
 532         if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
 533                                 | PM_L1_1_EN | PM_L1_2_EN))
 534                 option->force_clkreq_0 = false;
 535         else
 536                 option->force_clkreq_0 = true;
 537 }
 538
 539 static int rts5260_extra_init_hw(struct rtsx_pcr *pcr)
 540 {
 541         struct rtsx_cr_option *option = &pcr->option;
 542
 543         /* Set mcu_cnt to 7 to ensure data can be sampled properly */
 544         rtsx_pci_write_register(pcr, 0xFC03, 0x7F, 0x07);
 545         rtsx_pci_write_register(pcr, SSC_DIV_N_0, 0xFF, 0x5D);
 546
 547         rts5260_init_from_cfg(pcr);
 548
 549         /* force no MDIO*/
 550         rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4,
 551                                 0xFF, RTS5260_MIMO_DISABLE);
 552         /*Modify SDVCC Tune Default Parameters!*/
 553         rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
 554                                 RTS5260_DVCC_TUNE_MASK, RTS5260_DVCC_33);
 555
 556         rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
 557
 558         rts5260_init_hw(pcr);
 559
 560         /*
 561          * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
 562          * to drive low, and we forcibly request clock.
 563          */
 564         if (option->force_clkreq_0)
 565                 rtsx_pci_write_register(pcr, PETXCFG,
 566                                  FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
 567         else
 568                 rtsx_pci_write_register(pcr, PETXCFG,
 569                                  FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
 570
 571         return 0;
 572 }
 573
 574 static void rts5260_set_aspm(struct rtsx_pcr *pcr, bool enable)
 575 {
 576         struct rtsx_cr_option *option = &pcr->option;
 577         u8 val = 0;
 578
 579         if (pcr->aspm_enabled == enable)
 580                 return;
 581
 582         if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
 583                 if (enable)
 584                         val = pcr->aspm_en;
 585                 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
 586                                          ASPM_MASK_NEG, val);
 587         } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
 588                 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0;
 589
 590                 if (!enable)
 591                         val = FORCE_ASPM_CTL0;
 592                 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
 593         }
 594
 595         pcr->aspm_enabled = enable;
 596 }
 597
 598 static void rts5260_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
 599 {
 600         struct rtsx_cr_option *option = &pcr->option;
 601         u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
 602         int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
 603         int aspm_L1_1, aspm_L1_2;
 604         u8 val = 0;
 605
 606         aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
 607         aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
 608
 609         if (active) {
 610                 /* run, latency: 60us */
 611                 if (aspm_L1_1)
 612                         val = option->ltr_l1off_snooze_sspwrgate;
 613         } else {
 614                 /* l1off, latency: 300us */
 615                 if (aspm_L1_2)
 616                         val = option->ltr_l1off_sspwrgate;
 617         }
 618
 619         if (aspm_L1_1 || aspm_L1_2) {
 620                 if (rtsx_check_dev_flag(pcr,
 621                                         LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
 622                         if (card_exist)
 623                                 val &= ~L1OFF_MBIAS2_EN_5250;
 624                         else
 625                                 val |= L1OFF_MBIAS2_EN_5250;
 626                 }
 627         }
 628         rtsx_set_l1off_sub(pcr, val);
 629 }
 630
 631 static const struct pcr_ops rts5260_pcr_ops = {
 632         .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 633         .turn_on_led = rts5260_turn_on_led,
 634         .turn_off_led = rts5260_turn_off_led,
 635         .extra_init_hw = rts5260_extra_init_hw,
 636         .enable_auto_blink = rtsx_base_enable_auto_blink,
 637         .disable_auto_blink = rtsx_base_disable_auto_blink,
 638         .card_power_on = rts5260_card_power_on,
 639         .card_power_off = rts5260_card_power_off,
 640         .switch_output_voltage = rts5260_switch_output_voltage,
 641         .force_power_down = rtsx_base_force_power_down,
 642         .stop_cmd = rts5260_stop_cmd,
 643         .set_aspm = rts5260_set_aspm,
 644         .set_l1off_cfg_sub_d0 = rts5260_set_l1off_cfg_sub_d0,
 645         .enable_ocp = rts5260_enable_ocp,
 646         .disable_ocp = rts5260_disable_ocp,
 647         .init_ocp = rts5260_init_ocp,
 648         .process_ocp = rts5260_process_ocp,
 649         .get_ocpstat = rts5260_get_ocpstat,
 650         .clear_ocpstat = rts5260_clear_ocpstat,
 651 };
 652
 653 void rts5260_init_params(struct rtsx_pcr *pcr)
 654 {
 655         struct rtsx_cr_option *option = &pcr->option;
 656         struct rtsx_hw_param *hw_param = &pcr->hw_param;
 657
 658         pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
 659         pcr->num_slots = 2;
 660
 661         pcr->flags = 0;
 662         pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
 663         pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
 664         pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
 665         pcr->aspm_en = ASPM_L1_EN;
 666         pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
 667         pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
 668
 669         pcr->ic_version = rts5260_get_ic_version(pcr);
 670         pcr->sd_pull_ctl_enable_tbl = rts5260_sd_pull_ctl_enable_tbl;
 671         pcr->sd_pull_ctl_disable_tbl = rts5260_sd_pull_ctl_disable_tbl;
 672         pcr->ms_pull_ctl_enable_tbl = rts5260_ms_pull_ctl_enable_tbl;
 673         pcr->ms_pull_ctl_disable_tbl = rts5260_ms_pull_ctl_disable_tbl;
 674
 675         pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
 676
 677         pcr->ops = &rts5260_pcr_ops;
 678
 679         option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
 680                                 | LTR_L1SS_PWR_GATE_EN);
 681         option->ltr_en = true;
 682
 683         /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
 684         option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
 685         option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
 686         option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
 687         option->dev_aspm_mode = DEV_ASPM_DYNAMIC;
 688         option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
 689         option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
 690         option->ltr_l1off_snooze_sspwrgate =
 691                 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
 692
 693         option->ocp_en = 1;
 694         if (option->ocp_en)
 695                 hw_param->interrupt_en |= SD_OC_INT_EN;
 696         hw_param->ocp_glitch =  SD_OCP_GLITCH_100U | SDVIO_OCP_GLITCH_800U;
 697         option->sd_400mA_ocp_thd = RTS5260_DVCC_OCP_THD_550;
 698         option->sd_800mA_ocp_thd = RTS5260_DVCC_OCP_THD_970;
 699 }