drivers/memory/tegra/tegra124.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/of.h>
   7 #include <linux/mm.h>
   8
   9 #include <dt-bindings/memory/tegra124-mc.h>
  10
  11 #include "mc.h"
  12
  13 #define MC_EMEM_ARB_CFG                         0x90
  14 #define MC_EMEM_ARB_OUTSTANDING_REQ             0x94
  15 #define MC_EMEM_ARB_TIMING_RCD                  0x98
  16 #define MC_EMEM_ARB_TIMING_RP                   0x9c
  17 #define MC_EMEM_ARB_TIMING_RC                   0xa0
  18 #define MC_EMEM_ARB_TIMING_RAS                  0xa4
  19 #define MC_EMEM_ARB_TIMING_FAW                  0xa8
  20 #define MC_EMEM_ARB_TIMING_RRD                  0xac
  21 #define MC_EMEM_ARB_TIMING_RAP2PRE              0xb0
  22 #define MC_EMEM_ARB_TIMING_WAP2PRE              0xb4
  23 #define MC_EMEM_ARB_TIMING_R2R                  0xb8
  24 #define MC_EMEM_ARB_TIMING_W2W                  0xbc
  25 #define MC_EMEM_ARB_TIMING_R2W                  0xc0
  26 #define MC_EMEM_ARB_TIMING_W2R                  0xc4
  27 #define MC_EMEM_ARB_DA_TURNS                    0xd0
  28 #define MC_EMEM_ARB_DA_COVERS                   0xd4
  29 #define MC_EMEM_ARB_MISC0                       0xd8
  30 #define MC_EMEM_ARB_MISC1                       0xdc
  31 #define MC_EMEM_ARB_RING1_THROTTLE              0xe0
  32
  33 static const struct tegra_mc_client tegra124_mc_clients[] = {
  34         {
  35                 .id = 0x00,
  36                 .name = "ptcr",
  37                 .swgroup = TEGRA_SWGROUP_PTC,
  38         }, {
  39                 .id = 0x01,
  40                 .name = "display0a",
  41                 .swgroup = TEGRA_SWGROUP_DC,
  42                 .smmu = {
  43                         .reg = 0x228,
  44                         .bit = 1,
  45                 },
  46                 .la = {
  47                         .reg = 0x2e8,
  48                         .shift = 0,
  49                         .mask = 0xff,
  50                         .def = 0xc2,
  51                 },
  52         }, {
  53                 .id = 0x02,
  54                 .name = "display0ab",
  55                 .swgroup = TEGRA_SWGROUP_DCB,
  56                 .smmu = {
  57                         .reg = 0x228,
  58                         .bit = 2,
  59                 },
  60                 .la = {
  61                         .reg = 0x2f4,
  62                         .shift = 0,
  63                         .mask = 0xff,
  64                         .def = 0xc6,
  65                 },
  66         }, {
  67                 .id = 0x03,
  68                 .name = "display0b",
  69                 .swgroup = TEGRA_SWGROUP_DC,
  70                 .smmu = {
  71                         .reg = 0x228,
  72                         .bit = 3,
  73                 },
  74                 .la = {
  75                         .reg = 0x2e8,
  76                         .shift = 16,
  77                         .mask = 0xff,
  78                         .def = 0x50,
  79                 },
  80         }, {
  81                 .id = 0x04,
  82                 .name = "display0bb",
  83                 .swgroup = TEGRA_SWGROUP_DCB,
  84                 .smmu = {
  85                         .reg = 0x228,
  86                         .bit = 4,
  87                 },
  88                 .la = {
  89                         .reg = 0x2f4,
  90                         .shift = 16,
  91                         .mask = 0xff,
  92                         .def = 0x50,
  93                 },
  94         }, {
  95                 .id = 0x05,
  96                 .name = "display0c",
  97                 .swgroup = TEGRA_SWGROUP_DC,
  98                 .smmu = {
  99                         .reg = 0x228,
 100                         .bit = 5,
 101                 },
 102                 .la = {
 103                         .reg = 0x2ec,
 104                         .shift = 0,
 105                         .mask = 0xff,
 106                         .def = 0x50,
 107                 },
 108         }, {
 109                 .id = 0x06,
 110                 .name = "display0cb",
 111                 .swgroup = TEGRA_SWGROUP_DCB,
 112                 .smmu = {
 113                         .reg = 0x228,
 114                         .bit = 6,
 115                 },
 116                 .la = {
 117                         .reg = 0x2f8,
 118                         .shift = 0,
 119                         .mask = 0xff,
 120                         .def = 0x50,
 121                 },
 122         }, {
 123                 .id = 0x0e,
 124                 .name = "afir",
 125                 .swgroup = TEGRA_SWGROUP_AFI,
 126                 .smmu = {
 127                         .reg = 0x228,
 128                         .bit = 14,
 129                 },
 130                 .la = {
 131                         .reg = 0x2e0,
 132                         .shift = 0,
 133                         .mask = 0xff,
 134                         .def = 0x13,
 135                 },
 136         }, {
 137                 .id = 0x0f,
 138                 .name = "avpcarm7r",
 139                 .swgroup = TEGRA_SWGROUP_AVPC,
 140                 .smmu = {
 141                         .reg = 0x228,
 142                         .bit = 15,
 143                 },
 144                 .la = {
 145                         .reg = 0x2e4,
 146                         .shift = 0,
 147                         .mask = 0xff,
 148                         .def = 0x04,
 149                 },
 150         }, {
 151                 .id = 0x10,
 152                 .name = "displayhc",
 153                 .swgroup = TEGRA_SWGROUP_DC,
 154                 .smmu = {
 155                         .reg = 0x228,
 156                         .bit = 16,
 157                 },
 158                 .la = {
 159                         .reg = 0x2f0,
 160                         .shift = 0,
 161                         .mask = 0xff,
 162                         .def = 0x50,
 163                 },
 164         }, {
 165                 .id = 0x11,
 166                 .name = "displayhcb",
 167                 .swgroup = TEGRA_SWGROUP_DCB,
 168                 .smmu = {
 169                         .reg = 0x228,
 170                         .bit = 17,
 171                 },
 172                 .la = {
 173                         .reg = 0x2fc,
 174                         .shift = 0,
 175                         .mask = 0xff,
 176                         .def = 0x50,
 177                 },
 178         }, {
 179                 .id = 0x15,
 180                 .name = "hdar",
 181                 .swgroup = TEGRA_SWGROUP_HDA,
 182                 .smmu = {
 183                         .reg = 0x228,
 184                         .bit = 21,
 185                 },
 186                 .la = {
 187                         .reg = 0x318,
 188                         .shift = 0,
 189                         .mask = 0xff,
 190                         .def = 0x24,
 191                 },
 192         }, {
 193                 .id = 0x16,
 194                 .name = "host1xdmar",
 195                 .swgroup = TEGRA_SWGROUP_HC,
 196                 .smmu = {
 197                         .reg = 0x228,
 198                         .bit = 22,
 199                 },
 200                 .la = {
 201                         .reg = 0x310,
 202                         .shift = 0,
 203                         .mask = 0xff,
 204                         .def = 0x1e,
 205                 },
 206         }, {
 207                 .id = 0x17,
 208                 .name = "host1xr",
 209                 .swgroup = TEGRA_SWGROUP_HC,
 210                 .smmu = {
 211                         .reg = 0x228,
 212                         .bit = 23,
 213                 },
 214                 .la = {
 215                         .reg = 0x310,
 216                         .shift = 16,
 217                         .mask = 0xff,
 218                         .def = 0x50,
 219                 },
 220         }, {
 221                 .id = 0x1c,
 222                 .name = "msencsrd",
 223                 .swgroup = TEGRA_SWGROUP_MSENC,
 224                 .smmu = {
 225                         .reg = 0x228,
 226                         .bit = 28,
 227                 },
 228                 .la = {
 229                         .reg = 0x328,
 230                         .shift = 0,
 231                         .mask = 0xff,
 232                         .def = 0x23,
 233                 },
 234         }, {
 235                 .id = 0x1d,
 236                 .name = "ppcsahbdmar",
 237                 .swgroup = TEGRA_SWGROUP_PPCS,
 238                 .smmu = {
 239                         .reg = 0x228,
 240                         .bit = 29,
 241                 },
 242                 .la = {
 243                         .reg = 0x344,
 244                         .shift = 0,
 245                         .mask = 0xff,
 246                         .def = 0x49,
 247                 },
 248         }, {
 249                 .id = 0x1e,
 250                 .name = "ppcsahbslvr",
 251                 .swgroup = TEGRA_SWGROUP_PPCS,
 252                 .smmu = {
 253                         .reg = 0x228,
 254                         .bit = 30,
 255                 },
 256                 .la = {
 257                         .reg = 0x344,
 258                         .shift = 16,
 259                         .mask = 0xff,
 260                         .def = 0x1a,
 261                 },
 262         }, {
 263                 .id = 0x1f,
 264                 .name = "satar",
 265                 .swgroup = TEGRA_SWGROUP_SATA,
 266                 .smmu = {
 267                         .reg = 0x228,
 268                         .bit = 31,
 269                 },
 270                 .la = {
 271                         .reg = 0x350,
 272                         .shift = 0,
 273                         .mask = 0xff,
 274                         .def = 0x65,
 275                 },
 276         }, {
 277                 .id = 0x22,
 278                 .name = "vdebsevr",
 279                 .swgroup = TEGRA_SWGROUP_VDE,
 280                 .smmu = {
 281                         .reg = 0x22c,
 282                         .bit = 2,
 283                 },
 284                 .la = {
 285                         .reg = 0x354,
 286                         .shift = 0,
 287                         .mask = 0xff,
 288                         .def = 0x4f,
 289                 },
 290         }, {
 291                 .id = 0x23,
 292                 .name = "vdember",
 293                 .swgroup = TEGRA_SWGROUP_VDE,
 294                 .smmu = {
 295                         .reg = 0x22c,
 296                         .bit = 3,
 297                 },
 298                 .la = {
 299                         .reg = 0x354,
 300                         .shift = 16,
 301                         .mask = 0xff,
 302                         .def = 0x3d,
 303                 },
 304         }, {
 305                 .id = 0x24,
 306                 .name = "vdemcer",
 307                 .swgroup = TEGRA_SWGROUP_VDE,
 308                 .smmu = {
 309                         .reg = 0x22c,
 310                         .bit = 4,
 311                 },
 312                 .la = {
 313                         .reg = 0x358,
 314                         .shift = 0,
 315                         .mask = 0xff,
 316                         .def = 0x66,
 317                 },
 318         }, {
 319                 .id = 0x25,
 320                 .name = "vdetper",
 321                 .swgroup = TEGRA_SWGROUP_VDE,
 322                 .smmu = {
 323                         .reg = 0x22c,
 324                         .bit = 5,
 325                 },
 326                 .la = {
 327                         .reg = 0x358,
 328                         .shift = 16,
 329                         .mask = 0xff,
 330                         .def = 0xa5,
 331                 },
 332         }, {
 333                 .id = 0x26,
 334                 .name = "mpcorelpr",
 335                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 336                 .la = {
 337                         .reg = 0x324,
 338                         .shift = 0,
 339                         .mask = 0xff,
 340                         .def = 0x04,
 341                 },
 342         }, {
 343                 .id = 0x27,
 344                 .name = "mpcorer",
 345                 .swgroup = TEGRA_SWGROUP_MPCORE,
 346                 .la = {
 347                         .reg = 0x320,
 348                         .shift = 0,
 349                         .mask = 0xff,
 350                         .def = 0x04,
 351                 },
 352         }, {
 353                 .id = 0x2b,
 354                 .name = "msencswr",
 355                 .swgroup = TEGRA_SWGROUP_MSENC,
 356                 .smmu = {
 357                         .reg = 0x22c,
 358                         .bit = 11,
 359                 },
 360                 .la = {
 361                         .reg = 0x328,
 362                         .shift = 16,
 363                         .mask = 0xff,
 364                         .def = 0x80,
 365                 },
 366         }, {
 367                 .id = 0x31,
 368                 .name = "afiw",
 369                 .swgroup = TEGRA_SWGROUP_AFI,
 370                 .smmu = {
 371                         .reg = 0x22c,
 372                         .bit = 17,
 373                 },
 374                 .la = {
 375                         .reg = 0x2e0,
 376                         .shift = 16,
 377                         .mask = 0xff,
 378                         .def = 0x80,
 379                 },
 380         }, {
 381                 .id = 0x32,
 382                 .name = "avpcarm7w",
 383                 .swgroup = TEGRA_SWGROUP_AVPC,
 384                 .smmu = {
 385                         .reg = 0x22c,
 386                         .bit = 18,
 387                 },
 388                 .la = {
 389                         .reg = 0x2e4,
 390                         .shift = 16,
 391                         .mask = 0xff,
 392                         .def = 0x80,
 393                 },
 394         }, {
 395                 .id = 0x35,
 396                 .name = "hdaw",
 397                 .swgroup = TEGRA_SWGROUP_HDA,
 398                 .smmu = {
 399                         .reg = 0x22c,
 400                         .bit = 21,
 401                 },
 402                 .la = {
 403                         .reg = 0x318,
 404                         .shift = 16,
 405                         .mask = 0xff,
 406                         .def = 0x80,
 407                 },
 408         }, {
 409                 .id = 0x36,
 410                 .name = "host1xw",
 411                 .swgroup = TEGRA_SWGROUP_HC,
 412                 .smmu = {
 413                         .reg = 0x22c,
 414                         .bit = 22,
 415                 },
 416                 .la = {
 417                         .reg = 0x314,
 418                         .shift = 0,
 419                         .mask = 0xff,
 420                         .def = 0x80,
 421                 },
 422         }, {
 423                 .id = 0x38,
 424                 .name = "mpcorelpw",
 425                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 426                 .la = {
 427                         .reg = 0x324,
 428                         .shift = 16,
 429                         .mask = 0xff,
 430                         .def = 0x80,
 431                 },
 432         }, {
 433                 .id = 0x39,
 434                 .name = "mpcorew",
 435                 .swgroup = TEGRA_SWGROUP_MPCORE,
 436                 .la = {
 437                         .reg = 0x320,
 438                         .shift = 16,
 439                         .mask = 0xff,
 440                         .def = 0x80,
 441                 },
 442         }, {
 443                 .id = 0x3b,
 444                 .name = "ppcsahbdmaw",
 445                 .swgroup = TEGRA_SWGROUP_PPCS,
 446                 .smmu = {
 447                         .reg = 0x22c,
 448                         .bit = 27,
 449                 },
 450                 .la = {
 451                         .reg = 0x348,
 452                         .shift = 0,
 453                         .mask = 0xff,
 454                         .def = 0x80,
 455                 },
 456         }, {
 457                 .id = 0x3c,
 458                 .name = "ppcsahbslvw",
 459                 .swgroup = TEGRA_SWGROUP_PPCS,
 460                 .smmu = {
 461                         .reg = 0x22c,
 462                         .bit = 28,
 463                 },
 464                 .la = {
 465                         .reg = 0x348,
 466                         .shift = 16,
 467                         .mask = 0xff,
 468                         .def = 0x80,
 469                 },
 470         }, {
 471                 .id = 0x3d,
 472                 .name = "sataw",
 473                 .swgroup = TEGRA_SWGROUP_SATA,
 474                 .smmu = {
 475                         .reg = 0x22c,
 476                         .bit = 29,
 477                 },
 478                 .la = {
 479                         .reg = 0x350,
 480                         .shift = 16,
 481                         .mask = 0xff,
 482                         .def = 0x65,
 483                 },
 484         }, {
 485                 .id = 0x3e,
 486                 .name = "vdebsevw",
 487                 .swgroup = TEGRA_SWGROUP_VDE,
 488                 .smmu = {
 489                         .reg = 0x22c,
 490                         .bit = 30,
 491                 },
 492                 .la = {
 493                         .reg = 0x35c,
 494                         .shift = 0,
 495                         .mask = 0xff,
 496                         .def = 0x80,
 497                 },
 498         }, {
 499                 .id = 0x3f,
 500                 .name = "vdedbgw",
 501                 .swgroup = TEGRA_SWGROUP_VDE,
 502                 .smmu = {
 503                         .reg = 0x22c,
 504                         .bit = 31,
 505                 },
 506                 .la = {
 507                         .reg = 0x35c,
 508                         .shift = 16,
 509                         .mask = 0xff,
 510                         .def = 0x80,
 511                 },
 512         }, {
 513                 .id = 0x40,
 514                 .name = "vdembew",
 515                 .swgroup = TEGRA_SWGROUP_VDE,
 516                 .smmu = {
 517                         .reg = 0x230,
 518                         .bit = 0,
 519                 },
 520                 .la = {
 521                         .reg = 0x360,
 522                         .shift = 0,
 523                         .mask = 0xff,
 524                         .def = 0x80,
 525                 },
 526         }, {
 527                 .id = 0x41,
 528                 .name = "vdetpmw",
 529                 .swgroup = TEGRA_SWGROUP_VDE,
 530                 .smmu = {
 531                         .reg = 0x230,
 532                         .bit = 1,
 533                 },
 534                 .la = {
 535                         .reg = 0x360,
 536                         .shift = 16,
 537                         .mask = 0xff,
 538                         .def = 0x80,
 539                 },
 540         }, {
 541                 .id = 0x44,
 542                 .name = "ispra",
 543                 .swgroup = TEGRA_SWGROUP_ISP2,
 544                 .smmu = {
 545                         .reg = 0x230,
 546                         .bit = 4,
 547                 },
 548                 .la = {
 549                         .reg = 0x370,
 550                         .shift = 0,
 551                         .mask = 0xff,
 552                         .def = 0x18,
 553                 },
 554         }, {
 555                 .id = 0x46,
 556                 .name = "ispwa",
 557                 .swgroup = TEGRA_SWGROUP_ISP2,
 558                 .smmu = {
 559                         .reg = 0x230,
 560                         .bit = 6,
 561                 },
 562                 .la = {
 563                         .reg = 0x374,
 564                         .shift = 0,
 565                         .mask = 0xff,
 566                         .def = 0x80,
 567                 },
 568         }, {
 569                 .id = 0x47,
 570                 .name = "ispwb",
 571                 .swgroup = TEGRA_SWGROUP_ISP2,
 572                 .smmu = {
 573                         .reg = 0x230,
 574                         .bit = 7,
 575                 },
 576                 .la = {
 577                         .reg = 0x374,
 578                         .shift = 16,
 579                         .mask = 0xff,
 580                         .def = 0x80,
 581                 },
 582         }, {
 583                 .id = 0x4a,
 584                 .name = "xusb_hostr",
 585                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 586                 .smmu = {
 587                         .reg = 0x230,
 588                         .bit = 10,
 589                 },
 590                 .la = {
 591                         .reg = 0x37c,
 592                         .shift = 0,
 593                         .mask = 0xff,
 594                         .def = 0x39,
 595                 },
 596         }, {
 597                 .id = 0x4b,
 598                 .name = "xusb_hostw",
 599                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 600                 .smmu = {
 601                         .reg = 0x230,
 602                         .bit = 11,
 603                 },
 604                 .la = {
 605                         .reg = 0x37c,
 606                         .shift = 16,
 607                         .mask = 0xff,
 608                         .def = 0x80,
 609                 },
 610         }, {
 611                 .id = 0x4c,
 612                 .name = "xusb_devr",
 613                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 614                 .smmu = {
 615                         .reg = 0x230,
 616                         .bit = 12,
 617                 },
 618                 .la = {
 619                         .reg = 0x380,
 620                         .shift = 0,
 621                         .mask = 0xff,
 622                         .def = 0x39,
 623                 },
 624         }, {
 625                 .id = 0x4d,
 626                 .name = "xusb_devw",
 627                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 628                 .smmu = {
 629                         .reg = 0x230,
 630                         .bit = 13,
 631                 },
 632                 .la = {
 633                         .reg = 0x380,
 634                         .shift = 16,
 635                         .mask = 0xff,
 636                         .def = 0x80,
 637                 },
 638         }, {
 639                 .id = 0x4e,
 640                 .name = "isprab",
 641                 .swgroup = TEGRA_SWGROUP_ISP2B,
 642                 .smmu = {
 643                         .reg = 0x230,
 644                         .bit = 14,
 645                 },
 646                 .la = {
 647                         .reg = 0x384,
 648                         .shift = 0,
 649                         .mask = 0xff,
 650                         .def = 0x18,
 651                 },
 652         }, {
 653                 .id = 0x50,
 654                 .name = "ispwab",
 655                 .swgroup = TEGRA_SWGROUP_ISP2B,
 656                 .smmu = {
 657                         .reg = 0x230,
 658                         .bit = 16,
 659                 },
 660                 .la = {
 661                         .reg = 0x388,
 662                         .shift = 0,
 663                         .mask = 0xff,
 664                         .def = 0x80,
 665                 },
 666         }, {
 667                 .id = 0x51,
 668                 .name = "ispwbb",
 669                 .swgroup = TEGRA_SWGROUP_ISP2B,
 670                 .smmu = {
 671                         .reg = 0x230,
 672                         .bit = 17,
 673                 },
 674                 .la = {
 675                         .reg = 0x388,
 676                         .shift = 16,
 677                         .mask = 0xff,
 678                         .def = 0x80,
 679                 },
 680         }, {
 681                 .id = 0x54,
 682                 .name = "tsecsrd",
 683                 .swgroup = TEGRA_SWGROUP_TSEC,
 684                 .smmu = {
 685                         .reg = 0x230,
 686                         .bit = 20,
 687                 },
 688                 .la = {
 689                         .reg = 0x390,
 690                         .shift = 0,
 691                         .mask = 0xff,
 692                         .def = 0x9b,
 693                 },
 694         }, {
 695                 .id = 0x55,
 696                 .name = "tsecswr",
 697                 .swgroup = TEGRA_SWGROUP_TSEC,
 698                 .smmu = {
 699                         .reg = 0x230,
 700                         .bit = 21,
 701                 },
 702                 .la = {
 703                         .reg = 0x390,
 704                         .shift = 16,
 705                         .mask = 0xff,
 706                         .def = 0x80,
 707                 },
 708         }, {
 709                 .id = 0x56,
 710                 .name = "a9avpscr",
 711                 .swgroup = TEGRA_SWGROUP_A9AVP,
 712                 .smmu = {
 713                         .reg = 0x230,
 714                         .bit = 22,
 715                 },
 716                 .la = {
 717                         .reg = 0x3a4,
 718                         .shift = 0,
 719                         .mask = 0xff,
 720                         .def = 0x04,
 721                 },
 722         }, {
 723                 .id = 0x57,
 724                 .name = "a9avpscw",
 725                 .swgroup = TEGRA_SWGROUP_A9AVP,
 726                 .smmu = {
 727                         .reg = 0x230,
 728                         .bit = 23,
 729                 },
 730                 .la = {
 731                         .reg = 0x3a4,
 732                         .shift = 16,
 733                         .mask = 0xff,
 734                         .def = 0x80,
 735                 },
 736         }, {
 737                 .id = 0x58,
 738                 .name = "gpusrd",
 739                 .swgroup = TEGRA_SWGROUP_GPU,
 740                 .smmu = {
 741                         /* read-only */
 742                         .reg = 0x230,
 743                         .bit = 24,
 744                 },
 745                 .la = {
 746                         .reg = 0x3c8,
 747                         .shift = 0,
 748                         .mask = 0xff,
 749                         .def = 0x1a,
 750                 },
 751         }, {
 752                 .id = 0x59,
 753                 .name = "gpuswr",
 754                 .swgroup = TEGRA_SWGROUP_GPU,
 755                 .smmu = {
 756                         /* read-only */
 757                         .reg = 0x230,
 758                         .bit = 25,
 759                 },
 760                 .la = {
 761                         .reg = 0x3c8,
 762                         .shift = 16,
 763                         .mask = 0xff,
 764                         .def = 0x80,
 765                 },
 766         }, {
 767                 .id = 0x5a,
 768                 .name = "displayt",
 769                 .swgroup = TEGRA_SWGROUP_DC,
 770                 .smmu = {
 771                         .reg = 0x230,
 772                         .bit = 26,
 773                 },
 774                 .la = {
 775                         .reg = 0x2f0,
 776                         .shift = 16,
 777                         .mask = 0xff,
 778                         .def = 0x50,
 779                 },
 780         }, {
 781                 .id = 0x60,
 782                 .name = "sdmmcra",
 783                 .swgroup = TEGRA_SWGROUP_SDMMC1A,
 784                 .smmu = {
 785                         .reg = 0x234,
 786                         .bit = 0,
 787                 },
 788                 .la = {
 789                         .reg = 0x3b8,
 790                         .shift = 0,
 791                         .mask = 0xff,
 792                         .def = 0x49,
 793                 },
 794         }, {
 795                 .id = 0x61,
 796                 .name = "sdmmcraa",
 797                 .swgroup = TEGRA_SWGROUP_SDMMC2A,
 798                 .smmu = {
 799                         .reg = 0x234,
 800                         .bit = 1,
 801                 },
 802                 .la = {
 803                         .reg = 0x3bc,
 804                         .shift = 0,
 805                         .mask = 0xff,
 806                         .def = 0x49,
 807                 },
 808         }, {
 809                 .id = 0x62,
 810                 .name = "sdmmcr",
 811                 .swgroup = TEGRA_SWGROUP_SDMMC3A,
 812                 .smmu = {
 813                         .reg = 0x234,
 814                         .bit = 2,
 815                 },
 816                 .la = {
 817                         .reg = 0x3c0,
 818                         .shift = 0,
 819                         .mask = 0xff,
 820                         .def = 0x49,
 821                 },
 822         }, {
 823                 .id = 0x63,
 824                 .swgroup = TEGRA_SWGROUP_SDMMC4A,
 825                 .name = "sdmmcrab",
 826                 .smmu = {
 827                         .reg = 0x234,
 828                         .bit = 3,
 829                 },
 830                 .la = {
 831                         .reg = 0x3c4,
 832                         .shift = 0,
 833                         .mask = 0xff,
 834                         .def = 0x49,
 835                 },
 836         }, {
 837                 .id = 0x64,
 838                 .name = "sdmmcwa",
 839                 .swgroup = TEGRA_SWGROUP_SDMMC1A,
 840                 .smmu = {
 841                         .reg = 0x234,
 842                         .bit = 4,
 843                 },
 844                 .la = {
 845                         .reg = 0x3b8,
 846                         .shift = 16,
 847                         .mask = 0xff,
 848                         .def = 0x80,
 849                 },
 850         }, {
 851                 .id = 0x65,
 852                 .name = "sdmmcwaa",
 853                 .swgroup = TEGRA_SWGROUP_SDMMC2A,
 854                 .smmu = {
 855                         .reg = 0x234,
 856                         .bit = 5,
 857                 },
 858                 .la = {
 859                         .reg = 0x3bc,
 860                         .shift = 16,
 861                         .mask = 0xff,
 862                         .def = 0x80,
 863                 },
 864         }, {
 865                 .id = 0x66,
 866                 .name = "sdmmcw",
 867                 .swgroup = TEGRA_SWGROUP_SDMMC3A,
 868                 .smmu = {
 869                         .reg = 0x234,
 870                         .bit = 6,
 871                 },
 872                 .la = {
 873                         .reg = 0x3c0,
 874                         .shift = 16,
 875                         .mask = 0xff,
 876                         .def = 0x80,
 877                 },
 878         }, {
 879                 .id = 0x67,
 880                 .name = "sdmmcwab",
 881                 .swgroup = TEGRA_SWGROUP_SDMMC4A,
 882                 .smmu = {
 883                         .reg = 0x234,
 884                         .bit = 7,
 885                 },
 886                 .la = {
 887                         .reg = 0x3c4,
 888                         .shift = 16,
 889                         .mask = 0xff,
 890                         .def = 0x80,
 891                 },
 892         }, {
 893                 .id = 0x6c,
 894                 .name = "vicsrd",
 895                 .swgroup = TEGRA_SWGROUP_VIC,
 896                 .smmu = {
 897                         .reg = 0x234,
 898                         .bit = 12,
 899                 },
 900                 .la = {
 901                         .reg = 0x394,
 902                         .shift = 0,
 903                         .mask = 0xff,
 904                         .def = 0x1a,
 905                 },
 906         }, {
 907                 .id = 0x6d,
 908                 .name = "vicswr",
 909                 .swgroup = TEGRA_SWGROUP_VIC,
 910                 .smmu = {
 911                         .reg = 0x234,
 912                         .bit = 13,
 913                 },
 914                 .la = {
 915                         .reg = 0x394,
 916                         .shift = 16,
 917                         .mask = 0xff,
 918                         .def = 0x80,
 919                 },
 920         }, {
 921                 .id = 0x72,
 922                 .name = "viw",
 923                 .swgroup = TEGRA_SWGROUP_VI,
 924                 .smmu = {
 925                         .reg = 0x234,
 926                         .bit = 18,
 927                 },
 928                 .la = {
 929                         .reg = 0x398,
 930                         .shift = 0,
 931                         .mask = 0xff,
 932                         .def = 0x80,
 933                 },
 934         }, {
 935                 .id = 0x73,
 936                 .name = "displayd",
 937                 .swgroup = TEGRA_SWGROUP_DC,
 938                 .smmu = {
 939                         .reg = 0x234,
 940                         .bit = 19,
 941                 },
 942                 .la = {
 943                         .reg = 0x3c8,
 944                         .shift = 0,
 945                         .mask = 0xff,
 946                         .def = 0x50,
 947                 },
 948         },
 949 };
 950
 951 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
 952         { .name = "dc",        .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },
 953         { .name = "dcb",       .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },
 954         { .name = "afi",       .swgroup = TEGRA_SWGROUP_AFI,       .reg = 0x238 },
 955         { .name = "avpc",      .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },
 956         { .name = "hda",       .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },
 957         { .name = "hc",        .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },
 958         { .name = "msenc",     .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },
 959         { .name = "ppcs",      .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },
 960         { .name = "sata",      .swgroup = TEGRA_SWGROUP_SATA,      .reg = 0x274 },
 961         { .name = "vde",       .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },
 962         { .name = "isp2",      .swgroup = TEGRA_SWGROUP_ISP2,      .reg = 0x258 },
 963         { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
 964         { .name = "xusb_dev",  .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },
 965         { .name = "isp2b",     .swgroup = TEGRA_SWGROUP_ISP2B,     .reg = 0xaa4 },
 966         { .name = "tsec",      .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },
 967         { .name = "a9avp",     .swgroup = TEGRA_SWGROUP_A9AVP,     .reg = 0x290 },
 968         { .name = "gpu",       .swgroup = TEGRA_SWGROUP_GPU,       .reg = 0xaac },
 969         { .name = "sdmmc1a",   .swgroup = TEGRA_SWGROUP_SDMMC1A,   .reg = 0xa94 },
 970         { .name = "sdmmc2a",   .swgroup = TEGRA_SWGROUP_SDMMC2A,   .reg = 0xa98 },
 971         { .name = "sdmmc3a",   .swgroup = TEGRA_SWGROUP_SDMMC3A,   .reg = 0xa9c },
 972         { .name = "sdmmc4a",   .swgroup = TEGRA_SWGROUP_SDMMC4A,   .reg = 0xaa0 },
 973         { .name = "vic",       .swgroup = TEGRA_SWGROUP_VIC,       .reg = 0x284 },
 974         { .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
 975 };
 976
 977 static const unsigned int tegra124_group_display[] = {
 978         TEGRA_SWGROUP_DC,
 979         TEGRA_SWGROUP_DCB,
 980 };
 981
 982 static const struct tegra_smmu_group_soc tegra124_groups[] = {
 983         {
 984                 .name = "display",
 985                 .swgroups = tegra124_group_display,
 986                 .num_swgroups = ARRAY_SIZE(tegra124_group_display),
 987         },
 988 };
 989
 990 #define TEGRA124_MC_RESET(_name, _control, _status, _bit)       \
 991         {                                                       \
 992                 .name = #_name,                                 \
 993                 .id = TEGRA124_MC_RESET_##_name,                \
 994                 .control = _control,                            \
 995                 .status = _status,                              \
 996                 .bit = _bit,                                    \
 997         }
 998
 999 static const struct tegra_mc_reset tegra124_mc_resets[] = {
1000         TEGRA124_MC_RESET(AFI,       0x200, 0x204,  0),
1001         TEGRA124_MC_RESET(AVPC,      0x200, 0x204,  1),
1002         TEGRA124_MC_RESET(DC,        0x200, 0x204,  2),
1003         TEGRA124_MC_RESET(DCB,       0x200, 0x204,  3),
1004         TEGRA124_MC_RESET(HC,        0x200, 0x204,  6),
1005         TEGRA124_MC_RESET(HDA,       0x200, 0x204,  7),
1006         TEGRA124_MC_RESET(ISP2,      0x200, 0x204,  8),
1007         TEGRA124_MC_RESET(MPCORE,    0x200, 0x204,  9),
1008         TEGRA124_MC_RESET(MPCORELP,  0x200, 0x204, 10),
1009         TEGRA124_MC_RESET(MSENC,     0x200, 0x204, 11),
1010         TEGRA124_MC_RESET(PPCS,      0x200, 0x204, 14),
1011         TEGRA124_MC_RESET(SATA,      0x200, 0x204, 15),
1012         TEGRA124_MC_RESET(VDE,       0x200, 0x204, 16),
1013         TEGRA124_MC_RESET(VI,        0x200, 0x204, 17),
1014         TEGRA124_MC_RESET(VIC,       0x200, 0x204, 18),
1015         TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1016         TEGRA124_MC_RESET(XUSB_DEV,  0x200, 0x204, 20),
1017         TEGRA124_MC_RESET(TSEC,      0x200, 0x204, 21),
1018         TEGRA124_MC_RESET(SDMMC1,    0x200, 0x204, 22),
1019         TEGRA124_MC_RESET(SDMMC2,    0x200, 0x204, 23),
1020         TEGRA124_MC_RESET(SDMMC3,    0x200, 0x204, 25),
1021         TEGRA124_MC_RESET(SDMMC4,    0x970, 0x974,  0),
1022         TEGRA124_MC_RESET(ISP2B,     0x970, 0x974,  1),
1023         TEGRA124_MC_RESET(GPU,       0x970, 0x974,  2),
1024 };
1025
1026 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1027 static const unsigned long tegra124_mc_emem_regs[] = {
1028         MC_EMEM_ARB_CFG,
1029         MC_EMEM_ARB_OUTSTANDING_REQ,
1030         MC_EMEM_ARB_TIMING_RCD,
1031         MC_EMEM_ARB_TIMING_RP,
1032         MC_EMEM_ARB_TIMING_RC,
1033         MC_EMEM_ARB_TIMING_RAS,
1034         MC_EMEM_ARB_TIMING_FAW,
1035         MC_EMEM_ARB_TIMING_RRD,
1036         MC_EMEM_ARB_TIMING_RAP2PRE,
1037         MC_EMEM_ARB_TIMING_WAP2PRE,
1038         MC_EMEM_ARB_TIMING_R2R,
1039         MC_EMEM_ARB_TIMING_W2W,
1040         MC_EMEM_ARB_TIMING_R2W,
1041         MC_EMEM_ARB_TIMING_W2R,
1042         MC_EMEM_ARB_DA_TURNS,
1043         MC_EMEM_ARB_DA_COVERS,
1044         MC_EMEM_ARB_MISC0,
1045         MC_EMEM_ARB_MISC1,
1046         MC_EMEM_ARB_RING1_THROTTLE
1047 };
1048
1049 static const struct tegra_smmu_soc tegra124_smmu_soc = {
1050         .clients = tegra124_mc_clients,
1051         .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1052         .swgroups = tegra124_swgroups,
1053         .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1054         .groups = tegra124_groups,
1055         .num_groups = ARRAY_SIZE(tegra124_groups),
1056         .supports_round_robin_arbitration = true,
1057         .supports_request_limit = true,
1058         .num_tlb_lines = 32,
1059         .num_asids = 128,
1060 };
1061
1062 const struct tegra_mc_soc tegra124_mc_soc = {
1063         .clients = tegra124_mc_clients,
1064         .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1065         .num_address_bits = 34,
1066         .atom_size = 32,
1067         .client_id_mask = 0x7f,
1068         .smmu = &tegra124_smmu_soc,
1069         .emem_regs = tegra124_mc_emem_regs,
1070         .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1071         .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1072                    MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1073                    MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1074         .reset_ops = &tegra_mc_reset_ops_common,
1075         .resets = tegra124_mc_resets,
1076         .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1077 };
1078 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
1079
1080 #ifdef CONFIG_ARCH_TEGRA_132_SOC
1081 static const struct tegra_smmu_soc tegra132_smmu_soc = {
1082         .clients = tegra124_mc_clients,
1083         .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1084         .swgroups = tegra124_swgroups,
1085         .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1086         .groups = tegra124_groups,
1087         .num_groups = ARRAY_SIZE(tegra124_groups),
1088         .supports_round_robin_arbitration = true,
1089         .supports_request_limit = true,
1090         .num_tlb_lines = 32,
1091         .num_asids = 128,
1092 };
1093
1094 const struct tegra_mc_soc tegra132_mc_soc = {
1095         .clients = tegra124_mc_clients,
1096         .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1097         .num_address_bits = 34,
1098         .atom_size = 32,
1099         .client_id_mask = 0x7f,
1100         .smmu = &tegra132_smmu_soc,
1101         .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1102                    MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1103                    MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1104         .reset_ops = &tegra_mc_reset_ops_common,
1105         .resets = tegra124_mc_resets,
1106         .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1107 };
1108 #endif /* CONFIG_ARCH_TEGRA_132_SOC */