drivers/memory/tegra/tegra114.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/of.h>
   7 #include <linux/mm.h>
   8
   9 #include <dt-bindings/memory/tegra114-mc.h>
  10
  11 #include "mc.h"
  12
  13 static const struct tegra_mc_client tegra114_mc_clients[] = {
  14         {
  15                 .id = 0x00,
  16                 .name = "ptcr",
  17                 .swgroup = TEGRA_SWGROUP_PTC,
  18         }, {
  19                 .id = 0x01,
  20                 .name = "display0a",
  21                 .swgroup = TEGRA_SWGROUP_DC,
  22                 .smmu = {
  23                         .reg = 0x228,
  24                         .bit = 1,
  25                 },
  26                 .la = {
  27                         .reg = 0x2e8,
  28                         .shift = 0,
  29                         .mask = 0xff,
  30                         .def = 0x4e,
  31                 },
  32         }, {
  33                 .id = 0x02,
  34                 .name = "display0ab",
  35                 .swgroup = TEGRA_SWGROUP_DCB,
  36                 .smmu = {
  37                         .reg = 0x228,
  38                         .bit = 2,
  39                 },
  40                 .la = {
  41                         .reg = 0x2f4,
  42                         .shift = 0,
  43                         .mask = 0xff,
  44                         .def = 0x4e,
  45                 },
  46         }, {
  47                 .id = 0x03,
  48                 .name = "display0b",
  49                 .swgroup = TEGRA_SWGROUP_DC,
  50                 .smmu = {
  51                         .reg = 0x228,
  52                         .bit = 3,
  53                 },
  54                 .la = {
  55                         .reg = 0x2e8,
  56                         .shift = 16,
  57                         .mask = 0xff,
  58                         .def = 0x4e,
  59                 },
  60         }, {
  61                 .id = 0x04,
  62                 .name = "display0bb",
  63                 .swgroup = TEGRA_SWGROUP_DCB,
  64                 .smmu = {
  65                         .reg = 0x228,
  66                         .bit = 4,
  67                 },
  68                 .la = {
  69                         .reg = 0x2f4,
  70                         .shift = 16,
  71                         .mask = 0xff,
  72                         .def = 0x4e,
  73                 },
  74         }, {
  75                 .id = 0x05,
  76                 .name = "display0c",
  77                 .swgroup = TEGRA_SWGROUP_DC,
  78                 .smmu = {
  79                         .reg = 0x228,
  80                         .bit = 5,
  81                 },
  82                 .la = {
  83                         .reg = 0x2ec,
  84                         .shift = 0,
  85                         .mask = 0xff,
  86                         .def = 0x4e,
  87                 },
  88         }, {
  89                 .id = 0x06,
  90                 .name = "display0cb",
  91                 .swgroup = TEGRA_SWGROUP_DCB,
  92                 .smmu = {
  93                         .reg = 0x228,
  94                         .bit = 6,
  95                 },
  96                 .la = {
  97                         .reg = 0x2f8,
  98                         .shift = 0,
  99                         .mask = 0xff,
 100                         .def = 0x4e,
 101                 },
 102         }, {
 103                 .id = 0x09,
 104                 .name = "eppup",
 105                 .swgroup = TEGRA_SWGROUP_EPP,
 106                 .smmu = {
 107                         .reg = 0x228,
 108                         .bit = 9,
 109                 },
 110                 .la = {
 111                         .reg = 0x300,
 112                         .shift = 0,
 113                         .mask = 0xff,
 114                         .def = 0x33,
 115                 },
 116         }, {
 117                 .id = 0x0a,
 118                 .name = "g2pr",
 119                 .swgroup = TEGRA_SWGROUP_G2,
 120                 .smmu = {
 121                         .reg = 0x228,
 122                         .bit = 10,
 123                 },
 124                 .la = {
 125                         .reg = 0x308,
 126                         .shift = 0,
 127                         .mask = 0xff,
 128                         .def = 0x09,
 129                 },
 130         }, {
 131                 .id = 0x0b,
 132                 .name = "g2sr",
 133                 .swgroup = TEGRA_SWGROUP_G2,
 134                 .smmu = {
 135                         .reg = 0x228,
 136                         .bit = 11,
 137                 },
 138                 .la = {
 139                         .reg = 0x308,
 140                         .shift = 16,
 141                         .mask = 0xff,
 142                         .def = 0x09,
 143                 },
 144         }, {
 145                 .id = 0x0f,
 146                 .name = "avpcarm7r",
 147                 .swgroup = TEGRA_SWGROUP_AVPC,
 148                 .smmu = {
 149                         .reg = 0x228,
 150                         .bit = 15,
 151                 },
 152                 .la = {
 153                         .reg = 0x2e4,
 154                         .shift = 0,
 155                         .mask = 0xff,
 156                         .def = 0x04,
 157                 },
 158         }, {
 159                 .id = 0x10,
 160                 .name = "displayhc",
 161                 .swgroup = TEGRA_SWGROUP_DC,
 162                 .smmu = {
 163                         .reg = 0x228,
 164                         .bit = 16,
 165                 },
 166                 .la = {
 167                         .reg = 0x2f0,
 168                         .shift = 0,
 169                         .mask = 0xff,
 170                         .def = 0x68,
 171                 },
 172         }, {
 173                 .id = 0x11,
 174                 .name = "displayhcb",
 175                 .swgroup = TEGRA_SWGROUP_DCB,
 176                 .smmu = {
 177                         .reg = 0x228,
 178                         .bit = 17,
 179                 },
 180                 .la = {
 181                         .reg = 0x2fc,
 182                         .shift = 0,
 183                         .mask = 0xff,
 184                         .def = 0x68,
 185                 },
 186         }, {
 187                 .id = 0x12,
 188                 .name = "fdcdrd",
 189                 .swgroup = TEGRA_SWGROUP_NV,
 190                 .smmu = {
 191                         .reg = 0x228,
 192                         .bit = 18,
 193                 },
 194                 .la = {
 195                         .reg = 0x334,
 196                         .shift = 0,
 197                         .mask = 0xff,
 198                         .def = 0x0c,
 199                 },
 200         }, {
 201                 .id = 0x13,
 202                 .name = "fdcdrd2",
 203                 .swgroup = TEGRA_SWGROUP_NV,
 204                 .smmu = {
 205                         .reg = 0x228,
 206                         .bit = 19,
 207                 },
 208                 .la = {
 209                         .reg = 0x33c,
 210                         .shift = 0,
 211                         .mask = 0xff,
 212                         .def = 0x0c,
 213                 },
 214         }, {
 215                 .id = 0x14,
 216                 .name = "g2dr",
 217                 .swgroup = TEGRA_SWGROUP_G2,
 218                 .smmu = {
 219                         .reg = 0x228,
 220                         .bit = 20,
 221                 },
 222                 .la = {
 223                         .reg = 0x30c,
 224                         .shift = 0,
 225                         .mask = 0xff,
 226                         .def = 0x0a,
 227                 },
 228         }, {
 229                 .id = 0x15,
 230                 .name = "hdar",
 231                 .swgroup = TEGRA_SWGROUP_HDA,
 232                 .smmu = {
 233                         .reg = 0x228,
 234                         .bit = 21,
 235                 },
 236                 .la = {
 237                         .reg = 0x318,
 238                         .shift = 0,
 239                         .mask = 0xff,
 240                         .def = 0xff,
 241                 },
 242         }, {
 243                 .id = 0x16,
 244                 .name = "host1xdmar",
 245                 .swgroup = TEGRA_SWGROUP_HC,
 246                 .smmu = {
 247                         .reg = 0x228,
 248                         .bit = 22,
 249                 },
 250                 .la = {
 251                         .reg = 0x310,
 252                         .shift = 0,
 253                         .mask = 0xff,
 254                         .def = 0x10,
 255                 },
 256         }, {
 257                 .id = 0x17,
 258                 .name = "host1xr",
 259                 .swgroup = TEGRA_SWGROUP_HC,
 260                 .smmu = {
 261                         .reg = 0x228,
 262                         .bit = 23,
 263                 },
 264                 .la = {
 265                         .reg = 0x310,
 266                         .shift = 16,
 267                         .mask = 0xff,
 268                         .def = 0xa5,
 269                 },
 270         }, {
 271                 .id = 0x18,
 272                 .name = "idxsrd",
 273                 .swgroup = TEGRA_SWGROUP_NV,
 274                 .smmu = {
 275                         .reg = 0x228,
 276                         .bit = 24,
 277                 },
 278                 .la = {
 279                         .reg = 0x334,
 280                         .shift = 16,
 281                         .mask = 0xff,
 282                         .def = 0x0b,
 283                 },
 284         }, {
 285                 .id = 0x1c,
 286                 .name = "msencsrd",
 287                 .swgroup = TEGRA_SWGROUP_MSENC,
 288                 .smmu = {
 289                         .reg = 0x228,
 290                         .bit = 28,
 291                 },
 292                 .la = {
 293                         .reg = 0x328,
 294                         .shift = 0,
 295                         .mask = 0xff,
 296                         .def = 0x80,
 297                 },
 298         }, {
 299                 .id = 0x1d,
 300                 .name = "ppcsahbdmar",
 301                 .swgroup = TEGRA_SWGROUP_PPCS,
 302                 .smmu = {
 303                         .reg = 0x228,
 304                         .bit = 29,
 305                 },
 306                 .la = {
 307                         .reg = 0x344,
 308                         .shift = 0,
 309                         .mask = 0xff,
 310                         .def = 0x50,
 311                 },
 312         }, {
 313                 .id = 0x1e,
 314                 .name = "ppcsahbslvr",
 315                 .swgroup = TEGRA_SWGROUP_PPCS,
 316                 .smmu = {
 317                         .reg = 0x228,
 318                         .bit = 30,
 319                 },
 320                 .la = {
 321                         .reg = 0x344,
 322                         .shift = 16,
 323                         .mask = 0xff,
 324                         .def = 0xe8,
 325                 },
 326         }, {
 327                 .id = 0x20,
 328                 .name = "texl2srd",
 329                 .swgroup = TEGRA_SWGROUP_NV,
 330                 .smmu = {
 331                         .reg = 0x22c,
 332                         .bit = 0,
 333                 },
 334                 .la = {
 335                         .reg = 0x338,
 336                         .shift = 0,
 337                         .mask = 0xff,
 338                         .def = 0x0c,
 339                 },
 340         }, {
 341                 .id = 0x22,
 342                 .name = "vdebsevr",
 343                 .swgroup = TEGRA_SWGROUP_VDE,
 344                 .smmu = {
 345                         .reg = 0x22c,
 346                         .bit = 2,
 347                 },
 348                 .la = {
 349                         .reg = 0x354,
 350                         .shift = 0,
 351                         .mask = 0xff,
 352                         .def = 0xff,
 353                 },
 354         }, {
 355                 .id = 0x23,
 356                 .name = "vdember",
 357                 .swgroup = TEGRA_SWGROUP_VDE,
 358                 .smmu = {
 359                         .reg = 0x22c,
 360                         .bit = 3,
 361                 },
 362                 .la = {
 363                         .reg = 0x354,
 364                         .shift = 16,
 365                         .mask = 0xff,
 366                         .def = 0xff,
 367                 },
 368         }, {
 369                 .id = 0x24,
 370                 .name = "vdemcer",
 371                 .swgroup = TEGRA_SWGROUP_VDE,
 372                 .smmu = {
 373                         .reg = 0x22c,
 374                         .bit = 4,
 375                 },
 376                 .la = {
 377                         .reg = 0x358,
 378                         .shift = 0,
 379                         .mask = 0xff,
 380                         .def = 0xb8,
 381                 },
 382         }, {
 383                 .id = 0x25,
 384                 .name = "vdetper",
 385                 .swgroup = TEGRA_SWGROUP_VDE,
 386                 .smmu = {
 387                         .reg = 0x22c,
 388                         .bit = 5,
 389                 },
 390                 .la = {
 391                         .reg = 0x358,
 392                         .shift = 16,
 393                         .mask = 0xff,
 394                         .def = 0xee,
 395                 },
 396         }, {
 397                 .id = 0x26,
 398                 .name = "mpcorelpr",
 399                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 400                 .la = {
 401                         .reg = 0x324,
 402                         .shift = 0,
 403                         .mask = 0xff,
 404                         .def = 0x04,
 405                 },
 406         }, {
 407                 .id = 0x27,
 408                 .name = "mpcorer",
 409                 .swgroup = TEGRA_SWGROUP_MPCORE,
 410                 .la = {
 411                         .reg = 0x320,
 412                         .shift = 0,
 413                         .mask = 0xff,
 414                         .def = 0x04,
 415                 },
 416         }, {
 417                 .id = 0x28,
 418                 .name = "eppu",
 419                 .swgroup = TEGRA_SWGROUP_EPP,
 420                 .smmu = {
 421                         .reg = 0x22c,
 422                         .bit = 8,
 423                 },
 424                 .la = {
 425                         .reg = 0x300,
 426                         .shift = 16,
 427                         .mask = 0xff,
 428                         .def = 0x33,
 429                 },
 430         }, {
 431                 .id = 0x29,
 432                 .name = "eppv",
 433                 .swgroup = TEGRA_SWGROUP_EPP,
 434                 .smmu = {
 435                         .reg = 0x22c,
 436                         .bit = 9,
 437                 },
 438                 .la = {
 439                         .reg = 0x304,
 440                         .shift = 0,
 441                         .mask = 0xff,
 442                         .def = 0x6c,
 443                 },
 444         }, {
 445                 .id = 0x2a,
 446                 .name = "eppy",
 447                 .swgroup = TEGRA_SWGROUP_EPP,
 448                 .smmu = {
 449                         .reg = 0x22c,
 450                         .bit = 10,
 451                 },
 452                 .la = {
 453                         .reg = 0x304,
 454                         .shift = 16,
 455                         .mask = 0xff,
 456                         .def = 0x6c,
 457                 },
 458         }, {
 459                 .id = 0x2b,
 460                 .name = "msencswr",
 461                 .swgroup = TEGRA_SWGROUP_MSENC,
 462                 .smmu = {
 463                         .reg = 0x22c,
 464                         .bit = 11,
 465                 },
 466                 .la = {
 467                         .reg = 0x328,
 468                         .shift = 16,
 469                         .mask = 0xff,
 470                         .def = 0x80,
 471                 },
 472         }, {
 473                 .id = 0x2c,
 474                 .name = "viwsb",
 475                 .swgroup = TEGRA_SWGROUP_VI,
 476                 .smmu = {
 477                         .reg = 0x22c,
 478                         .bit = 12,
 479                 },
 480                 .la = {
 481                         .reg = 0x364,
 482                         .shift = 0,
 483                         .mask = 0xff,
 484                         .def = 0x47,
 485                 },
 486         }, {
 487                 .id = 0x2d,
 488                 .name = "viwu",
 489                 .swgroup = TEGRA_SWGROUP_VI,
 490                 .smmu = {
 491                         .reg = 0x22c,
 492                         .bit = 13,
 493                 },
 494                 .la = {
 495                         .reg = 0x368,
 496                         .shift = 0,
 497                         .mask = 0xff,
 498                         .def = 0xff,
 499                 },
 500         }, {
 501                 .id = 0x2e,
 502                 .name = "viwv",
 503                 .swgroup = TEGRA_SWGROUP_VI,
 504                 .smmu = {
 505                         .reg = 0x22c,
 506                         .bit = 14,
 507                 },
 508                 .la = {
 509                         .reg = 0x368,
 510                         .shift = 16,
 511                         .mask = 0xff,
 512                         .def = 0xff,
 513                 },
 514         }, {
 515                 .id = 0x2f,
 516                 .name = "viwy",
 517                 .swgroup = TEGRA_SWGROUP_VI,
 518                 .smmu = {
 519                         .reg = 0x22c,
 520                         .bit = 15,
 521                 },
 522                 .la = {
 523                         .reg = 0x36c,
 524                         .shift = 0,
 525                         .mask = 0xff,
 526                         .def = 0x47,
 527                 },
 528         }, {
 529                 .id = 0x30,
 530                 .name = "g2dw",
 531                 .swgroup = TEGRA_SWGROUP_G2,
 532                 .smmu = {
 533                         .reg = 0x22c,
 534                         .bit = 16,
 535                 },
 536                 .la = {
 537                         .reg = 0x30c,
 538                         .shift = 16,
 539                         .mask = 0xff,
 540                         .def = 0x9,
 541                 },
 542         }, {
 543                 .id = 0x32,
 544                 .name = "avpcarm7w",
 545                 .swgroup = TEGRA_SWGROUP_AVPC,
 546                 .smmu = {
 547                         .reg = 0x22c,
 548                         .bit = 18,
 549                 },
 550                 .la = {
 551                         .reg = 0x2e4,
 552                         .shift = 16,
 553                         .mask = 0xff,
 554                         .def = 0x0e,
 555                 },
 556         }, {
 557                 .id = 0x33,
 558                 .name = "fdcdwr",
 559                 .swgroup = TEGRA_SWGROUP_NV,
 560                 .smmu = {
 561                         .reg = 0x22c,
 562                         .bit = 19,
 563                 },
 564                 .la = {
 565                         .reg = 0x338,
 566                         .shift = 16,
 567                         .mask = 0xff,
 568                         .def = 0x10,
 569                 },
 570         }, {
 571                 .id = 0x34,
 572                 .name = "fdcdwr2",
 573                 .swgroup = TEGRA_SWGROUP_NV,
 574                 .smmu = {
 575                         .reg = 0x22c,
 576                         .bit = 20,
 577                 },
 578                 .la = {
 579                         .reg = 0x340,
 580                         .shift = 0,
 581                         .mask = 0xff,
 582                         .def = 0x10,
 583                 },
 584         }, {
 585                 .id = 0x35,
 586                 .name = "hdaw",
 587                 .swgroup = TEGRA_SWGROUP_HDA,
 588                 .smmu = {
 589                         .reg = 0x22c,
 590                         .bit = 21,
 591                 },
 592                 .la = {
 593                         .reg = 0x318,
 594                         .shift = 16,
 595                         .mask = 0xff,
 596                         .def = 0xff,
 597                 },
 598         }, {
 599                 .id = 0x36,
 600                 .name = "host1xw",
 601                 .swgroup = TEGRA_SWGROUP_HC,
 602                 .smmu = {
 603                         .reg = 0x22c,
 604                         .bit = 22,
 605                 },
 606                 .la = {
 607                         .reg = 0x314,
 608                         .shift = 0,
 609                         .mask = 0xff,
 610                         .def = 0x25,
 611                 },
 612         }, {
 613                 .id = 0x37,
 614                 .name = "ispw",
 615                 .swgroup = TEGRA_SWGROUP_ISP,
 616                 .smmu = {
 617                         .reg = 0x22c,
 618                         .bit = 23,
 619                 },
 620                 .la = {
 621                         .reg = 0x31c,
 622                         .shift = 0,
 623                         .mask = 0xff,
 624                         .def = 0xff,
 625                 },
 626         }, {
 627                 .id = 0x38,
 628                 .name = "mpcorelpw",
 629                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 630                 .la = {
 631                         .reg = 0x324,
 632                         .shift = 16,
 633                         .mask = 0xff,
 634                         .def = 0x80,
 635                 },
 636         }, {
 637                 .id = 0x39,
 638                 .name = "mpcorew",
 639                 .swgroup = TEGRA_SWGROUP_MPCORE,
 640                 .la = {
 641                         .reg = 0x320,
 642                         .shift = 16,
 643                         .mask = 0xff,
 644                         .def = 0x0e,
 645                 },
 646         }, {
 647                 .id = 0x3b,
 648                 .name = "ppcsahbdmaw",
 649                 .swgroup = TEGRA_SWGROUP_PPCS,
 650                 .smmu = {
 651                         .reg = 0x22c,
 652                         .bit = 27,
 653                 },
 654                 .la = {
 655                         .reg = 0x348,
 656                         .shift = 0,
 657                         .mask = 0xff,
 658                         .def = 0xa5,
 659                 },
 660         }, {
 661                 .id = 0x3c,
 662                 .name = "ppcsahbslvw",
 663                 .swgroup = TEGRA_SWGROUP_PPCS,
 664                 .smmu = {
 665                         .reg = 0x22c,
 666                         .bit = 28,
 667                 },
 668                 .la = {
 669                         .reg = 0x348,
 670                         .shift = 16,
 671                         .mask = 0xff,
 672                         .def = 0xe8,
 673                 },
 674         }, {
 675                 .id = 0x3e,
 676                 .name = "vdebsevw",
 677                 .swgroup = TEGRA_SWGROUP_VDE,
 678                 .smmu = {
 679                         .reg = 0x22c,
 680                         .bit = 30,
 681                 },
 682                 .la = {
 683                         .reg = 0x35c,
 684                         .shift = 0,
 685                         .mask = 0xff,
 686                         .def = 0xff,
 687                 },
 688         }, {
 689                 .id = 0x3f,
 690                 .name = "vdedbgw",
 691                 .swgroup = TEGRA_SWGROUP_VDE,
 692                 .smmu = {
 693                         .reg = 0x22c,
 694                         .bit = 31,
 695                 },
 696                 .la = {
 697                         .reg = 0x35c,
 698                         .shift = 16,
 699                         .mask = 0xff,
 700                         .def = 0xff,
 701                 },
 702         }, {
 703                 .id = 0x40,
 704                 .name = "vdembew",
 705                 .swgroup = TEGRA_SWGROUP_VDE,
 706                 .smmu = {
 707                         .reg = 0x230,
 708                         .bit = 0,
 709                 },
 710                 .la = {
 711                         .reg = 0x360,
 712                         .shift = 0,
 713                         .mask = 0xff,
 714                         .def = 0x89,
 715                 },
 716         }, {
 717                 .id = 0x41,
 718                 .name = "vdetpmw",
 719                 .swgroup = TEGRA_SWGROUP_VDE,
 720                 .smmu = {
 721                         .reg = 0x230,
 722                         .bit = 1,
 723                 },
 724                 .la = {
 725                         .reg = 0x360,
 726                         .shift = 16,
 727                         .mask = 0xff,
 728                         .def = 0x59,
 729                 },
 730         }, {
 731                 .id = 0x4a,
 732                 .name = "xusb_hostr",
 733                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 734                 .smmu = {
 735                         .reg = 0x230,
 736                         .bit = 10,
 737                 },
 738                 .la = {
 739                         .reg = 0x37c,
 740                         .shift = 0,
 741                         .mask = 0xff,
 742                         .def = 0xa5,
 743                 },
 744         }, {
 745                 .id = 0x4b,
 746                 .name = "xusb_hostw",
 747                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 748                 .smmu = {
 749                         .reg = 0x230,
 750                         .bit = 11,
 751                 },
 752                 .la = {
 753                         .reg = 0x37c,
 754                         .shift = 16,
 755                         .mask = 0xff,
 756                         .def = 0xa5,
 757                 },
 758         }, {
 759                 .id = 0x4c,
 760                 .name = "xusb_devr",
 761                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 762                 .smmu = {
 763                         .reg = 0x230,
 764                         .bit = 12,
 765                 },
 766                 .la = {
 767                         .reg = 0x380,
 768                         .shift = 0,
 769                         .mask = 0xff,
 770                         .def = 0xa5,
 771                 },
 772         }, {
 773                 .id = 0x4d,
 774                 .name = "xusb_devw",
 775                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 776                 .smmu = {
 777                         .reg = 0x230,
 778                         .bit = 13,
 779                 },
 780                 .la = {
 781                         .reg = 0x380,
 782                         .shift = 16,
 783                         .mask = 0xff,
 784                         .def = 0xa5,
 785                 },
 786         }, {
 787                 .id = 0x4e,
 788                 .name = "fdcdwr3",
 789                 .swgroup = TEGRA_SWGROUP_NV,
 790                 .smmu = {
 791                         .reg = 0x230,
 792                         .bit = 14,
 793                 },
 794                 .la = {
 795                         .reg = 0x388,
 796                         .shift = 0,
 797                         .mask = 0xff,
 798                         .def = 0x10,
 799                 },
 800         }, {
 801                 .id = 0x4f,
 802                 .name = "fdcdrd3",
 803                 .swgroup = TEGRA_SWGROUP_NV,
 804                 .smmu = {
 805                         .reg = 0x230,
 806                         .bit = 15,
 807                 },
 808                 .la = {
 809                         .reg = 0x384,
 810                         .shift = 0,
 811                         .mask = 0xff,
 812                         .def = 0x0c,
 813                 },
 814         }, {
 815                 .id = 0x50,
 816                 .name = "fdcwr4",
 817                 .swgroup = TEGRA_SWGROUP_NV,
 818                 .smmu = {
 819                         .reg = 0x230,
 820                         .bit = 16,
 821                 },
 822                 .la = {
 823                         .reg = 0x388,
 824                         .shift = 16,
 825                         .mask = 0xff,
 826                         .def = 0x10,
 827                 },
 828         }, {
 829                 .id = 0x51,
 830                 .name = "fdcrd4",
 831                 .swgroup = TEGRA_SWGROUP_NV,
 832                 .smmu = {
 833                         .reg = 0x230,
 834                         .bit = 17,
 835                 },
 836                 .la = {
 837                         .reg = 0x384,
 838                         .shift = 16,
 839                         .mask = 0xff,
 840                         .def = 0x0c,
 841                 },
 842         }, {
 843                 .id = 0x52,
 844                 .name = "emucifr",
 845                 .swgroup = TEGRA_SWGROUP_EMUCIF,
 846                 .la = {
 847                         .reg = 0x38c,
 848                         .shift = 0,
 849                         .mask = 0xff,
 850                         .def = 0x04,
 851                 },
 852         }, {
 853                 .id = 0x53,
 854                 .name = "emucifw",
 855                 .swgroup = TEGRA_SWGROUP_EMUCIF,
 856                 .la = {
 857                         .reg = 0x38c,
 858                         .shift = 16,
 859                         .mask = 0xff,
 860                         .def = 0x0e,
 861                 },
 862         }, {
 863                 .id = 0x54,
 864                 .name = "tsecsrd",
 865                 .swgroup = TEGRA_SWGROUP_TSEC,
 866                 .smmu = {
 867                         .reg = 0x230,
 868                         .bit = 20,
 869                 },
 870                 .la = {
 871                         .reg = 0x390,
 872                         .shift = 0,
 873                         .mask = 0xff,
 874                         .def = 0x50,
 875                 },
 876         }, {
 877                 .id = 0x55,
 878                 .name = "tsecswr",
 879                 .swgroup = TEGRA_SWGROUP_TSEC,
 880                 .smmu = {
 881                         .reg = 0x230,
 882                         .bit = 21,
 883                 },
 884                 .la = {
 885                         .reg = 0x390,
 886                         .shift = 16,
 887                         .mask = 0xff,
 888                         .def = 0x50,
 889                 },
 890         },
 891 };
 892
 893 static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
 894         { .name = "dc",        .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },
 895         { .name = "dcb",       .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },
 896         { .name = "epp",       .swgroup = TEGRA_SWGROUP_EPP,       .reg = 0x248 },
 897         { .name = "g2",        .swgroup = TEGRA_SWGROUP_G2,        .reg = 0x24c },
 898         { .name = "avpc",      .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },
 899         { .name = "nv",        .swgroup = TEGRA_SWGROUP_NV,        .reg = 0x268 },
 900         { .name = "hda",       .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },
 901         { .name = "hc",        .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },
 902         { .name = "msenc",     .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },
 903         { .name = "ppcs",      .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },
 904         { .name = "vde",       .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },
 905         { .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
 906         { .name = "isp",       .swgroup = TEGRA_SWGROUP_ISP,       .reg = 0x258 },
 907         { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
 908         { .name = "xusb_dev",  .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },
 909         { .name = "tsec",      .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },
 910 };
 911
 912 static const unsigned int tegra114_group_display[] = {
 913         TEGRA_SWGROUP_DC,
 914         TEGRA_SWGROUP_DCB,
 915 };
 916
 917 static const struct tegra_smmu_group_soc tegra114_groups[] = {
 918         {
 919                 .name = "display",
 920                 .swgroups = tegra114_group_display,
 921                 .num_swgroups = ARRAY_SIZE(tegra114_group_display),
 922         },
 923 };
 924
 925 static const struct tegra_smmu_soc tegra114_smmu_soc = {
 926         .clients = tegra114_mc_clients,
 927         .num_clients = ARRAY_SIZE(tegra114_mc_clients),
 928         .swgroups = tegra114_swgroups,
 929         .num_swgroups = ARRAY_SIZE(tegra114_swgroups),
 930         .groups = tegra114_groups,
 931         .num_groups = ARRAY_SIZE(tegra114_groups),
 932         .supports_round_robin_arbitration = false,
 933         .supports_request_limit = false,
 934         .num_tlb_lines = 32,
 935         .num_asids = 4,
 936 };
 937
 938 #define TEGRA114_MC_RESET(_name, _control, _status, _bit)       \
 939         {                                                       \
 940                 .name = #_name,                                 \
 941                 .id = TEGRA114_MC_RESET_##_name,                \
 942                 .control = _control,                            \
 943                 .status = _status,                              \
 944                 .bit = _bit,                                    \
 945         }
 946
 947 static const struct tegra_mc_reset tegra114_mc_resets[] = {
 948         TEGRA114_MC_RESET(AVPC,     0x200, 0x204,  1),
 949         TEGRA114_MC_RESET(DC,       0x200, 0x204,  2),
 950         TEGRA114_MC_RESET(DCB,      0x200, 0x204,  3),
 951         TEGRA114_MC_RESET(EPP,      0x200, 0x204,  4),
 952         TEGRA114_MC_RESET(2D,       0x200, 0x204,  5),
 953         TEGRA114_MC_RESET(HC,       0x200, 0x204,  6),
 954         TEGRA114_MC_RESET(HDA,      0x200, 0x204,  7),
 955         TEGRA114_MC_RESET(ISP,      0x200, 0x204,  8),
 956         TEGRA114_MC_RESET(MPCORE,   0x200, 0x204,  9),
 957         TEGRA114_MC_RESET(MPCORELP, 0x200, 0x204, 10),
 958         TEGRA114_MC_RESET(MPE,      0x200, 0x204, 11),
 959         TEGRA114_MC_RESET(3D,       0x200, 0x204, 12),
 960         TEGRA114_MC_RESET(3D2,      0x200, 0x204, 13),
 961         TEGRA114_MC_RESET(PPCS,     0x200, 0x204, 14),
 962         TEGRA114_MC_RESET(VDE,      0x200, 0x204, 16),
 963         TEGRA114_MC_RESET(VI,       0x200, 0x204, 17),
 964 };
 965
 966 const struct tegra_mc_soc tegra114_mc_soc = {
 967         .clients = tegra114_mc_clients,
 968         .num_clients = ARRAY_SIZE(tegra114_mc_clients),
 969         .num_address_bits = 32,
 970         .atom_size = 32,
 971         .client_id_mask = 0x7f,
 972         .smmu = &tegra114_smmu_soc,
 973         .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
 974                    MC_INT_DECERR_EMEM,
 975         .reset_ops = &tegra_mc_reset_ops_common,
 976         .resets = tegra114_mc_resets,
 977         .num_resets = ARRAY_SIZE(tegra114_mc_resets),
 978 };