drivers/media/usb/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/module.h>
  25 #include <linux/firmware.h>
  26 #include <linux/videodev2.h>
  27 #include <media/v4l2-common.h>
  28 #include <media/tuner.h>
  29 #include "pvrusb2.h"
  30 #include "pvrusb2-std.h"
  31 #include "pvrusb2-util.h"
  32 #include "pvrusb2-hdw.h"
  33 #include "pvrusb2-i2c-core.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38 #include "pvrusb2-fx2-cmd.h"
  39 #include "pvrusb2-wm8775.h"
  40 #include "pvrusb2-video-v4l.h"
  41 #include "pvrusb2-cx2584x-v4l.h"
  42 #include "pvrusb2-cs53l32a.h"
  43 #include "pvrusb2-audio.h"
  44
  45 #define TV_MIN_FREQ     55250000L
  46 #define TV_MAX_FREQ    850000000L
  47
  48 /* This defines a minimum interval that the decoder must remain quiet
  49    before we are allowed to start it running. */
  50 #define TIME_MSEC_DECODER_WAIT 50
  51
  52 /* This defines a minimum interval that the decoder must be allowed to run
  53    before we can safely begin using its streaming output. */
  54 #define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
  55
  56 /* This defines a minimum interval that the encoder must remain quiet
  57    before we are allowed to configure it. */
  58 #define TIME_MSEC_ENCODER_WAIT 50
  59
  60 /* This defines the minimum interval that the encoder must successfully run
  61    before we consider that the encoder has run at least once since its
  62    firmware has been loaded.  This measurement is in important for cases
  63    where we can't do something until we know that the encoder has been run
  64    at least once. */
  65 #define TIME_MSEC_ENCODER_OK 250
  66
  67 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  68 static DEFINE_MUTEX(pvr2_unit_mtx);
  69
  70 static int ctlchg;
  71 static int procreload;
  72 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  73 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  74 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  75 static int init_pause_msec;
  76
  77 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  78 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  79 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  80 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  81 module_param(procreload, int, S_IRUGO|S_IWUSR);
  82 MODULE_PARM_DESC(procreload,
  83                  "Attempt init failure recovery with firmware reload");
  84 module_param_array(tuner,    int, NULL, 0444);
  85 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  86 module_param_array(video_std,    int, NULL, 0444);
  87 MODULE_PARM_DESC(video_std,"specify initial video standard");
  88 module_param_array(tolerance,    int, NULL, 0444);
  89 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  90
  91 /* US Broadcast channel 3 (61.25 MHz), to help with testing */
  92 static int default_tv_freq    = 61250000L;
  93 /* 104.3 MHz, a usable FM station for my area */
  94 static int default_radio_freq = 104300000L;
  95
  96 module_param_named(tv_freq, default_tv_freq, int, 0444);
  97 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  98 module_param_named(radio_freq, default_radio_freq, int, 0444);
  99 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
 100
 101 #define PVR2_CTL_WRITE_ENDPOINT  0x01
 102 #define PVR2_CTL_READ_ENDPOINT   0x81
 103
 104 #define PVR2_GPIO_IN 0x9008
 105 #define PVR2_GPIO_OUT 0x900c
 106 #define PVR2_GPIO_DIR 0x9020
 107
 108 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 109
 110 #define PVR2_FIRMWARE_ENDPOINT   0x02
 111
 112 /* size of a firmware chunk */
 113 #define FIRMWARE_CHUNK_SIZE 0x2000
 114
 115 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 116                                         struct v4l2_subdev *);
 117
 118 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 119         [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 120         [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 121         [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 122         [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 123         [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
 124 };
 125
 126 static const char *module_names[] = {
 127         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 128         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 129         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 130         [PVR2_CLIENT_ID_TUNER] = "tuner",
 131         [PVR2_CLIENT_ID_DEMOD] = "tuner",
 132         [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
 133         [PVR2_CLIENT_ID_WM8775] = "wm8775",
 134 };
 135
 136
 137 static const unsigned char *module_i2c_addresses[] = {
 138         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 139         [PVR2_CLIENT_ID_DEMOD] = "\x43",
 140         [PVR2_CLIENT_ID_MSP3400] = "\x40",
 141         [PVR2_CLIENT_ID_SAA7115] = "\x21",
 142         [PVR2_CLIENT_ID_WM8775] = "\x1b",
 143         [PVR2_CLIENT_ID_CX25840] = "\x44",
 144         [PVR2_CLIENT_ID_CS53L32A] = "\x11",
 145 };
 146
 147
 148 static const char *ir_scheme_names[] = {
 149         [PVR2_IR_SCHEME_NONE] = "none",
 150         [PVR2_IR_SCHEME_29XXX] = "29xxx",
 151         [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
 152         [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
 153         [PVR2_IR_SCHEME_ZILOG] = "Zilog",
 154 };
 155
 156
 157 /* Define the list of additional controls we'll dynamically construct based
 158    on query of the cx2341x module. */
 159 struct pvr2_mpeg_ids {
 160         const char *strid;
 161         int id;
 162 };
 163 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 164         {
 165                 .strid = "audio_layer",
 166                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 167         },{
 168                 .strid = "audio_bitrate",
 169                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 170         },{
 171                 /* Already using audio_mode elsewhere :-( */
 172                 .strid = "mpeg_audio_mode",
 173                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 174         },{
 175                 .strid = "mpeg_audio_mode_extension",
 176                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 177         },{
 178                 .strid = "audio_emphasis",
 179                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 180         },{
 181                 .strid = "audio_crc",
 182                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 183         },{
 184                 .strid = "video_aspect",
 185                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 186         },{
 187                 .strid = "video_b_frames",
 188                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 189         },{
 190                 .strid = "video_gop_size",
 191                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 192         },{
 193                 .strid = "video_gop_closure",
 194                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 195         },{
 196                 .strid = "video_bitrate_mode",
 197                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 198         },{
 199                 .strid = "video_bitrate",
 200                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 201         },{
 202                 .strid = "video_bitrate_peak",
 203                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 204         },{
 205                 .strid = "video_temporal_decimation",
 206                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 207         },{
 208                 .strid = "stream_type",
 209                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 210         },{
 211                 .strid = "video_spatial_filter_mode",
 212                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 213         },{
 214                 .strid = "video_spatial_filter",
 215                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 216         },{
 217                 .strid = "video_luma_spatial_filter_type",
 218                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 219         },{
 220                 .strid = "video_chroma_spatial_filter_type",
 221                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 222         },{
 223                 .strid = "video_temporal_filter_mode",
 224                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 225         },{
 226                 .strid = "video_temporal_filter",
 227                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 228         },{
 229                 .strid = "video_median_filter_type",
 230                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 231         },{
 232                 .strid = "video_luma_median_filter_top",
 233                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 234         },{
 235                 .strid = "video_luma_median_filter_bottom",
 236                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 237         },{
 238                 .strid = "video_chroma_median_filter_top",
 239                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 240         },{
 241                 .strid = "video_chroma_median_filter_bottom",
 242                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 243         }
 244 };
 245 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 246
 247
 248 static const char *control_values_srate[] = {
 249         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 250         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 251         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 252 };
 253
 254
 255
 256 static const char *control_values_input[] = {
 257         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 258         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 259         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 260         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 261         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 262 };
 263
 264
 265 static const char *control_values_audiomode[] = {
 266         [V4L2_TUNER_MODE_MONO]   = "Mono",
 267         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 268         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 269         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 270         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 271 };
 272
 273
 274 static const char *control_values_hsm[] = {
 275         [PVR2_CVAL_HSM_FAIL] = "Fail",
 276         [PVR2_CVAL_HSM_HIGH] = "High",
 277         [PVR2_CVAL_HSM_FULL] = "Full",
 278 };
 279
 280
 281 static const char *pvr2_state_names[] = {
 282         [PVR2_STATE_NONE] =    "none",
 283         [PVR2_STATE_DEAD] =    "dead",
 284         [PVR2_STATE_COLD] =    "cold",
 285         [PVR2_STATE_WARM] =    "warm",
 286         [PVR2_STATE_ERROR] =   "error",
 287         [PVR2_STATE_READY] =   "ready",
 288         [PVR2_STATE_RUN] =     "run",
 289 };
 290
 291
 292 struct pvr2_fx2cmd_descdef {
 293         unsigned char id;
 294         unsigned char *desc;
 295 };
 296
 297 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 298         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 299         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 300         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 301         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 302         {FX2CMD_REG_WRITE, "write encoder register"},
 303         {FX2CMD_REG_READ, "read encoder register"},
 304         {FX2CMD_MEMSEL, "encoder memsel"},
 305         {FX2CMD_I2C_WRITE, "i2c write"},
 306         {FX2CMD_I2C_READ, "i2c read"},
 307         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 308         {FX2CMD_STREAMING_ON, "stream on"},
 309         {FX2CMD_STREAMING_OFF, "stream off"},
 310         {FX2CMD_FWPOST1, "fwpost1"},
 311         {FX2CMD_POWER_OFF, "power off"},
 312         {FX2CMD_POWER_ON, "power on"},
 313         {FX2CMD_DEEP_RESET, "deep reset"},
 314         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 315         {FX2CMD_GET_IR_CODE, "get IR code"},
 316         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 317         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 318         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 319         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 320         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 321         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 322         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 323 };
 324
 325
 326 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 327 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 328 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 329 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 330 static void pvr2_hdw_worker_poll(struct work_struct *work);
 331 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 332 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 333 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 334 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 335 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 336 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 337 static void pvr2_hdw_quiescent_timeout(unsigned long);
 338 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
 339 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 340 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 341 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 342 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 343                                 unsigned int timeout,int probe_fl,
 344                                 void *write_data,unsigned int write_len,
 345                                 void *read_data,unsigned int read_len);
 346 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 347 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw);
 348
 349 static void trace_stbit(const char *name,int val)
 350 {
 351         pvr2_trace(PVR2_TRACE_STBITS,
 352                    "State bit %s <-- %s",
 353                    name,(val ? "true" : "false"));
 354 }
 355
 356 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 357 {
 358         struct pvr2_hdw *hdw = cptr->hdw;
 359         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 360                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 361         } else {
 362                 *vp = 0;
 363         }
 364         return 0;
 365 }
 366
 367 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 368 {
 369         struct pvr2_hdw *hdw = cptr->hdw;
 370         unsigned int slotId = hdw->freqProgSlot;
 371         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 372                 hdw->freqTable[slotId-1] = v;
 373                 /* Handle side effects correctly - if we're tuned to this
 374                    slot, then forgot the slot id relation since the stored
 375                    frequency has been changed. */
 376                 if (hdw->freqSelector) {
 377                         if (hdw->freqSlotRadio == slotId) {
 378                                 hdw->freqSlotRadio = 0;
 379                         }
 380                 } else {
 381                         if (hdw->freqSlotTelevision == slotId) {
 382                                 hdw->freqSlotTelevision = 0;
 383                         }
 384                 }
 385         }
 386         return 0;
 387 }
 388
 389 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 390 {
 391         *vp = cptr->hdw->freqProgSlot;
 392         return 0;
 393 }
 394
 395 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 396 {
 397         struct pvr2_hdw *hdw = cptr->hdw;
 398         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 399                 hdw->freqProgSlot = v;
 400         }
 401         return 0;
 402 }
 403
 404 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 405 {
 406         struct pvr2_hdw *hdw = cptr->hdw;
 407         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 408         return 0;
 409 }
 410
 411 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 412 {
 413         unsigned freq = 0;
 414         struct pvr2_hdw *hdw = cptr->hdw;
 415         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 416         if (slotId > 0) {
 417                 freq = hdw->freqTable[slotId-1];
 418                 if (!freq) return 0;
 419                 pvr2_hdw_set_cur_freq(hdw,freq);
 420         }
 421         if (hdw->freqSelector) {
 422                 hdw->freqSlotRadio = slotId;
 423         } else {
 424                 hdw->freqSlotTelevision = slotId;
 425         }
 426         return 0;
 427 }
 428
 429 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 430 {
 431         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 432         return 0;
 433 }
 434
 435 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 436 {
 437         return cptr->hdw->freqDirty != 0;
 438 }
 439
 440 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 441 {
 442         cptr->hdw->freqDirty = 0;
 443 }
 444
 445 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 446 {
 447         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 448         return 0;
 449 }
 450
 451 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 452 {
 453         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 454         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 455         if (stat != 0) {
 456                 return stat;
 457         }
 458         *left = cap->bounds.left;
 459         return 0;
 460 }
 461
 462 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 463 {
 464         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 465         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 466         if (stat != 0) {
 467                 return stat;
 468         }
 469         *left = cap->bounds.left;
 470         if (cap->bounds.width > cptr->hdw->cropw_val) {
 471                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 472         }
 473         return 0;
 474 }
 475
 476 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 477 {
 478         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 479         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 480         if (stat != 0) {
 481                 return stat;
 482         }
 483         *top = cap->bounds.top;
 484         return 0;
 485 }
 486
 487 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 488 {
 489         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 490         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 491         if (stat != 0) {
 492                 return stat;
 493         }
 494         *top = cap->bounds.top;
 495         if (cap->bounds.height > cptr->hdw->croph_val) {
 496                 *top += cap->bounds.height - cptr->hdw->croph_val;
 497         }
 498         return 0;
 499 }
 500
 501 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
 502 {
 503         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 504         int stat, bleftend, cleft;
 505
 506         stat = pvr2_hdw_check_cropcap(cptr->hdw);
 507         if (stat != 0) {
 508                 return stat;
 509         }
 510         bleftend = cap->bounds.left+cap->bounds.width;
 511         cleft = cptr->hdw->cropl_val;
 512
 513         *width = cleft < bleftend ? bleftend-cleft : 0;
 514         return 0;
 515 }
 516
 517 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
 518 {
 519         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 520         int stat, btopend, ctop;
 521
 522         stat = pvr2_hdw_check_cropcap(cptr->hdw);
 523         if (stat != 0) {
 524                 return stat;
 525         }
 526         btopend = cap->bounds.top+cap->bounds.height;
 527         ctop = cptr->hdw->cropt_val;
 528
 529         *height = ctop < btopend ? btopend-ctop : 0;
 530         return 0;
 531 }
 532
 533 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 534 {
 535         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 536         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 537         if (stat != 0) {
 538                 return stat;
 539         }
 540         *val = cap->bounds.left;
 541         return 0;
 542 }
 543
 544 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 545 {
 546         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 547         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 548         if (stat != 0) {
 549                 return stat;
 550         }
 551         *val = cap->bounds.top;
 552         return 0;
 553 }
 554
 555 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 556 {
 557         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 558         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 559         if (stat != 0) {
 560                 return stat;
 561         }
 562         *val = cap->bounds.width;
 563         return 0;
 564 }
 565
 566 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 567 {
 568         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 569         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 570         if (stat != 0) {
 571                 return stat;
 572         }
 573         *val = cap->bounds.height;
 574         return 0;
 575 }
 576
 577 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 578 {
 579         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 580         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 581         if (stat != 0) {
 582                 return stat;
 583         }
 584         *val = cap->defrect.left;
 585         return 0;
 586 }
 587
 588 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 589 {
 590         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 591         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 592         if (stat != 0) {
 593                 return stat;
 594         }
 595         *val = cap->defrect.top;
 596         return 0;
 597 }
 598
 599 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 600 {
 601         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 602         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 603         if (stat != 0) {
 604                 return stat;
 605         }
 606         *val = cap->defrect.width;
 607         return 0;
 608 }
 609
 610 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 611 {
 612         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 613         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 614         if (stat != 0) {
 615                 return stat;
 616         }
 617         *val = cap->defrect.height;
 618         return 0;
 619 }
 620
 621 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 622 {
 623         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 624         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 625         if (stat != 0) {
 626                 return stat;
 627         }
 628         *val = cap->pixelaspect.numerator;
 629         return 0;
 630 }
 631
 632 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 633 {
 634         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 635         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 636         if (stat != 0) {
 637                 return stat;
 638         }
 639         *val = cap->pixelaspect.denominator;
 640         return 0;
 641 }
 642
 643 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 644 {
 645         /* Actual maximum depends on the video standard in effect. */
 646         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 647                 *vp = 480;
 648         } else {
 649                 *vp = 576;
 650         }
 651         return 0;
 652 }
 653
 654 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 655 {
 656         /* Actual minimum depends on device digitizer type. */
 657         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 658                 *vp = 75;
 659         } else {
 660                 *vp = 17;
 661         }
 662         return 0;
 663 }
 664
 665 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 666 {
 667         *vp = cptr->hdw->input_val;
 668         return 0;
 669 }
 670
 671 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 672 {
 673         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 674 }
 675
 676 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 677 {
 678         return pvr2_hdw_set_input(cptr->hdw,v);
 679 }
 680
 681 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 682 {
 683         return cptr->hdw->input_dirty != 0;
 684 }
 685
 686 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 687 {
 688         cptr->hdw->input_dirty = 0;
 689 }
 690
 691
 692 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 693 {
 694         unsigned long fv;
 695         struct pvr2_hdw *hdw = cptr->hdw;
 696         if (hdw->tuner_signal_stale) {
 697                 pvr2_hdw_status_poll(hdw);
 698         }
 699         fv = hdw->tuner_signal_info.rangehigh;
 700         if (!fv) {
 701                 /* Safety fallback */
 702                 *vp = TV_MAX_FREQ;
 703                 return 0;
 704         }
 705         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 706                 fv = (fv * 125) / 2;
 707         } else {
 708                 fv = fv * 62500;
 709         }
 710         *vp = fv;
 711         return 0;
 712 }
 713
 714 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 715 {
 716         unsigned long fv;
 717         struct pvr2_hdw *hdw = cptr->hdw;
 718         if (hdw->tuner_signal_stale) {
 719                 pvr2_hdw_status_poll(hdw);
 720         }
 721         fv = hdw->tuner_signal_info.rangelow;
 722         if (!fv) {
 723                 /* Safety fallback */
 724                 *vp = TV_MIN_FREQ;
 725                 return 0;
 726         }
 727         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 728                 fv = (fv * 125) / 2;
 729         } else {
 730                 fv = fv * 62500;
 731         }
 732         *vp = fv;
 733         return 0;
 734 }
 735
 736 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 737 {
 738         return cptr->hdw->enc_stale != 0;
 739 }
 740
 741 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 742 {
 743         cptr->hdw->enc_stale = 0;
 744         cptr->hdw->enc_unsafe_stale = 0;
 745 }
 746
 747 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 748 {
 749         int ret;
 750         struct v4l2_ext_controls cs;
 751         struct v4l2_ext_control c1;
 752         memset(&cs,0,sizeof(cs));
 753         memset(&c1,0,sizeof(c1));
 754         cs.controls = &c1;
 755         cs.count = 1;
 756         c1.id = cptr->info->v4l_id;
 757         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 758                                 VIDIOC_G_EXT_CTRLS);
 759         if (ret) return ret;
 760         *vp = c1.value;
 761         return 0;
 762 }
 763
 764 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 765 {
 766         int ret;
 767         struct pvr2_hdw *hdw = cptr->hdw;
 768         struct v4l2_ext_controls cs;
 769         struct v4l2_ext_control c1;
 770         memset(&cs,0,sizeof(cs));
 771         memset(&c1,0,sizeof(c1));
 772         cs.controls = &c1;
 773         cs.count = 1;
 774         c1.id = cptr->info->v4l_id;
 775         c1.value = v;
 776         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 777                                 hdw->state_encoder_run, &cs,
 778                                 VIDIOC_S_EXT_CTRLS);
 779         if (ret == -EBUSY) {
 780                 /* Oops.  cx2341x is telling us it's not safe to change
 781                    this control while we're capturing.  Make a note of this
 782                    fact so that the pipeline will be stopped the next time
 783                    controls are committed.  Then go on ahead and store this
 784                    change anyway. */
 785                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 786                                         0, &cs,
 787                                         VIDIOC_S_EXT_CTRLS);
 788                 if (!ret) hdw->enc_unsafe_stale = !0;
 789         }
 790         if (ret) return ret;
 791         hdw->enc_stale = !0;
 792         return 0;
 793 }
 794
 795 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 796 {
 797         struct v4l2_queryctrl qctrl;
 798         struct pvr2_ctl_info *info;
 799         qctrl.id = cptr->info->v4l_id;
 800         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 801         /* Strip out the const so we can adjust a function pointer.  It's
 802            OK to do this here because we know this is a dynamically created
 803            control, so the underlying storage for the info pointer is (a)
 804            private to us, and (b) not in read-only storage.  Either we do
 805            this or we significantly complicate the underlying control
 806            implementation. */
 807         info = (struct pvr2_ctl_info *)(cptr->info);
 808         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 809                 if (info->set_value) {
 810                         info->set_value = NULL;
 811                 }
 812         } else {
 813                 if (!(info->set_value)) {
 814                         info->set_value = ctrl_cx2341x_set;
 815                 }
 816         }
 817         return qctrl.flags;
 818 }
 819
 820 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 821 {
 822         *vp = cptr->hdw->state_pipeline_req;
 823         return 0;
 824 }
 825
 826 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 827 {
 828         *vp = cptr->hdw->master_state;
 829         return 0;
 830 }
 831
 832 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 833 {
 834         int result = pvr2_hdw_is_hsm(cptr->hdw);
 835         *vp = PVR2_CVAL_HSM_FULL;
 836         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 837         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 838         return 0;
 839 }
 840
 841 static int ctrl_stddetect_get(struct pvr2_ctrl *cptr, int *vp)
 842 {
 843         *vp = pvr2_hdw_get_detected_std(cptr->hdw);
 844         return 0;
 845 }
 846
 847 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 848 {
 849         *vp = cptr->hdw->std_mask_avail;
 850         return 0;
 851 }
 852
 853 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 854 {
 855         struct pvr2_hdw *hdw = cptr->hdw;
 856         v4l2_std_id ns;
 857         ns = hdw->std_mask_avail;
 858         ns = (ns & ~m) | (v & m);
 859         if (ns == hdw->std_mask_avail) return 0;
 860         hdw->std_mask_avail = ns;
 861         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
 862         return 0;
 863 }
 864
 865 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 866                                char *bufPtr,unsigned int bufSize,
 867                                unsigned int *len)
 868 {
 869         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 870         return 0;
 871 }
 872
 873 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 874                                const char *bufPtr,unsigned int bufSize,
 875                                int *mskp,int *valp)
 876 {
 877         int ret;
 878         v4l2_std_id id;
 879         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 880         if (ret < 0) return ret;
 881         if (mskp) *mskp = id;
 882         if (valp) *valp = id;
 883         return 0;
 884 }
 885
 886 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 887 {
 888         *vp = cptr->hdw->std_mask_cur;
 889         return 0;
 890 }
 891
 892 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 893 {
 894         struct pvr2_hdw *hdw = cptr->hdw;
 895         v4l2_std_id ns;
 896         ns = hdw->std_mask_cur;
 897         ns = (ns & ~m) | (v & m);
 898         if (ns == hdw->std_mask_cur) return 0;
 899         hdw->std_mask_cur = ns;
 900         hdw->std_dirty = !0;
 901         return 0;
 902 }
 903
 904 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 905 {
 906         return cptr->hdw->std_dirty != 0;
 907 }
 908
 909 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 910 {
 911         cptr->hdw->std_dirty = 0;
 912 }
 913
 914 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 915 {
 916         struct pvr2_hdw *hdw = cptr->hdw;
 917         pvr2_hdw_status_poll(hdw);
 918         *vp = hdw->tuner_signal_info.signal;
 919         return 0;
 920 }
 921
 922 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 923 {
 924         int val = 0;
 925         unsigned int subchan;
 926         struct pvr2_hdw *hdw = cptr->hdw;
 927         pvr2_hdw_status_poll(hdw);
 928         subchan = hdw->tuner_signal_info.rxsubchans;
 929         if (subchan & V4L2_TUNER_SUB_MONO) {
 930                 val |= (1 << V4L2_TUNER_MODE_MONO);
 931         }
 932         if (subchan & V4L2_TUNER_SUB_STEREO) {
 933                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 934         }
 935         if (subchan & V4L2_TUNER_SUB_LANG1) {
 936                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 937         }
 938         if (subchan & V4L2_TUNER_SUB_LANG2) {
 939                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 940         }
 941         *vp = val;
 942         return 0;
 943 }
 944
 945
 946 #define DEFINT(vmin,vmax) \
 947         .type = pvr2_ctl_int, \
 948         .def.type_int.min_value = vmin, \
 949         .def.type_int.max_value = vmax
 950
 951 #define DEFENUM(tab) \
 952         .type = pvr2_ctl_enum, \
 953         .def.type_enum.count = ARRAY_SIZE(tab), \
 954         .def.type_enum.value_names = tab
 955
 956 #define DEFBOOL \
 957         .type = pvr2_ctl_bool
 958
 959 #define DEFMASK(msk,tab) \
 960         .type = pvr2_ctl_bitmask, \
 961         .def.type_bitmask.valid_bits = msk, \
 962         .def.type_bitmask.bit_names = tab
 963
 964 #define DEFREF(vname) \
 965         .set_value = ctrl_set_##vname, \
 966         .get_value = ctrl_get_##vname, \
 967         .is_dirty = ctrl_isdirty_##vname, \
 968         .clear_dirty = ctrl_cleardirty_##vname
 969
 970
 971 #define VCREATE_FUNCS(vname) \
 972 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 973 {*vp = cptr->hdw->vname##_val; return 0;} \
 974 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 975 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 976 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 977 {return cptr->hdw->vname##_dirty != 0;} \
 978 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 979 {cptr->hdw->vname##_dirty = 0;}
 980
 981 VCREATE_FUNCS(brightness)
 982 VCREATE_FUNCS(contrast)
 983 VCREATE_FUNCS(saturation)
 984 VCREATE_FUNCS(hue)
 985 VCREATE_FUNCS(volume)
 986 VCREATE_FUNCS(balance)
 987 VCREATE_FUNCS(bass)
 988 VCREATE_FUNCS(treble)
 989 VCREATE_FUNCS(mute)
 990 VCREATE_FUNCS(cropl)
 991 VCREATE_FUNCS(cropt)
 992 VCREATE_FUNCS(cropw)
 993 VCREATE_FUNCS(croph)
 994 VCREATE_FUNCS(audiomode)
 995 VCREATE_FUNCS(res_hor)
 996 VCREATE_FUNCS(res_ver)
 997 VCREATE_FUNCS(srate)
 998
 999 /* Table definition of all controls which can be manipulated */
1000 static const struct pvr2_ctl_info control_defs[] = {
1001         {
1002                 .v4l_id = V4L2_CID_BRIGHTNESS,
1003                 .desc = "Brightness",
1004                 .name = "brightness",
1005                 .default_value = 128,
1006                 DEFREF(brightness),
1007                 DEFINT(0,255),
1008         },{
1009                 .v4l_id = V4L2_CID_CONTRAST,
1010                 .desc = "Contrast",
1011                 .name = "contrast",
1012                 .default_value = 68,
1013                 DEFREF(contrast),
1014                 DEFINT(0,127),
1015         },{
1016                 .v4l_id = V4L2_CID_SATURATION,
1017                 .desc = "Saturation",
1018                 .name = "saturation",
1019                 .default_value = 64,
1020                 DEFREF(saturation),
1021                 DEFINT(0,127),
1022         },{
1023                 .v4l_id = V4L2_CID_HUE,
1024                 .desc = "Hue",
1025                 .name = "hue",
1026                 .default_value = 0,
1027                 DEFREF(hue),
1028                 DEFINT(-128,127),
1029         },{
1030                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1031                 .desc = "Volume",
1032                 .name = "volume",
1033                 .default_value = 62000,
1034                 DEFREF(volume),
1035                 DEFINT(0,65535),
1036         },{
1037                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1038                 .desc = "Balance",
1039                 .name = "balance",
1040                 .default_value = 0,
1041                 DEFREF(balance),
1042                 DEFINT(-32768,32767),
1043         },{
1044                 .v4l_id = V4L2_CID_AUDIO_BASS,
1045                 .desc = "Bass",
1046                 .name = "bass",
1047                 .default_value = 0,
1048                 DEFREF(bass),
1049                 DEFINT(-32768,32767),
1050         },{
1051                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1052                 .desc = "Treble",
1053                 .name = "treble",
1054                 .default_value = 0,
1055                 DEFREF(treble),
1056                 DEFINT(-32768,32767),
1057         },{
1058                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1059                 .desc = "Mute",
1060                 .name = "mute",
1061                 .default_value = 0,
1062                 DEFREF(mute),
1063                 DEFBOOL,
1064         }, {
1065                 .desc = "Capture crop left margin",
1066                 .name = "crop_left",
1067                 .internal_id = PVR2_CID_CROPL,
1068                 .default_value = 0,
1069                 DEFREF(cropl),
1070                 DEFINT(-129, 340),
1071                 .get_min_value = ctrl_cropl_min_get,
1072                 .get_max_value = ctrl_cropl_max_get,
1073                 .get_def_value = ctrl_get_cropcapdl,
1074         }, {
1075                 .desc = "Capture crop top margin",
1076                 .name = "crop_top",
1077                 .internal_id = PVR2_CID_CROPT,
1078                 .default_value = 0,
1079                 DEFREF(cropt),
1080                 DEFINT(-35, 544),
1081                 .get_min_value = ctrl_cropt_min_get,
1082                 .get_max_value = ctrl_cropt_max_get,
1083                 .get_def_value = ctrl_get_cropcapdt,
1084         }, {
1085                 .desc = "Capture crop width",
1086                 .name = "crop_width",
1087                 .internal_id = PVR2_CID_CROPW,
1088                 .default_value = 720,
1089                 DEFREF(cropw),
1090                 DEFINT(0, 864),
1091                 .get_max_value = ctrl_cropw_max_get,
1092                 .get_def_value = ctrl_get_cropcapdw,
1093         }, {
1094                 .desc = "Capture crop height",
1095                 .name = "crop_height",
1096                 .internal_id = PVR2_CID_CROPH,
1097                 .default_value = 480,
1098                 DEFREF(croph),
1099                 DEFINT(0, 576),
1100                 .get_max_value = ctrl_croph_max_get,
1101                 .get_def_value = ctrl_get_cropcapdh,
1102         }, {
1103                 .desc = "Capture capability pixel aspect numerator",
1104                 .name = "cropcap_pixel_numerator",
1105                 .internal_id = PVR2_CID_CROPCAPPAN,
1106                 .get_value = ctrl_get_cropcappan,
1107         }, {
1108                 .desc = "Capture capability pixel aspect denominator",
1109                 .name = "cropcap_pixel_denominator",
1110                 .internal_id = PVR2_CID_CROPCAPPAD,
1111                 .get_value = ctrl_get_cropcappad,
1112         }, {
1113                 .desc = "Capture capability bounds top",
1114                 .name = "cropcap_bounds_top",
1115                 .internal_id = PVR2_CID_CROPCAPBT,
1116                 .get_value = ctrl_get_cropcapbt,
1117         }, {
1118                 .desc = "Capture capability bounds left",
1119                 .name = "cropcap_bounds_left",
1120                 .internal_id = PVR2_CID_CROPCAPBL,
1121                 .get_value = ctrl_get_cropcapbl,
1122         }, {
1123                 .desc = "Capture capability bounds width",
1124                 .name = "cropcap_bounds_width",
1125                 .internal_id = PVR2_CID_CROPCAPBW,
1126                 .get_value = ctrl_get_cropcapbw,
1127         }, {
1128                 .desc = "Capture capability bounds height",
1129                 .name = "cropcap_bounds_height",
1130                 .internal_id = PVR2_CID_CROPCAPBH,
1131                 .get_value = ctrl_get_cropcapbh,
1132         },{
1133                 .desc = "Video Source",
1134                 .name = "input",
1135                 .internal_id = PVR2_CID_INPUT,
1136                 .default_value = PVR2_CVAL_INPUT_TV,
1137                 .check_value = ctrl_check_input,
1138                 DEFREF(input),
1139                 DEFENUM(control_values_input),
1140         },{
1141                 .desc = "Audio Mode",
1142                 .name = "audio_mode",
1143                 .internal_id = PVR2_CID_AUDIOMODE,
1144                 .default_value = V4L2_TUNER_MODE_STEREO,
1145                 DEFREF(audiomode),
1146                 DEFENUM(control_values_audiomode),
1147         },{
1148                 .desc = "Horizontal capture resolution",
1149                 .name = "resolution_hor",
1150                 .internal_id = PVR2_CID_HRES,
1151                 .default_value = 720,
1152                 DEFREF(res_hor),
1153                 DEFINT(19,720),
1154         },{
1155                 .desc = "Vertical capture resolution",
1156                 .name = "resolution_ver",
1157                 .internal_id = PVR2_CID_VRES,
1158                 .default_value = 480,
1159                 DEFREF(res_ver),
1160                 DEFINT(17,576),
1161                 /* Hook in check for video standard and adjust maximum
1162                    depending on the standard. */
1163                 .get_max_value = ctrl_vres_max_get,
1164                 .get_min_value = ctrl_vres_min_get,
1165         },{
1166                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1167                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1168                 .desc = "Audio Sampling Frequency",
1169                 .name = "srate",
1170                 DEFREF(srate),
1171                 DEFENUM(control_values_srate),
1172         },{
1173                 .desc = "Tuner Frequency (Hz)",
1174                 .name = "frequency",
1175                 .internal_id = PVR2_CID_FREQUENCY,
1176                 .default_value = 0,
1177                 .set_value = ctrl_freq_set,
1178                 .get_value = ctrl_freq_get,
1179                 .is_dirty = ctrl_freq_is_dirty,
1180                 .clear_dirty = ctrl_freq_clear_dirty,
1181                 DEFINT(0,0),
1182                 /* Hook in check for input value (tv/radio) and adjust
1183                    max/min values accordingly */
1184                 .get_max_value = ctrl_freq_max_get,
1185                 .get_min_value = ctrl_freq_min_get,
1186         },{
1187                 .desc = "Channel",
1188                 .name = "channel",
1189                 .set_value = ctrl_channel_set,
1190                 .get_value = ctrl_channel_get,
1191                 DEFINT(0,FREQTABLE_SIZE),
1192         },{
1193                 .desc = "Channel Program Frequency",
1194                 .name = "freq_table_value",
1195                 .set_value = ctrl_channelfreq_set,
1196                 .get_value = ctrl_channelfreq_get,
1197                 DEFINT(0,0),
1198                 /* Hook in check for input value (tv/radio) and adjust
1199                    max/min values accordingly */
1200                 .get_max_value = ctrl_freq_max_get,
1201                 .get_min_value = ctrl_freq_min_get,
1202         },{
1203                 .desc = "Channel Program ID",
1204                 .name = "freq_table_channel",
1205                 .set_value = ctrl_channelprog_set,
1206                 .get_value = ctrl_channelprog_get,
1207                 DEFINT(0,FREQTABLE_SIZE),
1208         },{
1209                 .desc = "Streaming Enabled",
1210                 .name = "streaming_enabled",
1211                 .get_value = ctrl_streamingenabled_get,
1212                 DEFBOOL,
1213         },{
1214                 .desc = "USB Speed",
1215                 .name = "usb_speed",
1216                 .get_value = ctrl_hsm_get,
1217                 DEFENUM(control_values_hsm),
1218         },{
1219                 .desc = "Master State",
1220                 .name = "master_state",
1221                 .get_value = ctrl_masterstate_get,
1222                 DEFENUM(pvr2_state_names),
1223         },{
1224                 .desc = "Signal Present",
1225                 .name = "signal_present",
1226                 .get_value = ctrl_signal_get,
1227                 DEFINT(0,65535),
1228         },{
1229                 .desc = "Audio Modes Present",
1230                 .name = "audio_modes_present",
1231                 .get_value = ctrl_audio_modes_present_get,
1232                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1233                    v4l.  Nothing outside of this module cares about this,
1234                    but I reuse it in order to also reuse the
1235                    control_values_audiomode string table. */
1236                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1237                          (1 << V4L2_TUNER_MODE_STEREO)|
1238                          (1 << V4L2_TUNER_MODE_LANG1)|
1239                          (1 << V4L2_TUNER_MODE_LANG2)),
1240                         control_values_audiomode),
1241         },{
1242                 .desc = "Video Standards Available Mask",
1243                 .name = "video_standard_mask_available",
1244                 .internal_id = PVR2_CID_STDAVAIL,
1245                 .skip_init = !0,
1246                 .get_value = ctrl_stdavail_get,
1247                 .set_value = ctrl_stdavail_set,
1248                 .val_to_sym = ctrl_std_val_to_sym,
1249                 .sym_to_val = ctrl_std_sym_to_val,
1250                 .type = pvr2_ctl_bitmask,
1251         },{
1252                 .desc = "Video Standards In Use Mask",
1253                 .name = "video_standard_mask_active",
1254                 .internal_id = PVR2_CID_STDCUR,
1255                 .skip_init = !0,
1256                 .get_value = ctrl_stdcur_get,
1257                 .set_value = ctrl_stdcur_set,
1258                 .is_dirty = ctrl_stdcur_is_dirty,
1259                 .clear_dirty = ctrl_stdcur_clear_dirty,
1260                 .val_to_sym = ctrl_std_val_to_sym,
1261                 .sym_to_val = ctrl_std_sym_to_val,
1262                 .type = pvr2_ctl_bitmask,
1263         },{
1264                 .desc = "Video Standards Detected Mask",
1265                 .name = "video_standard_mask_detected",
1266                 .internal_id = PVR2_CID_STDDETECT,
1267                 .skip_init = !0,
1268                 .get_value = ctrl_stddetect_get,
1269                 .val_to_sym = ctrl_std_val_to_sym,
1270                 .sym_to_val = ctrl_std_sym_to_val,
1271                 .type = pvr2_ctl_bitmask,
1272         }
1273 };
1274
1275 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1276
1277
1278 const char *pvr2_config_get_name(enum pvr2_config cfg)
1279 {
1280         switch (cfg) {
1281         case pvr2_config_empty: return "empty";
1282         case pvr2_config_mpeg: return "mpeg";
1283         case pvr2_config_vbi: return "vbi";
1284         case pvr2_config_pcm: return "pcm";
1285         case pvr2_config_rawvideo: return "raw video";
1286         }
1287         return "<unknown>";
1288 }
1289
1290
1291 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1292 {
1293         return hdw->usb_dev;
1294 }
1295
1296
1297 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1298 {
1299         return hdw->serial_number;
1300 }
1301
1302
1303 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1304 {
1305         return hdw->bus_info;
1306 }
1307
1308
1309 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1310 {
1311         return hdw->identifier;
1312 }
1313
1314
1315 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1316 {
1317         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1318 }
1319
1320 /* Set the currently tuned frequency and account for all possible
1321    driver-core side effects of this action. */
1322 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1323 {
1324         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1325                 if (hdw->freqSelector) {
1326                         /* Swing over to radio frequency selection */
1327                         hdw->freqSelector = 0;
1328                         hdw->freqDirty = !0;
1329                 }
1330                 if (hdw->freqValRadio != val) {
1331                         hdw->freqValRadio = val;
1332                         hdw->freqSlotRadio = 0;
1333                         hdw->freqDirty = !0;
1334                 }
1335         } else {
1336                 if (!(hdw->freqSelector)) {
1337                         /* Swing over to television frequency selection */
1338                         hdw->freqSelector = 1;
1339                         hdw->freqDirty = !0;
1340                 }
1341                 if (hdw->freqValTelevision != val) {
1342                         hdw->freqValTelevision = val;
1343                         hdw->freqSlotTelevision = 0;
1344                         hdw->freqDirty = !0;
1345                 }
1346         }
1347 }
1348
1349 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1350 {
1351         return hdw->unit_number;
1352 }
1353
1354
1355 /* Attempt to locate one of the given set of files.  Messages are logged
1356    appropriate to what has been found.  The return value will be 0 or
1357    greater on success (it will be the index of the file name found) and
1358    fw_entry will be filled in.  Otherwise a negative error is returned on
1359    failure.  If the return value is -ENOENT then no viable firmware file
1360    could be located. */
1361 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1362                                 const struct firmware **fw_entry,
1363                                 const char *fwtypename,
1364                                 unsigned int fwcount,
1365                                 const char *fwnames[])
1366 {
1367         unsigned int idx;
1368         int ret = -EINVAL;
1369         for (idx = 0; idx < fwcount; idx++) {
1370                 ret = reject_firmware(fw_entry,
1371                                        fwnames[idx],
1372                                        &hdw->usb_dev->dev);
1373                 if (!ret) {
1374                         trace_firmware("Located %s firmware: %s;"
1375                                        " uploading...",
1376                                        fwtypename,
1377                                        fwnames[idx]);
1378                         return idx;
1379                 }
1380                 if (ret == -ENOENT) continue;
1381                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1382                            "request_firmware fatal error with code=%d",ret);
1383                 return ret;
1384         }
1385         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1386                    "***WARNING***"
1387                    " Device %s firmware"
1388                    " seems to be missing.",
1389                    fwtypename);
1390         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1391                    "Did you install the pvrusb2 firmware files"
1392                    " in their proper location?");
1393         if (fwcount == 1) {
1394                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1395                            "request_firmware unable to locate %s file %s",
1396                            fwtypename,fwnames[0]);
1397         } else {
1398                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1399                            "request_firmware unable to locate"
1400                            " one of the following %s files:",
1401                            fwtypename);
1402                 for (idx = 0; idx < fwcount; idx++) {
1403                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1404                                    "reject_firmware: Failed to find %s",
1405                                    fwnames[idx]);
1406                 }
1407         }
1408         return ret;
1409 }
1410
1411
1412 /*
1413  * pvr2_upload_firmware1().
1414  *
1415  * Send the 8051 firmware to the device.  After the upload, arrange for
1416  * device to re-enumerate.
1417  *
1418  * NOTE : the pointer to the firmware data given by reject_firmware()
1419  * is not suitable for an usb transaction.
1420  *
1421  */
1422 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1423 {
1424         const struct firmware *fw_entry = NULL;
1425         void  *fw_ptr;
1426         unsigned int pipe;
1427         unsigned int fwsize;
1428         int ret;
1429         u16 address;
1430
1431         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1432                 hdw->fw1_state = FW1_STATE_OK;
1433                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1434                            "Connected device type defines"
1435                            " no firmware to upload; ignoring firmware");
1436                 return -ENOTTY;
1437         }
1438
1439         hdw->fw1_state = FW1_STATE_FAILED; // default result
1440
1441         trace_firmware("pvr2_upload_firmware1");
1442
1443         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1444                                    hdw->hdw_desc->fx2_firmware.cnt,
1445                                    hdw->hdw_desc->fx2_firmware.lst);
1446         if (ret < 0) {
1447                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1448                 return ret;
1449         }
1450
1451         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1452
1453         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1454         fwsize = fw_entry->size;
1455
1456         if ((fwsize != 0x2000) &&
1457             (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1458                 if (hdw->hdw_desc->flag_fx2_16kb) {
1459                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1460                                    "Wrong fx2 firmware size"
1461                                    " (expected 8192 or 16384, got %u)",
1462                                    fwsize);
1463                 } else {
1464                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1465                                    "Wrong fx2 firmware size"
1466                                    " (expected 8192, got %u)",
1467                                    fwsize);
1468                 }
1469                 release_firmware(fw_entry);
1470                 return -ENOMEM;
1471         }
1472
1473         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1474         if (fw_ptr == NULL){
1475                 release_firmware(fw_entry);
1476                 return -ENOMEM;
1477         }
1478
1479         /* We have to hold the CPU during firmware upload. */
1480         pvr2_hdw_cpureset_assert(hdw,1);
1481
1482         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1483            chunk. */
1484
1485         ret = 0;
1486         for (address = 0; address < fwsize; address += 0x800) {
1487                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1488                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1489                                        0, fw_ptr, 0x800, HZ);
1490         }
1491
1492         trace_firmware("Upload done, releasing device's CPU");
1493
1494         /* Now release the CPU.  It will disconnect and reconnect later. */
1495         pvr2_hdw_cpureset_assert(hdw,0);
1496
1497         kfree(fw_ptr);
1498         release_firmware(fw_entry);
1499
1500         trace_firmware("Upload done (%d bytes sent)",ret);
1501
1502         /* We should have written fwsize bytes */
1503         if (ret == fwsize) {
1504                 hdw->fw1_state = FW1_STATE_RELOAD;
1505                 return 0;
1506         }
1507
1508         return -EIO;
1509 }
1510
1511
1512 /*
1513  * pvr2_upload_firmware2()
1514  *
1515  * This uploads encoder firmware on endpoint 2.
1516  *
1517  */
1518
1519 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1520 {
1521         const struct firmware *fw_entry = NULL;
1522         void  *fw_ptr;
1523         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1524         int actual_length;
1525         int ret = 0;
1526         int fwidx;
1527         static const char *fw_files[] = {
1528                 CX2341X_FIRM_ENC_FILENAME,
1529         };
1530
1531         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1532                 return 0;
1533         }
1534
1535         trace_firmware("pvr2_upload_firmware2");
1536
1537         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1538                                    ARRAY_SIZE(fw_files), fw_files);
1539         if (ret < 0) return ret;
1540         fwidx = ret;
1541         ret = 0;
1542         /* Since we're about to completely reinitialize the encoder,
1543            invalidate our cached copy of its configuration state.  Next
1544            time we configure the encoder, then we'll fully configure it. */
1545         hdw->enc_cur_valid = 0;
1546
1547         /* Encoder is about to be reset so note that as far as we're
1548            concerned now, the encoder has never been run. */
1549         del_timer_sync(&hdw->encoder_run_timer);
1550         if (hdw->state_encoder_runok) {
1551                 hdw->state_encoder_runok = 0;
1552                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1553         }
1554
1555         /* First prepare firmware loading */
1556         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1557         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1558         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1559         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1560         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1561         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1562         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1563         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1564         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1565         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1566         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1567         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1568         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1569         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1570         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1571         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1572         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1573         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1574
1575         if (ret) {
1576                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1577                            "firmware2 upload prep failed, ret=%d",ret);
1578                 release_firmware(fw_entry);
1579                 goto done;
1580         }
1581
1582         /* Now send firmware */
1583
1584         fw_len = fw_entry->size;
1585
1586         if (fw_len % sizeof(u32)) {
1587                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1588                            "size of %s firmware"
1589                            " must be a multiple of %zu bytes",
1590                            fw_files[fwidx],sizeof(u32));
1591                 release_firmware(fw_entry);
1592                 ret = -EINVAL;
1593                 goto done;
1594         }
1595
1596         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1597         if (fw_ptr == NULL){
1598                 release_firmware(fw_entry);
1599                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1600                            "failed to allocate memory for firmware2 upload");
1601                 ret = -ENOMEM;
1602                 goto done;
1603         }
1604
1605         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1606
1607         fw_done = 0;
1608         for (fw_done = 0; fw_done < fw_len;) {
1609                 bcnt = fw_len - fw_done;
1610                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1611                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1612                 /* Usbsnoop log shows that we must swap bytes... */
1613                 /* Some background info: The data being swapped here is a
1614                    firmware image destined for the mpeg encoder chip that
1615                    lives at the other end of a USB endpoint.  The encoder
1616                    chip always talks in 32 bit chunks and its storage is
1617                    organized into 32 bit words.  However from the file
1618                    system to the encoder chip everything is purely a byte
1619                    stream.  The firmware file's contents are always 32 bit
1620                    swapped from what the encoder expects.  Thus the need
1621                    always exists to swap the bytes regardless of the endian
1622                    type of the host processor and therefore swab32() makes
1623                    the most sense. */
1624                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1625                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1626
1627                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1628                                     &actual_length, HZ);
1629                 ret |= (actual_length != bcnt);
1630                 if (ret) break;
1631                 fw_done += bcnt;
1632         }
1633
1634         trace_firmware("upload of %s : %i / %i ",
1635                        fw_files[fwidx],fw_done,fw_len);
1636
1637         kfree(fw_ptr);
1638         release_firmware(fw_entry);
1639
1640         if (ret) {
1641                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1642                            "firmware2 upload transfer failure");
1643                 goto done;
1644         }
1645
1646         /* Finish upload */
1647
1648         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1649         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1650         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1651
1652         if (ret) {
1653                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1654                            "firmware2 upload post-proc failure");
1655         }
1656
1657  done:
1658         if (hdw->hdw_desc->signal_routing_scheme ==
1659             PVR2_ROUTING_SCHEME_GOTVIEW) {
1660                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1661                    hardware. */
1662                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1663         }
1664         return ret;
1665 }
1666
1667
1668 static const char *pvr2_get_state_name(unsigned int st)
1669 {
1670         if (st < ARRAY_SIZE(pvr2_state_names)) {
1671                 return pvr2_state_names[st];
1672         }
1673         return "???";
1674 }
1675
1676 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1677 {
1678         /* Even though we really only care about the video decoder chip at
1679            this point, we'll broadcast stream on/off to all sub-devices
1680            anyway, just in case somebody else wants to hear the
1681            command... */
1682         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1683                    (enablefl ? "on" : "off"));
1684         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1685         v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1686         if (hdw->decoder_client_id) {
1687                 /* We get here if the encoder has been noticed.  Otherwise
1688                    we'll issue a warning to the user (which should
1689                    normally never happen). */
1690                 return 0;
1691         }
1692         if (!hdw->flag_decoder_missed) {
1693                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1694                            "WARNING: No decoder present");
1695                 hdw->flag_decoder_missed = !0;
1696                 trace_stbit("flag_decoder_missed",
1697                             hdw->flag_decoder_missed);
1698         }
1699         return -EIO;
1700 }
1701
1702
1703 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1704 {
1705         return hdw->master_state;
1706 }
1707
1708
1709 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1710 {
1711         if (!hdw->flag_tripped) return 0;
1712         hdw->flag_tripped = 0;
1713         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1714                    "Clearing driver error statuss");
1715         return !0;
1716 }
1717
1718
1719 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1720 {
1721         int fl;
1722         LOCK_TAKE(hdw->big_lock); do {
1723                 fl = pvr2_hdw_untrip_unlocked(hdw);
1724         } while (0); LOCK_GIVE(hdw->big_lock);
1725         if (fl) pvr2_hdw_state_sched(hdw);
1726         return 0;
1727 }
1728
1729
1730
1731
1732 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1733 {
1734         return hdw->state_pipeline_req != 0;
1735 }
1736
1737
1738 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1739 {
1740         int ret,st;
1741         LOCK_TAKE(hdw->big_lock); do {
1742                 pvr2_hdw_untrip_unlocked(hdw);
1743                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1744                         hdw->state_pipeline_req = enable_flag != 0;
1745                         pvr2_trace(PVR2_TRACE_START_STOP,
1746                                    "/*--TRACE_STREAM--*/ %s",
1747                                    enable_flag ? "enable" : "disable");
1748                 }
1749                 pvr2_hdw_state_sched(hdw);
1750         } while (0); LOCK_GIVE(hdw->big_lock);
1751         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1752         if (enable_flag) {
1753                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1754                         if (st != PVR2_STATE_READY) return -EIO;
1755                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1756                 }
1757         }
1758         return 0;
1759 }
1760
1761
1762 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1763 {
1764         int fl;
1765         LOCK_TAKE(hdw->big_lock);
1766         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1767                 hdw->desired_stream_type = config;
1768                 hdw->state_pipeline_config = 0;
1769                 trace_stbit("state_pipeline_config",
1770                             hdw->state_pipeline_config);
1771                 pvr2_hdw_state_sched(hdw);
1772         }
1773         LOCK_GIVE(hdw->big_lock);
1774         if (fl) return 0;
1775         return pvr2_hdw_wait(hdw,0);
1776 }
1777
1778
1779 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1780 {
1781         int unit_number = hdw->unit_number;
1782         int tp = -1;
1783         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1784                 tp = tuner[unit_number];
1785         }
1786         if (tp < 0) return -EINVAL;
1787         hdw->tuner_type = tp;
1788         hdw->tuner_updated = !0;
1789         return 0;
1790 }
1791
1792
1793 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1794 {
1795         int unit_number = hdw->unit_number;
1796         int tp = 0;
1797         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1798                 tp = video_std[unit_number];
1799                 if (tp) return tp;
1800         }
1801         return 0;
1802 }
1803
1804
1805 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1806 {
1807         int unit_number = hdw->unit_number;
1808         int tp = 0;
1809         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1810                 tp = tolerance[unit_number];
1811         }
1812         return tp;
1813 }
1814
1815
1816 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1817 {
1818         /* Try a harmless request to fetch the eeprom's address over
1819            endpoint 1.  See what happens.  Only the full FX2 image can
1820            respond to this.  If this probe fails then likely the FX2
1821            firmware needs be loaded. */
1822         int result;
1823         LOCK_TAKE(hdw->ctl_lock); do {
1824                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1825                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1826                                            hdw->cmd_buffer,1,
1827                                            hdw->cmd_buffer,1);
1828                 if (result < 0) break;
1829         } while(0); LOCK_GIVE(hdw->ctl_lock);
1830         if (result) {
1831                 pvr2_trace(PVR2_TRACE_INIT,
1832                            "Probe of device endpoint 1 result status %d",
1833                            result);
1834         } else {
1835                 pvr2_trace(PVR2_TRACE_INIT,
1836                            "Probe of device endpoint 1 succeeded");
1837         }
1838         return result == 0;
1839 }
1840
1841 struct pvr2_std_hack {
1842         v4l2_std_id pat;  /* Pattern to match */
1843         v4l2_std_id msk;  /* Which bits we care about */
1844         v4l2_std_id std;  /* What additional standards or default to set */
1845 };
1846
1847 /* This data structure labels specific combinations of standards from
1848    tveeprom that we'll try to recognize.  If we recognize one, then assume
1849    a specified default standard to use.  This is here because tveeprom only
1850    tells us about available standards not the intended default standard (if
1851    any) for the device in question.  We guess the default based on what has
1852    been reported as available.  Note that this is only for guessing a
1853    default - which can always be overridden explicitly - and if the user
1854    has otherwise named a default then that default will always be used in
1855    place of this table. */
1856 static const struct pvr2_std_hack std_eeprom_maps[] = {
1857         {       /* PAL(B/G) */
1858                 .pat = V4L2_STD_B|V4L2_STD_GH,
1859                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1860         },
1861         {       /* NTSC(M) */
1862                 .pat = V4L2_STD_MN,
1863                 .std = V4L2_STD_NTSC_M,
1864         },
1865         {       /* PAL(I) */
1866                 .pat = V4L2_STD_PAL_I,
1867                 .std = V4L2_STD_PAL_I,
1868         },
1869         {       /* SECAM(L/L') */
1870                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1871                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1872         },
1873         {       /* PAL(D/D1/K) */
1874                 .pat = V4L2_STD_DK,
1875                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1876         },
1877 };
1878
1879 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1880 {
1881         char buf[40];
1882         unsigned int bcnt;
1883         v4l2_std_id std1,std2,std3;
1884
1885         std1 = get_default_standard(hdw);
1886         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1887
1888         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1889         pvr2_trace(PVR2_TRACE_STD,
1890                    "Supported video standard(s) reported available"
1891                    " in hardware: %.*s",
1892                    bcnt,buf);
1893
1894         hdw->std_mask_avail = hdw->std_mask_eeprom;
1895
1896         std2 = (std1|std3) & ~hdw->std_mask_avail;
1897         if (std2) {
1898                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1899                 pvr2_trace(PVR2_TRACE_STD,
1900                            "Expanding supported video standards"
1901                            " to include: %.*s",
1902                            bcnt,buf);
1903                 hdw->std_mask_avail |= std2;
1904         }
1905
1906         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1907
1908         if (std1) {
1909                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1910                 pvr2_trace(PVR2_TRACE_STD,
1911                            "Initial video standard forced to %.*s",
1912                            bcnt,buf);
1913                 hdw->std_mask_cur = std1;
1914                 hdw->std_dirty = !0;
1915                 return;
1916         }
1917         if (std3) {
1918                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1919                 pvr2_trace(PVR2_TRACE_STD,
1920                            "Initial video standard"
1921                            " (determined by device type): %.*s",bcnt,buf);
1922                 hdw->std_mask_cur = std3;
1923                 hdw->std_dirty = !0;
1924                 return;
1925         }
1926
1927         {
1928                 unsigned int idx;
1929                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1930                         if (std_eeprom_maps[idx].msk ?
1931                             ((std_eeprom_maps[idx].pat ^
1932                              hdw->std_mask_eeprom) &
1933                              std_eeprom_maps[idx].msk) :
1934                             (std_eeprom_maps[idx].pat !=
1935                              hdw->std_mask_eeprom)) continue;
1936                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1937                                                   std_eeprom_maps[idx].std);
1938                         pvr2_trace(PVR2_TRACE_STD,
1939                                    "Initial video standard guessed as %.*s",
1940                                    bcnt,buf);
1941                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1942                         hdw->std_dirty = !0;
1943                         return;
1944                 }
1945         }
1946
1947 }
1948
1949
1950 static unsigned int pvr2_copy_i2c_addr_list(
1951         unsigned short *dst, const unsigned char *src,
1952         unsigned int dst_max)
1953 {
1954         unsigned int cnt = 0;
1955         if (!src) return 0;
1956         while (src[cnt] && (cnt + 1) < dst_max) {
1957                 dst[cnt] = src[cnt];
1958                 cnt++;
1959         }
1960         dst[cnt] = I2C_CLIENT_END;
1961         return cnt;
1962 }
1963
1964
1965 static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
1966 {
1967         /*
1968           Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
1969           for cx25840 causes that module to correctly set up its video
1970           scaling.  This is really a problem in the cx25840 module itself,
1971           but we work around it here.  The problem has not been seen in
1972           ivtv because there VBI is supported and set up.  We don't do VBI
1973           here (at least not yet) and thus we never attempted to even set
1974           it up.
1975         */
1976         struct v4l2_format fmt;
1977         if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
1978                 /* We're not using a cx25840 so don't enable the hack */
1979                 return;
1980         }
1981
1982         pvr2_trace(PVR2_TRACE_INIT,
1983                    "Module ID %u:"
1984                    " Executing cx25840 VBI hack",
1985                    hdw->decoder_client_id);
1986         memset(&fmt, 0, sizeof(fmt));
1987         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
1988         fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
1989         fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
1990         v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
1991                              vbi, s_sliced_fmt, &fmt.fmt.sliced);
1992 }
1993
1994
1995 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1996                                 const struct pvr2_device_client_desc *cd)
1997 {
1998         const char *fname;
1999         unsigned char mid;
2000         struct v4l2_subdev *sd;
2001         unsigned int i2ccnt;
2002         const unsigned char *p;
2003         /* Arbitrary count - max # i2c addresses we will probe */
2004         unsigned short i2caddr[25];
2005
2006         mid = cd->module_id;
2007         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2008         if (!fname) {
2009                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2010                            "Module ID %u for device %s has no name?"
2011                            "  The driver might have a configuration problem.",
2012                            mid,
2013                            hdw->hdw_desc->description);
2014                 return -EINVAL;
2015         }
2016         pvr2_trace(PVR2_TRACE_INIT,
2017                    "Module ID %u (%s) for device %s being loaded...",
2018                    mid, fname,
2019                    hdw->hdw_desc->description);
2020
2021         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2022                                          ARRAY_SIZE(i2caddr));
2023         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2024                          module_i2c_addresses[mid] : NULL) != NULL)) {
2025                 /* Second chance: Try default i2c address list */
2026                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2027                                                  ARRAY_SIZE(i2caddr));
2028                 if (i2ccnt) {
2029                         pvr2_trace(PVR2_TRACE_INIT,
2030                                    "Module ID %u:"
2031                                    " Using default i2c address list",
2032                                    mid);
2033                 }
2034         }
2035
2036         if (!i2ccnt) {
2037                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2038                            "Module ID %u (%s) for device %s:"
2039                            " No i2c addresses."
2040                            "  The driver might have a configuration problem.",
2041                            mid, fname, hdw->hdw_desc->description);
2042                 return -EINVAL;
2043         }
2044
2045         if (i2ccnt == 1) {
2046                 pvr2_trace(PVR2_TRACE_INIT,
2047                            "Module ID %u:"
2048                            " Setting up with specified i2c address 0x%x",
2049                            mid, i2caddr[0]);
2050                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2051                                          fname, i2caddr[0], NULL);
2052         } else {
2053                 pvr2_trace(PVR2_TRACE_INIT,
2054                            "Module ID %u:"
2055                            " Setting up with address probe list",
2056                            mid);
2057                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2058                                          fname, 0, i2caddr);
2059         }
2060
2061         if (!sd) {
2062                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2063                            "Module ID %u (%s) for device %s failed to load."
2064                            "  Possible missing sub-device kernel module or"
2065                            " initialization failure within module.",
2066                            mid, fname, hdw->hdw_desc->description);
2067                 return -EIO;
2068         }
2069
2070         /* Tag this sub-device instance with the module ID we know about.
2071            In other places we'll use that tag to determine if the instance
2072            requires special handling. */
2073         sd->grp_id = mid;
2074
2075         pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2076
2077
2078         /* client-specific setup... */
2079         switch (mid) {
2080         case PVR2_CLIENT_ID_CX25840:
2081         case PVR2_CLIENT_ID_SAA7115:
2082                 hdw->decoder_client_id = mid;
2083                 break;
2084         default: break;
2085         }
2086
2087         return 0;
2088 }
2089
2090
2091 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2092 {
2093         unsigned int idx;
2094         const struct pvr2_string_table *cm;
2095         const struct pvr2_device_client_table *ct;
2096         int okFl = !0;
2097
2098         cm = &hdw->hdw_desc->client_modules;
2099         for (idx = 0; idx < cm->cnt; idx++) {
2100                 request_module(cm->lst[idx]);
2101         }
2102
2103         ct = &hdw->hdw_desc->client_table;
2104         for (idx = 0; idx < ct->cnt; idx++) {
2105                 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2106         }
2107         if (!okFl) {
2108                 hdw->flag_modulefail = !0;
2109                 pvr2_hdw_render_useless(hdw);
2110         }
2111 }
2112
2113
2114 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2115 {
2116         int ret;
2117         unsigned int idx;
2118         struct pvr2_ctrl *cptr;
2119         int reloadFl = 0;
2120         if (hdw->hdw_desc->fx2_firmware.cnt) {
2121                 if (!reloadFl) {
2122                         reloadFl =
2123                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2124                                  == 0);
2125                         if (reloadFl) {
2126                                 pvr2_trace(PVR2_TRACE_INIT,
2127                                            "USB endpoint config looks strange"
2128                                            "; possibly firmware needs to be"
2129                                            " loaded");
2130                         }
2131                 }
2132                 if (!reloadFl) {
2133                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2134                         if (reloadFl) {
2135                                 pvr2_trace(PVR2_TRACE_INIT,
2136                                            "Check for FX2 firmware failed"
2137                                            "; possibly firmware needs to be"
2138                                            " loaded");
2139                         }
2140                 }
2141                 if (reloadFl) {
2142                         if (pvr2_upload_firmware1(hdw) != 0) {
2143                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2144                                            "Failure uploading firmware1");
2145                         }
2146                         return;
2147                 }
2148         }
2149         hdw->fw1_state = FW1_STATE_OK;
2150
2151         if (!pvr2_hdw_dev_ok(hdw)) return;
2152
2153         hdw->force_dirty = !0;
2154
2155         if (!hdw->hdw_desc->flag_no_powerup) {
2156                 pvr2_hdw_cmd_powerup(hdw);
2157                 if (!pvr2_hdw_dev_ok(hdw)) return;
2158         }
2159
2160         /* Take the IR chip out of reset, if appropriate */
2161         if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2162                 pvr2_issue_simple_cmd(hdw,
2163                                       FX2CMD_HCW_ZILOG_RESET |
2164                                       (1 << 8) |
2165                                       ((0) << 16));
2166         }
2167
2168         // This step MUST happen after the earlier powerup step.
2169         pvr2_i2c_core_init(hdw);
2170         if (!pvr2_hdw_dev_ok(hdw)) return;
2171
2172         pvr2_hdw_load_modules(hdw);
2173         if (!pvr2_hdw_dev_ok(hdw)) return;
2174
2175         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2176
2177         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2178                 cptr = hdw->controls + idx;
2179                 if (cptr->info->skip_init) continue;
2180                 if (!cptr->info->set_value) continue;
2181                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2182         }
2183
2184         pvr2_hdw_cx25840_vbi_hack(hdw);
2185
2186         /* Set up special default values for the television and radio
2187            frequencies here.  It's not really important what these defaults
2188            are, but I set them to something usable in the Chicago area just
2189            to make driver testing a little easier. */
2190
2191         hdw->freqValTelevision = default_tv_freq;
2192         hdw->freqValRadio = default_radio_freq;
2193
2194         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2195         // thread-safe against the normal pvr2_send_request() mechanism.
2196         // (We should make it thread safe).
2197
2198         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2199                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2200                 if (!pvr2_hdw_dev_ok(hdw)) return;
2201                 if (ret < 0) {
2202                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2203                                    "Unable to determine location of eeprom,"
2204                                    " skipping");
2205                 } else {
2206                         hdw->eeprom_addr = ret;
2207                         pvr2_eeprom_analyze(hdw);
2208                         if (!pvr2_hdw_dev_ok(hdw)) return;
2209                 }
2210         } else {
2211                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2212                 hdw->tuner_updated = !0;
2213                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2214         }
2215
2216         if (hdw->serial_number) {
2217                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2218                                 "sn-%lu", hdw->serial_number);
2219         } else if (hdw->unit_number >= 0) {
2220                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2221                                 "unit-%c",
2222                                 hdw->unit_number + 'a');
2223         } else {
2224                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2225                                 "unit-??");
2226         }
2227         hdw->identifier[idx] = 0;
2228
2229         pvr2_hdw_setup_std(hdw);
2230
2231         if (!get_default_tuner_type(hdw)) {
2232                 pvr2_trace(PVR2_TRACE_INIT,
2233                            "pvr2_hdw_setup: Tuner type overridden to %d",
2234                            hdw->tuner_type);
2235         }
2236
2237
2238         if (!pvr2_hdw_dev_ok(hdw)) return;
2239
2240         if (hdw->hdw_desc->signal_routing_scheme ==
2241             PVR2_ROUTING_SCHEME_GOTVIEW) {
2242                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2243                    hardware. */
2244                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2245         }
2246
2247         pvr2_hdw_commit_setup(hdw);
2248
2249         hdw->vid_stream = pvr2_stream_create();
2250         if (!pvr2_hdw_dev_ok(hdw)) return;
2251         pvr2_trace(PVR2_TRACE_INIT,
2252                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2253         if (hdw->vid_stream) {
2254                 idx = get_default_error_tolerance(hdw);
2255                 if (idx) {
2256                         pvr2_trace(PVR2_TRACE_INIT,
2257                                    "pvr2_hdw_setup: video stream %p"
2258                                    " setting tolerance %u",
2259                                    hdw->vid_stream,idx);
2260                 }
2261                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2262                                   PVR2_VID_ENDPOINT,idx);
2263         }
2264
2265         if (!pvr2_hdw_dev_ok(hdw)) return;
2266
2267         hdw->flag_init_ok = !0;
2268
2269         pvr2_hdw_state_sched(hdw);
2270 }
2271
2272
2273 /* Set up the structure and attempt to put the device into a usable state.
2274    This can be a time-consuming operation, which is why it is not done
2275    internally as part of the create() step. */
2276 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2277 {
2278         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2279         do {
2280                 pvr2_hdw_setup_low(hdw);
2281                 pvr2_trace(PVR2_TRACE_INIT,
2282                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2283                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2284                 if (pvr2_hdw_dev_ok(hdw)) {
2285                         if (hdw->flag_init_ok) {
2286                                 pvr2_trace(
2287                                         PVR2_TRACE_INFO,
2288                                         "Device initialization"
2289                                         " completed successfully.");
2290                                 break;
2291                         }
2292                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2293                                 pvr2_trace(
2294                                         PVR2_TRACE_INFO,
2295                                         "Device microcontroller firmware"
2296                                         " (re)loaded; it should now reset"
2297                                         " and reconnect.");
2298                                 break;
2299                         }
2300                         pvr2_trace(
2301                                 PVR2_TRACE_ERROR_LEGS,
2302                                 "Device initialization was not successful.");
2303                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2304                                 pvr2_trace(
2305                                         PVR2_TRACE_ERROR_LEGS,
2306                                         "Giving up since device"
2307                                         " microcontroller firmware"
2308                                         " appears to be missing.");
2309                                 break;
2310                         }
2311                 }
2312                 if (hdw->flag_modulefail) {
2313                         pvr2_trace(
2314                                 PVR2_TRACE_ERROR_LEGS,
2315                                 "***WARNING*** pvrusb2 driver initialization"
2316                                 " failed due to the failure of one or more"
2317                                 " sub-device kernel modules.");
2318                         pvr2_trace(
2319                                 PVR2_TRACE_ERROR_LEGS,
2320                                 "You need to resolve the failing condition"
2321                                 " before this driver can function.  There"
2322                                 " should be some earlier messages giving more"
2323                                 " information about the problem.");
2324                         break;
2325                 }
2326                 if (procreload) {
2327                         pvr2_trace(
2328                                 PVR2_TRACE_ERROR_LEGS,
2329                                 "Attempting pvrusb2 recovery by reloading"
2330                                 " primary firmware.");
2331                         pvr2_trace(
2332                                 PVR2_TRACE_ERROR_LEGS,
2333                                 "If this works, device should disconnect"
2334                                 " and reconnect in a sane state.");
2335                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2336                         pvr2_upload_firmware1(hdw);
2337                 } else {
2338                         pvr2_trace(
2339                                 PVR2_TRACE_ERROR_LEGS,
2340                                 "***WARNING*** pvrusb2 device hardware"
2341                                 " appears to be jammed"
2342                                 " and I can't clear it.");
2343                         pvr2_trace(
2344                                 PVR2_TRACE_ERROR_LEGS,
2345                                 "You might need to power cycle"
2346                                 " the pvrusb2 device"
2347                                 " in order to recover.");
2348                 }
2349         } while (0);
2350         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2351 }
2352
2353
2354 /* Perform second stage initialization.  Set callback pointer first so that
2355    we can avoid a possible initialization race (if the kernel thread runs
2356    before the callback has been set). */
2357 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2358                         void (*callback_func)(void *),
2359                         void *callback_data)
2360 {
2361         LOCK_TAKE(hdw->big_lock); do {
2362                 if (hdw->flag_disconnected) {
2363                         /* Handle a race here: If we're already
2364                            disconnected by this point, then give up.  If we
2365                            get past this then we'll remain connected for
2366                            the duration of initialization since the entire
2367                            initialization sequence is now protected by the
2368                            big_lock. */
2369                         break;
2370                 }
2371                 hdw->state_data = callback_data;
2372                 hdw->state_func = callback_func;
2373                 pvr2_hdw_setup(hdw);
2374         } while (0); LOCK_GIVE(hdw->big_lock);
2375         return hdw->flag_init_ok;
2376 }
2377
2378
2379 /* Create, set up, and return a structure for interacting with the
2380    underlying hardware.  */
2381 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2382                                  const struct usb_device_id *devid)
2383 {
2384         unsigned int idx,cnt1,cnt2,m;
2385         struct pvr2_hdw *hdw = NULL;
2386         int valid_std_mask;
2387         struct pvr2_ctrl *cptr;
2388         struct usb_device *usb_dev;
2389         const struct pvr2_device_desc *hdw_desc;
2390         __u8 ifnum;
2391         struct v4l2_queryctrl qctrl;
2392         struct pvr2_ctl_info *ciptr;
2393
2394         usb_dev = interface_to_usbdev(intf);
2395
2396         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2397
2398         if (hdw_desc == NULL) {
2399                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2400                            " No device description pointer,"
2401                            " unable to continue.");
2402                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2403                            " please contact Mike Isely <isely@pobox.com>"
2404                            " to get it included in the driver\n");
2405                 goto fail;
2406         }
2407
2408         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2409         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2410                    hdw,hdw_desc->description);
2411         pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
2412                 hdw_desc->description);
2413         if (hdw_desc->flag_is_experimental) {
2414                 pvr2_trace(PVR2_TRACE_INFO, "**********");
2415                 pvr2_trace(PVR2_TRACE_INFO,
2416                            "WARNING: Support for this device (%s) is"
2417                            " experimental.", hdw_desc->description);
2418                 pvr2_trace(PVR2_TRACE_INFO,
2419                            "Important functionality might not be"
2420                            " entirely working.");
2421                 pvr2_trace(PVR2_TRACE_INFO,
2422                            "Please consider contacting the driver author to"
2423                            " help with further stabilization of the driver.");
2424                 pvr2_trace(PVR2_TRACE_INFO, "**********");
2425         }
2426         if (!hdw) goto fail;
2427
2428         setup_timer(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout,
2429                     (unsigned long)hdw);
2430
2431         setup_timer(&hdw->decoder_stabilization_timer,
2432                     pvr2_hdw_decoder_stabilization_timeout,
2433                     (unsigned long)hdw);
2434
2435         setup_timer(&hdw->encoder_wait_timer, pvr2_hdw_encoder_wait_timeout,
2436                     (unsigned long)hdw);
2437
2438         setup_timer(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout,
2439                     (unsigned long)hdw);
2440
2441         hdw->master_state = PVR2_STATE_DEAD;
2442
2443         init_waitqueue_head(&hdw->state_wait_data);
2444
2445         hdw->tuner_signal_stale = !0;
2446         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2447
2448         /* Calculate which inputs are OK */
2449         m = 0;
2450         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2451         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2452                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2453         }
2454         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2455         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2456         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2457         hdw->input_avail_mask = m;
2458         hdw->input_allowed_mask = hdw->input_avail_mask;
2459
2460         /* If not a hybrid device, pathway_state never changes.  So
2461            initialize it here to what it should forever be. */
2462         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2463                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2464         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2465                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2466         }
2467
2468         hdw->control_cnt = CTRLDEF_COUNT;
2469         hdw->control_cnt += MPEGDEF_COUNT;
2470         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2471                                 GFP_KERNEL);
2472         if (!hdw->controls) goto fail;
2473         hdw->hdw_desc = hdw_desc;
2474         hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2475         for (idx = 0; idx < hdw->control_cnt; idx++) {
2476                 cptr = hdw->controls + idx;
2477                 cptr->hdw = hdw;
2478         }
2479         for (idx = 0; idx < 32; idx++) {
2480                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2481         }
2482         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2483                 cptr = hdw->controls + idx;
2484                 cptr->info = control_defs+idx;
2485         }
2486
2487         /* Ensure that default input choice is a valid one. */
2488         m = hdw->input_avail_mask;
2489         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2490                 if (!((1 << idx) & m)) continue;
2491                 hdw->input_val = idx;
2492                 break;
2493         }
2494
2495         /* Define and configure additional controls from cx2341x module. */
2496         hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT,
2497                                       sizeof(*(hdw->mpeg_ctrl_info)),
2498                                       GFP_KERNEL);
2499         if (!hdw->mpeg_ctrl_info) goto fail;
2500         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2501                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2502                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2503                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2504                 ciptr->name = mpeg_ids[idx].strid;
2505                 ciptr->v4l_id = mpeg_ids[idx].id;
2506                 ciptr->skip_init = !0;
2507                 ciptr->get_value = ctrl_cx2341x_get;
2508                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2509                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2510                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2511                 qctrl.id = ciptr->v4l_id;
2512                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2513                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2514                         ciptr->set_value = ctrl_cx2341x_set;
2515                 }
2516                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2517                         PVR2_CTLD_INFO_DESC_SIZE);
2518                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2519                 ciptr->default_value = qctrl.default_value;
2520                 switch (qctrl.type) {
2521                 default:
2522                 case V4L2_CTRL_TYPE_INTEGER:
2523                         ciptr->type = pvr2_ctl_int;
2524                         ciptr->def.type_int.min_value = qctrl.minimum;
2525                         ciptr->def.type_int.max_value = qctrl.maximum;
2526                         break;
2527                 case V4L2_CTRL_TYPE_BOOLEAN:
2528                         ciptr->type = pvr2_ctl_bool;
2529                         break;
2530                 case V4L2_CTRL_TYPE_MENU:
2531                         ciptr->type = pvr2_ctl_enum;
2532                         ciptr->def.type_enum.value_names =
2533                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2534                                                                 ciptr->v4l_id);
2535                         for (cnt1 = 0;
2536                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2537                              cnt1++) { }
2538                         ciptr->def.type_enum.count = cnt1;
2539                         break;
2540                 }
2541                 cptr->info = ciptr;
2542         }
2543
2544         // Initialize control data regarding video standard masks
2545         valid_std_mask = pvr2_std_get_usable();
2546         for (idx = 0; idx < 32; idx++) {
2547                 if (!(valid_std_mask & (1 << idx))) continue;
2548                 cnt1 = pvr2_std_id_to_str(
2549                         hdw->std_mask_names[idx],
2550                         sizeof(hdw->std_mask_names[idx])-1,
2551                         1 << idx);
2552                 hdw->std_mask_names[idx][cnt1] = 0;
2553         }
2554         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2555         if (cptr) {
2556                 memcpy(&hdw->std_info_avail,cptr->info,
2557                        sizeof(hdw->std_info_avail));
2558                 cptr->info = &hdw->std_info_avail;
2559                 hdw->std_info_avail.def.type_bitmask.bit_names =
2560                         hdw->std_mask_ptrs;
2561                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2562                         valid_std_mask;
2563         }
2564         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2565         if (cptr) {
2566                 memcpy(&hdw->std_info_cur,cptr->info,
2567                        sizeof(hdw->std_info_cur));
2568                 cptr->info = &hdw->std_info_cur;
2569                 hdw->std_info_cur.def.type_bitmask.bit_names =
2570                         hdw->std_mask_ptrs;
2571                 hdw->std_info_cur.def.type_bitmask.valid_bits =
2572                         valid_std_mask;
2573         }
2574         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT);
2575         if (cptr) {
2576                 memcpy(&hdw->std_info_detect,cptr->info,
2577                        sizeof(hdw->std_info_detect));
2578                 cptr->info = &hdw->std_info_detect;
2579                 hdw->std_info_detect.def.type_bitmask.bit_names =
2580                         hdw->std_mask_ptrs;
2581                 hdw->std_info_detect.def.type_bitmask.valid_bits =
2582                         valid_std_mask;
2583         }
2584
2585         hdw->cropcap_stale = !0;
2586         hdw->eeprom_addr = -1;
2587         hdw->unit_number = -1;
2588         hdw->v4l_minor_number_video = -1;
2589         hdw->v4l_minor_number_vbi = -1;
2590         hdw->v4l_minor_number_radio = -1;
2591         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2592         if (!hdw->ctl_write_buffer) goto fail;
2593         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2594         if (!hdw->ctl_read_buffer) goto fail;
2595         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2596         if (!hdw->ctl_write_urb) goto fail;
2597         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2598         if (!hdw->ctl_read_urb) goto fail;
2599
2600         if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2601                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2602                            "Error registering with v4l core, giving up");
2603                 goto fail;
2604         }
2605         mutex_lock(&pvr2_unit_mtx);
2606         do {
2607                 for (idx = 0; idx < PVR_NUM; idx++) {
2608                         if (unit_pointers[idx]) continue;
2609                         hdw->unit_number = idx;
2610                         unit_pointers[idx] = hdw;
2611                         break;
2612                 }
2613         } while (0);
2614         mutex_unlock(&pvr2_unit_mtx);
2615
2616         cnt1 = 0;
2617         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2618         cnt1 += cnt2;
2619         if (hdw->unit_number >= 0) {
2620                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2621                                  ('a' + hdw->unit_number));
2622                 cnt1 += cnt2;
2623         }
2624         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2625         hdw->name[cnt1] = 0;
2626
2627         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2628
2629         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2630                    hdw->unit_number,hdw->name);
2631
2632         hdw->tuner_type = -1;
2633         hdw->flag_ok = !0;
2634
2635         hdw->usb_intf = intf;
2636         hdw->usb_dev = usb_dev;
2637
2638         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2639
2640         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2641         usb_set_interface(hdw->usb_dev,ifnum,0);
2642
2643         mutex_init(&hdw->ctl_lock_mutex);
2644         mutex_init(&hdw->big_lock_mutex);
2645
2646         return hdw;
2647  fail:
2648         if (hdw) {
2649                 del_timer_sync(&hdw->quiescent_timer);
2650                 del_timer_sync(&hdw->decoder_stabilization_timer);
2651                 del_timer_sync(&hdw->encoder_run_timer);
2652                 del_timer_sync(&hdw->encoder_wait_timer);
2653                 flush_work(&hdw->workpoll);
2654                 usb_free_urb(hdw->ctl_read_urb);
2655                 usb_free_urb(hdw->ctl_write_urb);
2656                 kfree(hdw->ctl_read_buffer);
2657                 kfree(hdw->ctl_write_buffer);
2658                 kfree(hdw->controls);
2659                 kfree(hdw->mpeg_ctrl_info);
2660                 kfree(hdw);
2661         }
2662         return NULL;
2663 }
2664
2665
2666 /* Remove _all_ associations between this driver and the underlying USB
2667    layer. */
2668 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2669 {
2670         if (hdw->flag_disconnected) return;
2671         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2672         if (hdw->ctl_read_urb) {
2673                 usb_kill_urb(hdw->ctl_read_urb);
2674                 usb_free_urb(hdw->ctl_read_urb);
2675                 hdw->ctl_read_urb = NULL;
2676         }
2677         if (hdw->ctl_write_urb) {
2678                 usb_kill_urb(hdw->ctl_write_urb);
2679                 usb_free_urb(hdw->ctl_write_urb);
2680                 hdw->ctl_write_urb = NULL;
2681         }
2682         if (hdw->ctl_read_buffer) {
2683                 kfree(hdw->ctl_read_buffer);
2684                 hdw->ctl_read_buffer = NULL;
2685         }
2686         if (hdw->ctl_write_buffer) {
2687                 kfree(hdw->ctl_write_buffer);
2688                 hdw->ctl_write_buffer = NULL;
2689         }
2690         hdw->flag_disconnected = !0;
2691         /* If we don't do this, then there will be a dangling struct device
2692            reference to our disappearing device persisting inside the V4L
2693            core... */
2694         v4l2_device_disconnect(&hdw->v4l2_dev);
2695         hdw->usb_dev = NULL;
2696         hdw->usb_intf = NULL;
2697         pvr2_hdw_render_useless(hdw);
2698 }
2699
2700 void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev)
2701 {
2702         vdev->v4l2_dev = &hdw->v4l2_dev;
2703 }
2704
2705 /* Destroy hardware interaction structure */
2706 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2707 {
2708         if (!hdw) return;
2709         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2710         flush_work(&hdw->workpoll);
2711         del_timer_sync(&hdw->quiescent_timer);
2712         del_timer_sync(&hdw->decoder_stabilization_timer);
2713         del_timer_sync(&hdw->encoder_run_timer);
2714         del_timer_sync(&hdw->encoder_wait_timer);
2715         if (hdw->fw_buffer) {
2716                 kfree(hdw->fw_buffer);
2717                 hdw->fw_buffer = NULL;
2718         }
2719         if (hdw->vid_stream) {
2720                 pvr2_stream_destroy(hdw->vid_stream);
2721                 hdw->vid_stream = NULL;
2722         }
2723         pvr2_i2c_core_done(hdw);
2724         v4l2_device_unregister(&hdw->v4l2_dev);
2725         pvr2_hdw_remove_usb_stuff(hdw);
2726         mutex_lock(&pvr2_unit_mtx);
2727         do {
2728                 if ((hdw->unit_number >= 0) &&
2729                     (hdw->unit_number < PVR_NUM) &&
2730                     (unit_pointers[hdw->unit_number] == hdw)) {
2731                         unit_pointers[hdw->unit_number] = NULL;
2732                 }
2733         } while (0);
2734         mutex_unlock(&pvr2_unit_mtx);
2735         kfree(hdw->controls);
2736         kfree(hdw->mpeg_ctrl_info);
2737         kfree(hdw);
2738 }
2739
2740
2741 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2742 {
2743         return (hdw && hdw->flag_ok);
2744 }
2745
2746
2747 /* Called when hardware has been unplugged */
2748 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2749 {
2750         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2751         LOCK_TAKE(hdw->big_lock);
2752         LOCK_TAKE(hdw->ctl_lock);
2753         pvr2_hdw_remove_usb_stuff(hdw);
2754         LOCK_GIVE(hdw->ctl_lock);
2755         LOCK_GIVE(hdw->big_lock);
2756 }
2757
2758
2759 /* Get the number of defined controls */
2760 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2761 {
2762         return hdw->control_cnt;
2763 }
2764
2765
2766 /* Retrieve a control handle given its index (0..count-1) */
2767 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2768                                              unsigned int idx)
2769 {
2770         if (idx >= hdw->control_cnt) return NULL;
2771         return hdw->controls + idx;
2772 }
2773
2774
2775 /* Retrieve a control handle given its index (0..count-1) */
2776 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2777                                           unsigned int ctl_id)
2778 {
2779         struct pvr2_ctrl *cptr;
2780         unsigned int idx;
2781         int i;
2782
2783         /* This could be made a lot more efficient, but for now... */
2784         for (idx = 0; idx < hdw->control_cnt; idx++) {
2785                 cptr = hdw->controls + idx;
2786                 i = cptr->info->internal_id;
2787                 if (i && (i == ctl_id)) return cptr;
2788         }
2789         return NULL;
2790 }
2791
2792
2793 /* Given a V4L ID, retrieve the control structure associated with it. */
2794 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2795 {
2796         struct pvr2_ctrl *cptr;
2797         unsigned int idx;
2798         int i;
2799
2800         /* This could be made a lot more efficient, but for now... */
2801         for (idx = 0; idx < hdw->control_cnt; idx++) {
2802                 cptr = hdw->controls + idx;
2803                 i = cptr->info->v4l_id;
2804                 if (i && (i == ctl_id)) return cptr;
2805         }
2806         return NULL;
2807 }
2808
2809
2810 /* Given a V4L ID for its immediate predecessor, retrieve the control
2811    structure associated with it. */
2812 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2813                                             unsigned int ctl_id)
2814 {
2815         struct pvr2_ctrl *cptr,*cp2;
2816         unsigned int idx;
2817         int i;
2818
2819         /* This could be made a lot more efficient, but for now... */
2820         cp2 = NULL;
2821         for (idx = 0; idx < hdw->control_cnt; idx++) {
2822                 cptr = hdw->controls + idx;
2823                 i = cptr->info->v4l_id;
2824                 if (!i) continue;
2825                 if (i <= ctl_id) continue;
2826                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2827                 cp2 = cptr;
2828         }
2829         return cp2;
2830         return NULL;
2831 }
2832
2833
2834 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2835 {
2836         switch (tp) {
2837         case pvr2_ctl_int: return "integer";
2838         case pvr2_ctl_enum: return "enum";
2839         case pvr2_ctl_bool: return "boolean";
2840         case pvr2_ctl_bitmask: return "bitmask";
2841         }
2842         return "";
2843 }
2844
2845
2846 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2847                                     const char *name, int val)
2848 {
2849         struct v4l2_control ctrl;
2850         struct v4l2_subdev *sd;
2851
2852         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2853         memset(&ctrl, 0, sizeof(ctrl));
2854         ctrl.id = id;
2855         ctrl.value = val;
2856
2857         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev)
2858                 v4l2_s_ctrl(NULL, sd->ctrl_handler, &ctrl);
2859 }
2860
2861 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2862         if ((hdw)->lab##_dirty || (hdw)->force_dirty) {         \
2863                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2864         }
2865
2866 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw)
2867 {
2868         v4l2_std_id std;
2869         std = (v4l2_std_id)hdw->std_mask_avail;
2870         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2871                              video, querystd, &std);
2872         return std;
2873 }
2874
2875 /* Execute whatever commands are required to update the state of all the
2876    sub-devices so that they match our current control values. */
2877 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2878 {
2879         struct v4l2_subdev *sd;
2880         unsigned int id;
2881         pvr2_subdev_update_func fp;
2882
2883         pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2884
2885         if (hdw->tuner_updated || hdw->force_dirty) {
2886                 struct tuner_setup setup;
2887                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2888                            hdw->tuner_type);
2889                 if (((int)(hdw->tuner_type)) >= 0) {
2890                         memset(&setup, 0, sizeof(setup));
2891                         setup.addr = ADDR_UNSET;
2892                         setup.type = hdw->tuner_type;
2893                         setup.mode_mask = T_RADIO | T_ANALOG_TV;
2894                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2895                                              tuner, s_type_addr, &setup);
2896                 }
2897         }
2898
2899         if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
2900                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2901                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2902                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2903                                              tuner, s_radio);
2904                 } else {
2905                         v4l2_std_id vs;
2906                         vs = hdw->std_mask_cur;
2907                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2908                                              video, s_std, vs);
2909                         pvr2_hdw_cx25840_vbi_hack(hdw);
2910                 }
2911                 hdw->tuner_signal_stale = !0;
2912                 hdw->cropcap_stale = !0;
2913         }
2914
2915         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2916         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2917         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2918         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2919         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2920         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2921         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2922         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2923         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2924
2925         if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2926                 struct v4l2_tuner vt;
2927                 memset(&vt, 0, sizeof(vt));
2928                 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
2929                         V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2930                 vt.audmode = hdw->audiomode_val;
2931                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2932         }
2933
2934         if (hdw->freqDirty || hdw->force_dirty) {
2935                 unsigned long fv;
2936                 struct v4l2_frequency freq;
2937                 fv = pvr2_hdw_get_cur_freq(hdw);
2938                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2939                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2940                 memset(&freq, 0, sizeof(freq));
2941                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2942                         /* ((fv * 1000) / 62500) */
2943                         freq.frequency = (fv * 2) / 125;
2944                 } else {
2945                         freq.frequency = fv / 62500;
2946                 }
2947                 /* tuner-core currently doesn't seem to care about this, but
2948                    let's set it anyway for completeness. */
2949                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2950                         freq.type = V4L2_TUNER_RADIO;
2951                 } else {
2952                         freq.type = V4L2_TUNER_ANALOG_TV;
2953                 }
2954                 freq.tuner = 0;
2955                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2956                                      s_frequency, &freq);
2957         }
2958
2959         if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2960                 struct v4l2_subdev_format format = {
2961                         .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2962                 };
2963
2964                 format.format.width = hdw->res_hor_val;
2965                 format.format.height = hdw->res_ver_val;
2966                 format.format.code = MEDIA_BUS_FMT_FIXED;
2967                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2968                            format.format.width, format.format.height);
2969                 v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt,
2970                                      NULL, &format);
2971         }
2972
2973         if (hdw->srate_dirty || hdw->force_dirty) {
2974                 u32 val;
2975                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
2976                            hdw->srate_val);
2977                 switch (hdw->srate_val) {
2978                 default:
2979                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
2980                         val = 48000;
2981                         break;
2982                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
2983                         val = 44100;
2984                         break;
2985                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
2986                         val = 32000;
2987                         break;
2988                 }
2989                 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2990                                      audio, s_clock_freq, val);
2991         }
2992
2993         /* Unable to set crop parameters; there is apparently no equivalent
2994            for VIDIOC_S_CROP */
2995
2996         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
2997                 id = sd->grp_id;
2998                 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
2999                 fp = pvr2_module_update_functions[id];
3000                 if (!fp) continue;
3001                 (*fp)(hdw, sd);
3002         }
3003
3004         if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
3005                 pvr2_hdw_status_poll(hdw);
3006         }
3007 }
3008
3009
3010 /* Figure out if we need to commit control changes.  If so, mark internal
3011    state flags to indicate this fact and return true.  Otherwise do nothing
3012    else and return false. */
3013 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3014 {
3015         unsigned int idx;
3016         struct pvr2_ctrl *cptr;
3017         int value;
3018         int commit_flag = hdw->force_dirty;
3019         char buf[100];
3020         unsigned int bcnt,ccnt;
3021
3022         for (idx = 0; idx < hdw->control_cnt; idx++) {
3023                 cptr = hdw->controls + idx;
3024                 if (!cptr->info->is_dirty) continue;
3025                 if (!cptr->info->is_dirty(cptr)) continue;
3026                 commit_flag = !0;
3027
3028                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3029                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3030                                  cptr->info->name);
3031                 value = 0;
3032                 cptr->info->get_value(cptr,&value);
3033                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3034                                                 buf+bcnt,
3035                                                 sizeof(buf)-bcnt,&ccnt);
3036                 bcnt += ccnt;
3037                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3038                                   get_ctrl_typename(cptr->info->type));
3039                 pvr2_trace(PVR2_TRACE_CTL,
3040                            "/*--TRACE_COMMIT--*/ %.*s",
3041                            bcnt,buf);
3042         }
3043
3044         if (!commit_flag) {
3045                 /* Nothing has changed */
3046                 return 0;
3047         }
3048
3049         hdw->state_pipeline_config = 0;
3050         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3051         pvr2_hdw_state_sched(hdw);
3052
3053         return !0;
3054 }
3055
3056
3057 /* Perform all operations needed to commit all control changes.  This must
3058    be performed in synchronization with the pipeline state and is thus
3059    expected to be called as part of the driver's worker thread.  Return
3060    true if commit successful, otherwise return false to indicate that
3061    commit isn't possible at this time. */
3062 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3063 {
3064         unsigned int idx;
3065         struct pvr2_ctrl *cptr;
3066         int disruptive_change;
3067
3068         if (hdw->input_dirty && hdw->state_pathway_ok &&
3069             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3070               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3071              hdw->pathway_state)) {
3072                 /* Change of mode being asked for... */
3073                 hdw->state_pathway_ok = 0;
3074                 trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3075         }
3076         if (!hdw->state_pathway_ok) {
3077                 /* Can't commit anything until pathway is ok. */
3078                 return 0;
3079         }
3080
3081         /* Handle some required side effects when the video standard is
3082            changed.... */
3083         if (hdw->std_dirty) {
3084                 int nvres;
3085                 int gop_size;
3086                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3087                         nvres = 480;
3088                         gop_size = 15;
3089                 } else {
3090                         nvres = 576;
3091                         gop_size = 12;
3092                 }
3093                 /* Rewrite the vertical resolution to be appropriate to the
3094                    video standard that has been selected. */
3095                 if (nvres != hdw->res_ver_val) {
3096                         hdw->res_ver_val = nvres;
3097                         hdw->res_ver_dirty = !0;
3098                 }
3099                 /* Rewrite the GOP size to be appropriate to the video
3100                    standard that has been selected. */
3101                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3102                         struct v4l2_ext_controls cs;
3103                         struct v4l2_ext_control c1;
3104                         memset(&cs, 0, sizeof(cs));
3105                         memset(&c1, 0, sizeof(c1));
3106                         cs.controls = &c1;
3107                         cs.count = 1;
3108                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3109                         c1.value = gop_size;
3110                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3111                                           VIDIOC_S_EXT_CTRLS);
3112                 }
3113         }
3114
3115         /* The broadcast decoder can only scale down, so if
3116          * res_*_dirty && crop window < output format ==> enlarge crop.
3117          *
3118          * The mpeg encoder receives fields of res_hor_val dots and
3119          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3120          */
3121         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3122                 hdw->cropw_val = hdw->res_hor_val;
3123                 hdw->cropw_dirty = !0;
3124         } else if (hdw->cropw_dirty) {
3125                 hdw->res_hor_dirty = !0;           /* must rescale */
3126                 hdw->res_hor_val = min(720, hdw->cropw_val);
3127         }
3128         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3129                 hdw->croph_val = hdw->res_ver_val;
3130                 hdw->croph_dirty = !0;
3131         } else if (hdw->croph_dirty) {
3132                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3133                 hdw->res_ver_dirty = !0;
3134                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3135         }
3136
3137         /* If any of the below has changed, then we can't do the update
3138            while the pipeline is running.  Pipeline must be paused first
3139            and decoder -> encoder connection be made quiescent before we
3140            can proceed. */
3141         disruptive_change =
3142                 (hdw->std_dirty ||
3143                  hdw->enc_unsafe_stale ||
3144                  hdw->srate_dirty ||
3145                  hdw->res_ver_dirty ||
3146                  hdw->res_hor_dirty ||
3147                  hdw->cropw_dirty ||
3148                  hdw->croph_dirty ||
3149                  hdw->input_dirty ||
3150                  (hdw->active_stream_type != hdw->desired_stream_type));
3151         if (disruptive_change && !hdw->state_pipeline_idle) {
3152                 /* Pipeline is not idle; we can't proceed.  Arrange to
3153                    cause pipeline to stop so that we can try this again
3154                    later.... */
3155                 hdw->state_pipeline_pause = !0;
3156                 return 0;
3157         }
3158
3159         if (hdw->srate_dirty) {
3160                 /* Write new sample rate into control structure since
3161                  * the master copy is stale.  We must track srate
3162                  * separate from the mpeg control structure because
3163                  * other logic also uses this value. */
3164                 struct v4l2_ext_controls cs;
3165                 struct v4l2_ext_control c1;
3166                 memset(&cs,0,sizeof(cs));
3167                 memset(&c1,0,sizeof(c1));
3168                 cs.controls = &c1;
3169                 cs.count = 1;
3170                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3171                 c1.value = hdw->srate_val;
3172                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3173         }
3174
3175         if (hdw->active_stream_type != hdw->desired_stream_type) {
3176                 /* Handle any side effects of stream config here */
3177                 hdw->active_stream_type = hdw->desired_stream_type;
3178         }
3179
3180         if (hdw->hdw_desc->signal_routing_scheme ==
3181             PVR2_ROUTING_SCHEME_GOTVIEW) {
3182                 u32 b;
3183                 /* Handle GOTVIEW audio switching */
3184                 pvr2_hdw_gpio_get_out(hdw,&b);
3185                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3186                         /* Set GPIO 11 */
3187                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3188                 } else {
3189                         /* Clear GPIO 11 */
3190                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3191                 }
3192         }
3193
3194         /* Check and update state for all sub-devices. */
3195         pvr2_subdev_update(hdw);
3196
3197         hdw->tuner_updated = 0;
3198         hdw->force_dirty = 0;
3199         for (idx = 0; idx < hdw->control_cnt; idx++) {
3200                 cptr = hdw->controls + idx;
3201                 if (!cptr->info->clear_dirty) continue;
3202                 cptr->info->clear_dirty(cptr);
3203         }
3204
3205         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3206             hdw->state_encoder_run) {
3207                 /* If encoder isn't running or it can't be touched, then
3208                    this will get worked out later when we start the
3209                    encoder. */
3210                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3211         }
3212
3213         hdw->state_pipeline_config = !0;
3214         /* Hardware state may have changed in a way to cause the cropping
3215            capabilities to have changed.  So mark it stale, which will
3216            cause a later re-fetch. */
3217         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3218         return !0;
3219 }
3220
3221
3222 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3223 {
3224         int fl;
3225         LOCK_TAKE(hdw->big_lock);
3226         fl = pvr2_hdw_commit_setup(hdw);
3227         LOCK_GIVE(hdw->big_lock);
3228         if (!fl) return 0;
3229         return pvr2_hdw_wait(hdw,0);
3230 }
3231
3232
3233 static void pvr2_hdw_worker_poll(struct work_struct *work)
3234 {
3235         int fl = 0;
3236         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3237         LOCK_TAKE(hdw->big_lock); do {
3238                 fl = pvr2_hdw_state_eval(hdw);
3239         } while (0); LOCK_GIVE(hdw->big_lock);
3240         if (fl && hdw->state_func) {
3241                 hdw->state_func(hdw->state_data);
3242         }
3243 }
3244
3245
3246 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3247 {
3248         return wait_event_interruptible(
3249                 hdw->state_wait_data,
3250                 (hdw->state_stale == 0) &&
3251                 (!state || (hdw->master_state != state)));
3252 }
3253
3254
3255 /* Return name for this driver instance */
3256 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3257 {
3258         return hdw->name;
3259 }
3260
3261
3262 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3263 {
3264         return hdw->hdw_desc->description;
3265 }
3266
3267
3268 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3269 {
3270         return hdw->hdw_desc->shortname;
3271 }
3272
3273
3274 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3275 {
3276         int result;
3277         LOCK_TAKE(hdw->ctl_lock); do {
3278                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3279                 result = pvr2_send_request(hdw,
3280                                            hdw->cmd_buffer,1,
3281                                            hdw->cmd_buffer,1);
3282                 if (result < 0) break;
3283                 result = (hdw->cmd_buffer[0] != 0);
3284         } while(0); LOCK_GIVE(hdw->ctl_lock);
3285         return result;
3286 }
3287
3288
3289 /* Execute poll of tuner status */
3290 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3291 {
3292         LOCK_TAKE(hdw->big_lock); do {
3293                 pvr2_hdw_status_poll(hdw);
3294         } while (0); LOCK_GIVE(hdw->big_lock);
3295 }
3296
3297
3298 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3299 {
3300         if (!hdw->cropcap_stale) {
3301                 return 0;
3302         }
3303         pvr2_hdw_status_poll(hdw);
3304         if (hdw->cropcap_stale) {
3305                 return -EIO;
3306         }
3307         return 0;
3308 }
3309
3310
3311 /* Return information about cropping capabilities */
3312 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3313 {
3314         int stat = 0;
3315         LOCK_TAKE(hdw->big_lock);
3316         stat = pvr2_hdw_check_cropcap(hdw);
3317         if (!stat) {
3318                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3319         }
3320         LOCK_GIVE(hdw->big_lock);
3321         return stat;
3322 }
3323
3324
3325 /* Return information about the tuner */
3326 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3327 {
3328         LOCK_TAKE(hdw->big_lock); do {
3329                 if (hdw->tuner_signal_stale) {
3330                         pvr2_hdw_status_poll(hdw);
3331                 }
3332                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3333         } while (0); LOCK_GIVE(hdw->big_lock);
3334         return 0;
3335 }
3336
3337
3338 /* Get handle to video output stream */
3339 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3340 {
3341         return hp->vid_stream;
3342 }
3343
3344
3345 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3346 {
3347         int nr = pvr2_hdw_get_unit_number(hdw);
3348         LOCK_TAKE(hdw->big_lock);
3349         do {
3350                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3351                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3352                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3353                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3354                 pvr2_hdw_state_log_state(hdw);
3355                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3356         } while (0);
3357         LOCK_GIVE(hdw->big_lock);
3358 }
3359
3360
3361 /* Grab EEPROM contents, needed for direct method. */
3362 #define EEPROM_SIZE 8192
3363 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3364 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3365 {
3366         struct i2c_msg msg[2];
3367         u8 *eeprom;
3368         u8 iadd[2];
3369         u8 addr;
3370         u16 eepromSize;
3371         unsigned int offs;
3372         int ret;
3373         int mode16 = 0;
3374         unsigned pcnt,tcnt;
3375         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3376         if (!eeprom) {
3377                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3378                            "Failed to allocate memory"
3379                            " required to read eeprom");
3380                 return NULL;
3381         }
3382
3383         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3384                      hdw->eeprom_addr);
3385         addr = hdw->eeprom_addr;
3386         /* Seems that if the high bit is set, then the *real* eeprom
3387            address is shifted right now bit position (noticed this in
3388            newer PVR USB2 hardware) */
3389         if (addr & 0x80) addr >>= 1;
3390
3391         /* FX2 documentation states that a 16bit-addressed eeprom is
3392            expected if the I2C address is an odd number (yeah, this is
3393            strange but it's what they do) */
3394         mode16 = (addr & 1);
3395         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3396         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3397                      " using %d bit addressing",eepromSize,addr,
3398                      mode16 ? 16 : 8);
3399
3400         msg[0].addr = addr;
3401         msg[0].flags = 0;
3402         msg[0].len = mode16 ? 2 : 1;
3403         msg[0].buf = iadd;
3404         msg[1].addr = addr;
3405         msg[1].flags = I2C_M_RD;
3406
3407         /* We have to do the actual eeprom data fetch ourselves, because
3408            (1) we're only fetching part of the eeprom, and (2) if we were
3409            getting the whole thing our I2C driver can't grab it in one
3410            pass - which is what tveeprom is otherwise going to attempt */
3411         memset(eeprom,0,EEPROM_SIZE);
3412         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3413                 pcnt = 16;
3414                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3415                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3416                 if (mode16) {
3417                         iadd[0] = offs >> 8;
3418                         iadd[1] = offs;
3419                 } else {
3420                         iadd[0] = offs;
3421                 }
3422                 msg[1].len = pcnt;
3423                 msg[1].buf = eeprom+tcnt;
3424                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3425                                         msg,ARRAY_SIZE(msg))) != 2) {
3426                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3427                                    "eeprom fetch set offs err=%d",ret);
3428                         kfree(eeprom);
3429                         return NULL;
3430                 }
3431         }
3432         return eeprom;
3433 }
3434
3435
3436 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3437                                 int mode,
3438                                 int enable_flag)
3439 {
3440         int ret;
3441         u16 address;
3442         unsigned int pipe;
3443         LOCK_TAKE(hdw->big_lock); do {
3444                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3445
3446                 if (!enable_flag) {
3447                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3448                                    "Cleaning up after CPU firmware fetch");
3449                         kfree(hdw->fw_buffer);
3450                         hdw->fw_buffer = NULL;
3451                         hdw->fw_size = 0;
3452                         if (hdw->fw_cpu_flag) {
3453                                 /* Now release the CPU.  It will disconnect
3454                                    and reconnect later. */
3455                                 pvr2_hdw_cpureset_assert(hdw,0);
3456                         }
3457                         break;
3458                 }
3459
3460                 hdw->fw_cpu_flag = (mode != 2);
3461                 if (hdw->fw_cpu_flag) {
3462                         hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3463                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3464                                    "Preparing to suck out CPU firmware"
3465                                    " (size=%u)", hdw->fw_size);
3466                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3467                         if (!hdw->fw_buffer) {
3468                                 hdw->fw_size = 0;
3469                                 break;
3470                         }
3471
3472                         /* We have to hold the CPU during firmware upload. */
3473                         pvr2_hdw_cpureset_assert(hdw,1);
3474
3475                         /* download the firmware from address 0000-1fff in 2048
3476                            (=0x800) bytes chunk. */
3477
3478                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3479                                    "Grabbing CPU firmware");
3480                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3481                         for(address = 0; address < hdw->fw_size;
3482                             address += 0x800) {
3483                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3484                                                       0xa0,0xc0,
3485                                                       address,0,
3486                                                       hdw->fw_buffer+address,
3487                                                       0x800,HZ);
3488                                 if (ret < 0) break;
3489                         }
3490
3491                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3492                                    "Done grabbing CPU firmware");
3493                 } else {
3494                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3495                                    "Sucking down EEPROM contents");
3496                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3497                         if (!hdw->fw_buffer) {
3498                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3499                                            "EEPROM content suck failed.");
3500                                 break;
3501                         }
3502                         hdw->fw_size = EEPROM_SIZE;
3503                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3504                                    "Done sucking down EEPROM contents");
3505                 }
3506
3507         } while (0); LOCK_GIVE(hdw->big_lock);
3508 }
3509
3510
3511 /* Return true if we're in a mode for retrieval CPU firmware */
3512 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3513 {
3514         return hdw->fw_buffer != NULL;
3515 }
3516
3517
3518 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3519                        char *buf,unsigned int cnt)
3520 {
3521         int ret = -EINVAL;
3522         LOCK_TAKE(hdw->big_lock); do {
3523                 if (!buf) break;
3524                 if (!cnt) break;
3525
3526                 if (!hdw->fw_buffer) {
3527                         ret = -EIO;
3528                         break;
3529                 }
3530
3531                 if (offs >= hdw->fw_size) {
3532                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3533                                    "Read firmware data offs=%d EOF",
3534                                    offs);
3535                         ret = 0;
3536                         break;
3537                 }
3538
3539                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3540
3541                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3542
3543                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3544                            "Read firmware data offs=%d cnt=%d",
3545                            offs,cnt);
3546                 ret = cnt;
3547         } while (0); LOCK_GIVE(hdw->big_lock);
3548
3549         return ret;
3550 }
3551
3552
3553 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3554                                   enum pvr2_v4l_type index)
3555 {
3556         switch (index) {
3557         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3558         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3559         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3560         default: return -1;
3561         }
3562 }
3563
3564
3565 /* Store a v4l minor device number */
3566 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3567                                      enum pvr2_v4l_type index,int v)
3568 {
3569         switch (index) {
3570         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break;
3571         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break;
3572         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break;
3573         default: break;
3574         }
3575 }
3576
3577
3578 static void pvr2_ctl_write_complete(struct urb *urb)
3579 {
3580         struct pvr2_hdw *hdw = urb->context;
3581         hdw->ctl_write_pend_flag = 0;
3582         if (hdw->ctl_read_pend_flag) return;
3583         complete(&hdw->ctl_done);
3584 }
3585
3586
3587 static void pvr2_ctl_read_complete(struct urb *urb)
3588 {
3589         struct pvr2_hdw *hdw = urb->context;
3590         hdw->ctl_read_pend_flag = 0;
3591         if (hdw->ctl_write_pend_flag) return;
3592         complete(&hdw->ctl_done);
3593 }
3594
3595
3596 static void pvr2_ctl_timeout(unsigned long data)
3597 {
3598         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3599         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3600                 hdw->ctl_timeout_flag = !0;
3601                 if (hdw->ctl_write_pend_flag)
3602                         usb_unlink_urb(hdw->ctl_write_urb);
3603                 if (hdw->ctl_read_pend_flag)
3604                         usb_unlink_urb(hdw->ctl_read_urb);
3605         }
3606 }
3607
3608
3609 /* Issue a command and get a response from the device.  This extended
3610    version includes a probe flag (which if set means that device errors
3611    should not be logged or treated as fatal) and a timeout in jiffies.
3612    This can be used to non-lethally probe the health of endpoint 1. */
3613 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3614                                 unsigned int timeout,int probe_fl,
3615                                 void *write_data,unsigned int write_len,
3616                                 void *read_data,unsigned int read_len)
3617 {
3618         unsigned int idx;
3619         int status = 0;
3620         struct timer_list timer;
3621         if (!hdw->ctl_lock_held) {
3622                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3623                            "Attempted to execute control transfer"
3624                            " without lock!!");
3625                 return -EDEADLK;
3626         }
3627         if (!hdw->flag_ok && !probe_fl) {
3628                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3629                            "Attempted to execute control transfer"
3630                            " when device not ok");
3631                 return -EIO;
3632         }
3633         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3634                 if (!probe_fl) {
3635                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3636                                    "Attempted to execute control transfer"
3637                                    " when USB is disconnected");
3638                 }
3639                 return -ENOTTY;
3640         }
3641
3642         /* Ensure that we have sane parameters */
3643         if (!write_data) write_len = 0;
3644         if (!read_data) read_len = 0;
3645         if (write_len > PVR2_CTL_BUFFSIZE) {
3646                 pvr2_trace(
3647                         PVR2_TRACE_ERROR_LEGS,
3648                         "Attempted to execute %d byte"
3649                         " control-write transfer (limit=%d)",
3650                         write_len,PVR2_CTL_BUFFSIZE);
3651                 return -EINVAL;
3652         }
3653         if (read_len > PVR2_CTL_BUFFSIZE) {
3654                 pvr2_trace(
3655                         PVR2_TRACE_ERROR_LEGS,
3656                         "Attempted to execute %d byte"
3657                         " control-read transfer (limit=%d)",
3658                         write_len,PVR2_CTL_BUFFSIZE);
3659                 return -EINVAL;
3660         }
3661         if ((!write_len) && (!read_len)) {
3662                 pvr2_trace(
3663                         PVR2_TRACE_ERROR_LEGS,
3664                         "Attempted to execute null control transfer?");
3665                 return -EINVAL;
3666         }
3667
3668
3669         hdw->cmd_debug_state = 1;
3670         if (write_len && write_data)
3671                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3672         else
3673                 hdw->cmd_debug_code = 0;
3674         hdw->cmd_debug_write_len = write_len;
3675         hdw->cmd_debug_read_len = read_len;
3676
3677         /* Initialize common stuff */
3678         init_completion(&hdw->ctl_done);
3679         hdw->ctl_timeout_flag = 0;
3680         hdw->ctl_write_pend_flag = 0;
3681         hdw->ctl_read_pend_flag = 0;
3682         setup_timer(&timer, pvr2_ctl_timeout, (unsigned long)hdw);
3683         timer.expires = jiffies + timeout;
3684
3685         if (write_len && write_data) {
3686                 hdw->cmd_debug_state = 2;
3687                 /* Transfer write data to internal buffer */
3688                 for (idx = 0; idx < write_len; idx++) {
3689                         hdw->ctl_write_buffer[idx] =
3690                                 ((unsigned char *)write_data)[idx];
3691                 }
3692                 /* Initiate a write request */
3693                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3694                                   hdw->usb_dev,
3695                                   usb_sndbulkpipe(hdw->usb_dev,
3696                                                   PVR2_CTL_WRITE_ENDPOINT),
3697                                   hdw->ctl_write_buffer,
3698                                   write_len,
3699                                   pvr2_ctl_write_complete,
3700                                   hdw);
3701                 hdw->ctl_write_urb->actual_length = 0;
3702                 hdw->ctl_write_pend_flag = !0;
3703                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3704                 if (status < 0) {
3705                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3706                                    "Failed to submit write-control"
3707                                    " URB status=%d",status);
3708                         hdw->ctl_write_pend_flag = 0;
3709                         goto done;
3710                 }
3711         }
3712
3713         if (read_len) {
3714                 hdw->cmd_debug_state = 3;
3715                 memset(hdw->ctl_read_buffer,0x43,read_len);
3716                 /* Initiate a read request */
3717                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3718                                   hdw->usb_dev,
3719                                   usb_rcvbulkpipe(hdw->usb_dev,
3720                                                   PVR2_CTL_READ_ENDPOINT),
3721                                   hdw->ctl_read_buffer,
3722                                   read_len,
3723                                   pvr2_ctl_read_complete,
3724                                   hdw);
3725                 hdw->ctl_read_urb->actual_length = 0;
3726                 hdw->ctl_read_pend_flag = !0;
3727                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3728                 if (status < 0) {
3729                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3730                                    "Failed to submit read-control"
3731                                    " URB status=%d",status);
3732                         hdw->ctl_read_pend_flag = 0;
3733                         goto done;
3734                 }
3735         }
3736
3737         /* Start timer */
3738         add_timer(&timer);
3739
3740         /* Now wait for all I/O to complete */
3741         hdw->cmd_debug_state = 4;
3742         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3743                 wait_for_completion(&hdw->ctl_done);
3744         }
3745         hdw->cmd_debug_state = 5;
3746
3747         /* Stop timer */
3748         del_timer_sync(&timer);
3749
3750         hdw->cmd_debug_state = 6;
3751         status = 0;
3752
3753         if (hdw->ctl_timeout_flag) {
3754                 status = -ETIMEDOUT;
3755                 if (!probe_fl) {
3756                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3757                                    "Timed out control-write");
3758                 }
3759                 goto done;
3760         }
3761
3762         if (write_len) {
3763                 /* Validate results of write request */
3764                 if ((hdw->ctl_write_urb->status != 0) &&
3765                     (hdw->ctl_write_urb->status != -ENOENT) &&
3766                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3767                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3768                         /* USB subsystem is reporting some kind of failure
3769                            on the write */
3770                         status = hdw->ctl_write_urb->status;
3771                         if (!probe_fl) {
3772                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3773                                            "control-write URB failure,"
3774                                            " status=%d",
3775                                            status);
3776                         }
3777                         goto done;
3778                 }
3779                 if (hdw->ctl_write_urb->actual_length < write_len) {
3780                         /* Failed to write enough data */
3781                         status = -EIO;
3782                         if (!probe_fl) {
3783                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3784                                            "control-write URB short,"
3785                                            " expected=%d got=%d",
3786                                            write_len,
3787                                            hdw->ctl_write_urb->actual_length);
3788                         }
3789                         goto done;
3790                 }
3791         }
3792         if (read_len && read_data) {
3793                 /* Validate results of read request */
3794                 if ((hdw->ctl_read_urb->status != 0) &&
3795                     (hdw->ctl_read_urb->status != -ENOENT) &&
3796                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3797                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3798                         /* USB subsystem is reporting some kind of failure
3799                            on the read */
3800                         status = hdw->ctl_read_urb->status;
3801                         if (!probe_fl) {
3802                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3803                                            "control-read URB failure,"
3804                                            " status=%d",
3805                                            status);
3806                         }
3807                         goto done;
3808                 }
3809                 if (hdw->ctl_read_urb->actual_length < read_len) {
3810                         /* Failed to read enough data */
3811                         status = -EIO;
3812                         if (!probe_fl) {
3813                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3814                                            "control-read URB short,"
3815                                            " expected=%d got=%d",
3816                                            read_len,
3817                                            hdw->ctl_read_urb->actual_length);
3818                         }
3819                         goto done;
3820                 }
3821                 /* Transfer retrieved data out from internal buffer */
3822                 for (idx = 0; idx < read_len; idx++) {
3823                         ((unsigned char *)read_data)[idx] =
3824                                 hdw->ctl_read_buffer[idx];
3825                 }
3826         }
3827
3828  done:
3829
3830         hdw->cmd_debug_state = 0;
3831         if ((status < 0) && (!probe_fl)) {
3832                 pvr2_hdw_render_useless(hdw);
3833         }
3834         return status;
3835 }
3836
3837
3838 int pvr2_send_request(struct pvr2_hdw *hdw,
3839                       void *write_data,unsigned int write_len,
3840                       void *read_data,unsigned int read_len)
3841 {
3842         return pvr2_send_request_ex(hdw,HZ*4,0,
3843                                     write_data,write_len,
3844                                     read_data,read_len);
3845 }
3846
3847
3848 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3849 {
3850         int ret;
3851         unsigned int cnt = 1;
3852         unsigned int args = 0;
3853         LOCK_TAKE(hdw->ctl_lock);
3854         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3855         args = (cmdcode >> 8) & 0xffu;
3856         args = (args > 2) ? 2 : args;
3857         if (args) {
3858                 cnt += args;
3859                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3860                 if (args > 1) {
3861                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3862                 }
3863         }
3864         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3865                 unsigned int idx;
3866                 unsigned int ccnt,bcnt;
3867                 char tbuf[50];
3868                 cmdcode &= 0xffu;
3869                 bcnt = 0;
3870                 ccnt = scnprintf(tbuf+bcnt,
3871                                  sizeof(tbuf)-bcnt,
3872                                  "Sending FX2 command 0x%x",cmdcode);
3873                 bcnt += ccnt;
3874                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3875                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3876                                 ccnt = scnprintf(tbuf+bcnt,
3877                                                  sizeof(tbuf)-bcnt,
3878                                                  " \"%s\"",
3879                                                  pvr2_fx2cmd_desc[idx].desc);
3880                                 bcnt += ccnt;
3881                                 break;
3882                         }
3883                 }
3884                 if (args) {
3885                         ccnt = scnprintf(tbuf+bcnt,
3886                                          sizeof(tbuf)-bcnt,
3887                                          " (%u",hdw->cmd_buffer[1]);
3888                         bcnt += ccnt;
3889                         if (args > 1) {
3890                                 ccnt = scnprintf(tbuf+bcnt,
3891                                                  sizeof(tbuf)-bcnt,
3892                                                  ",%u",hdw->cmd_buffer[2]);
3893                                 bcnt += ccnt;
3894                         }
3895                         ccnt = scnprintf(tbuf+bcnt,
3896                                          sizeof(tbuf)-bcnt,
3897                                          ")");
3898                         bcnt += ccnt;
3899                 }
3900                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3901         }
3902         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3903         LOCK_GIVE(hdw->ctl_lock);
3904         return ret;
3905 }
3906
3907
3908 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3909 {
3910         int ret;
3911
3912         LOCK_TAKE(hdw->ctl_lock);
3913
3914         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3915         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3916         hdw->cmd_buffer[5] = 0;
3917         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3918         hdw->cmd_buffer[7] = reg & 0xff;
3919
3920
3921         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3922
3923         LOCK_GIVE(hdw->ctl_lock);
3924
3925         return ret;
3926 }
3927
3928
3929 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3930 {
3931         int ret = 0;
3932
3933         LOCK_TAKE(hdw->ctl_lock);
3934
3935         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3936         hdw->cmd_buffer[1] = 0;
3937         hdw->cmd_buffer[2] = 0;
3938         hdw->cmd_buffer[3] = 0;
3939         hdw->cmd_buffer[4] = 0;
3940         hdw->cmd_buffer[5] = 0;
3941         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3942         hdw->cmd_buffer[7] = reg & 0xff;
3943
3944         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3945         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3946
3947         LOCK_GIVE(hdw->ctl_lock);
3948
3949         return ret;
3950 }
3951
3952
3953 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3954 {
3955         if (!hdw->flag_ok) return;
3956         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3957                    "Device being rendered inoperable");
3958         if (hdw->vid_stream) {
3959                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3960         }
3961         hdw->flag_ok = 0;
3962         trace_stbit("flag_ok",hdw->flag_ok);
3963         pvr2_hdw_state_sched(hdw);
3964 }
3965
3966
3967 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3968 {
3969         int ret;
3970         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3971         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3972         if (ret == 0) {
3973                 ret = usb_reset_device(hdw->usb_dev);
3974                 usb_unlock_device(hdw->usb_dev);
3975         } else {
3976                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3977                            "Failed to lock USB device ret=%d",ret);
3978         }
3979         if (init_pause_msec) {
3980                 pvr2_trace(PVR2_TRACE_INFO,
3981                            "Waiting %u msec for hardware to settle",
3982                            init_pause_msec);
3983                 msleep(init_pause_msec);
3984         }
3985
3986 }
3987
3988
3989 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3990 {
3991         char *da;
3992         unsigned int pipe;
3993         int ret;
3994
3995         if (!hdw->usb_dev) return;
3996
3997         da = kmalloc(16, GFP_KERNEL);
3998
3999         if (da == NULL) {
4000                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4001                            "Unable to allocate memory to control CPU reset");
4002                 return;
4003         }
4004
4005         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4006
4007         da[0] = val ? 0x01 : 0x00;
4008
4009         /* Write the CPUCS register on the 8051.  The lsb of the register
4010            is the reset bit; a 1 asserts reset while a 0 clears it. */
4011         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4012         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4013         if (ret < 0) {
4014                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4015                            "cpureset_assert(%d) error=%d",val,ret);
4016                 pvr2_hdw_render_useless(hdw);
4017         }
4018
4019         kfree(da);
4020 }
4021
4022
4023 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4024 {
4025         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4026 }
4027
4028
4029 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4030 {
4031         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4032 }
4033
4034
4035
4036 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4037 {
4038         pvr2_trace(PVR2_TRACE_INIT,
4039                    "Requesting decoder reset");
4040         if (hdw->decoder_client_id) {
4041                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4042                                      core, reset, 0);
4043                 pvr2_hdw_cx25840_vbi_hack(hdw);
4044                 return 0;
4045         }
4046         pvr2_trace(PVR2_TRACE_INIT,
4047                    "Unable to reset decoder: nothing attached");
4048         return -ENOTTY;
4049 }
4050
4051
4052 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4053 {
4054         hdw->flag_ok = !0;
4055         return pvr2_issue_simple_cmd(hdw,
4056                                      FX2CMD_HCW_DEMOD_RESETIN |
4057                                      (1 << 8) |
4058                                      ((onoff ? 1 : 0) << 16));
4059 }
4060
4061
4062 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4063 {
4064         hdw->flag_ok = !0;
4065         return pvr2_issue_simple_cmd(hdw,(onoff ?
4066                                           FX2CMD_ONAIR_DTV_POWER_ON :
4067                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4068 }
4069
4070
4071 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4072                                                 int onoff)
4073 {
4074         return pvr2_issue_simple_cmd(hdw,(onoff ?
4075                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4076                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4077 }
4078
4079
4080 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4081 {
4082         int cmode;
4083         /* Compare digital/analog desired setting with current setting.  If
4084            they don't match, fix it... */
4085         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4086         if (cmode == hdw->pathway_state) {
4087                 /* They match; nothing to do */
4088                 return;
4089         }
4090
4091         switch (hdw->hdw_desc->digital_control_scheme) {
4092         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4093                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4094                 if (cmode == PVR2_PATHWAY_ANALOG) {
4095                         /* If moving to analog mode, also force the decoder
4096                            to reset.  If no decoder is attached, then it's
4097                            ok to ignore this because if/when the decoder
4098                            attaches, it will reset itself at that time. */
4099                         pvr2_hdw_cmd_decoder_reset(hdw);
4100                 }
4101                 break;
4102         case PVR2_DIGITAL_SCHEME_ONAIR:
4103                 /* Supposedly we should always have the power on whether in
4104                    digital or analog mode.  But for now do what appears to
4105                    work... */
4106                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4107                 break;
4108         default: break;
4109         }
4110
4111         pvr2_hdw_untrip_unlocked(hdw);
4112         hdw->pathway_state = cmode;
4113 }
4114
4115
4116 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4117 {
4118         /* change some GPIO data
4119          *
4120          * note: bit d7 of dir appears to control the LED,
4121          * so we shut it off here.
4122          *
4123          */
4124         if (onoff) {
4125                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4126         } else {
4127                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4128         }
4129         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4130 }
4131
4132
4133 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4134
4135 static led_method_func led_methods[] = {
4136         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4137 };
4138
4139
4140 /* Toggle LED */
4141 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4142 {
4143         unsigned int scheme_id;
4144         led_method_func fp;
4145
4146         if ((!onoff) == (!hdw->led_on)) return;
4147
4148         hdw->led_on = onoff != 0;
4149
4150         scheme_id = hdw->hdw_desc->led_scheme;
4151         if (scheme_id < ARRAY_SIZE(led_methods)) {
4152                 fp = led_methods[scheme_id];
4153         } else {
4154                 fp = NULL;
4155         }
4156
4157         if (fp) (*fp)(hdw,onoff);
4158 }
4159
4160
4161 /* Stop / start video stream transport */
4162 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4163 {
4164         int ret;
4165
4166         /* If we're in analog mode, then just issue the usual analog
4167            command. */
4168         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4169                 return pvr2_issue_simple_cmd(hdw,
4170                                              (runFl ?
4171                                               FX2CMD_STREAMING_ON :
4172                                               FX2CMD_STREAMING_OFF));
4173                 /*Note: Not reached */
4174         }
4175
4176         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4177                 /* Whoops, we don't know what mode we're in... */
4178                 return -EINVAL;
4179         }
4180
4181         /* To get here we have to be in digital mode.  The mechanism here
4182            is unfortunately different for different vendors.  So we switch
4183            on the device's digital scheme attribute in order to figure out
4184            what to do. */
4185         switch (hdw->hdw_desc->digital_control_scheme) {
4186         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4187                 return pvr2_issue_simple_cmd(hdw,
4188                                              (runFl ?
4189                                               FX2CMD_HCW_DTV_STREAMING_ON :
4190                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4191         case PVR2_DIGITAL_SCHEME_ONAIR:
4192                 ret = pvr2_issue_simple_cmd(hdw,
4193                                             (runFl ?
4194                                              FX2CMD_STREAMING_ON :
4195                                              FX2CMD_STREAMING_OFF));
4196                 if (ret) return ret;
4197                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4198         default:
4199                 return -EINVAL;
4200         }
4201 }
4202
4203
4204 /* Evaluate whether or not state_pathway_ok can change */
4205 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4206 {
4207         if (hdw->state_pathway_ok) {
4208                 /* Nothing to do if pathway is already ok */
4209                 return 0;
4210         }
4211         if (!hdw->state_pipeline_idle) {
4212                 /* Not allowed to change anything if pipeline is not idle */
4213                 return 0;
4214         }
4215         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4216         hdw->state_pathway_ok = !0;
4217         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4218         return !0;
4219 }
4220
4221
4222 /* Evaluate whether or not state_encoder_ok can change */
4223 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4224 {
4225         if (hdw->state_encoder_ok) return 0;
4226         if (hdw->flag_tripped) return 0;
4227         if (hdw->state_encoder_run) return 0;
4228         if (hdw->state_encoder_config) return 0;
4229         if (hdw->state_decoder_run) return 0;
4230         if (hdw->state_usbstream_run) return 0;
4231         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4232                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4233         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4234                 return 0;
4235         }
4236
4237         if (pvr2_upload_firmware2(hdw) < 0) {
4238                 hdw->flag_tripped = !0;
4239                 trace_stbit("flag_tripped",hdw->flag_tripped);
4240                 return !0;
4241         }
4242         hdw->state_encoder_ok = !0;
4243         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4244         return !0;
4245 }
4246
4247
4248 /* Evaluate whether or not state_encoder_config can change */
4249 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4250 {
4251         if (hdw->state_encoder_config) {
4252                 if (hdw->state_encoder_ok) {
4253                         if (hdw->state_pipeline_req &&
4254                             !hdw->state_pipeline_pause) return 0;
4255                 }
4256                 hdw->state_encoder_config = 0;
4257                 hdw->state_encoder_waitok = 0;
4258                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4259                 /* paranoia - solve race if timer just completed */
4260                 del_timer_sync(&hdw->encoder_wait_timer);
4261         } else {
4262                 if (!hdw->state_pathway_ok ||
4263                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4264                     !hdw->state_encoder_ok ||
4265                     !hdw->state_pipeline_idle ||
4266                     hdw->state_pipeline_pause ||
4267                     !hdw->state_pipeline_req ||
4268                     !hdw->state_pipeline_config) {
4269                         /* We must reset the enforced wait interval if
4270                            anything has happened that might have disturbed
4271                            the encoder.  This should be a rare case. */
4272                         if (timer_pending(&hdw->encoder_wait_timer)) {
4273                                 del_timer_sync(&hdw->encoder_wait_timer);
4274                         }
4275                         if (hdw->state_encoder_waitok) {
4276                                 /* Must clear the state - therefore we did
4277                                    something to a state bit and must also
4278                                    return true. */
4279                                 hdw->state_encoder_waitok = 0;
4280                                 trace_stbit("state_encoder_waitok",
4281                                             hdw->state_encoder_waitok);
4282                                 return !0;
4283                         }
4284                         return 0;
4285                 }
4286                 if (!hdw->state_encoder_waitok) {
4287                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4288                                 /* waitok flag wasn't set and timer isn't
4289                                    running.  Check flag once more to avoid
4290                                    a race then start the timer.  This is
4291                                    the point when we measure out a minimal
4292                                    quiet interval before doing something to
4293                                    the encoder. */
4294                                 if (!hdw->state_encoder_waitok) {
4295                                         hdw->encoder_wait_timer.expires =
4296                                                 jiffies + msecs_to_jiffies(
4297                                                 TIME_MSEC_ENCODER_WAIT);
4298                                         add_timer(&hdw->encoder_wait_timer);
4299                                 }
4300                         }
4301                         /* We can't continue until we know we have been
4302                            quiet for the interval measured by this
4303                            timer. */
4304                         return 0;
4305                 }
4306                 pvr2_encoder_configure(hdw);
4307                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4308         }
4309         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4310         return !0;
4311 }
4312
4313
4314 /* Return true if the encoder should not be running. */
4315 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4316 {
4317         if (!hdw->state_encoder_ok) {
4318                 /* Encoder isn't healthy at the moment, so stop it. */
4319                 return !0;
4320         }
4321         if (!hdw->state_pathway_ok) {
4322                 /* Mode is not understood at the moment (i.e. it wants to
4323                    change), so encoder must be stopped. */
4324                 return !0;
4325         }
4326
4327         switch (hdw->pathway_state) {
4328         case PVR2_PATHWAY_ANALOG:
4329                 if (!hdw->state_decoder_run) {
4330                         /* We're in analog mode and the decoder is not
4331                            running; thus the encoder should be stopped as
4332                            well. */
4333                         return !0;
4334                 }
4335                 break;
4336         case PVR2_PATHWAY_DIGITAL:
4337                 if (hdw->state_encoder_runok) {
4338                         /* This is a funny case.  We're in digital mode so
4339                            really the encoder should be stopped.  However
4340                            if it really is running, only kill it after
4341                            runok has been set.  This gives a chance for the
4342                            onair quirk to function (encoder must run
4343                            briefly first, at least once, before onair
4344                            digital streaming can work). */
4345                         return !0;
4346                 }
4347                 break;
4348         default:
4349                 /* Unknown mode; so encoder should be stopped. */
4350                 return !0;
4351         }
4352
4353         /* If we get here, we haven't found a reason to stop the
4354            encoder. */
4355         return 0;
4356 }
4357
4358
4359 /* Return true if the encoder should be running. */
4360 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4361 {
4362         if (!hdw->state_encoder_ok) {
4363                 /* Don't run the encoder if it isn't healthy... */
4364                 return 0;
4365         }
4366         if (!hdw->state_pathway_ok) {
4367                 /* Don't run the encoder if we don't (yet) know what mode
4368                    we need to be in... */
4369                 return 0;
4370         }
4371
4372         switch (hdw->pathway_state) {
4373         case PVR2_PATHWAY_ANALOG:
4374                 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
4375                         /* In analog mode, if the decoder is running, then
4376                            run the encoder. */
4377                         return !0;
4378                 }
4379                 break;
4380         case PVR2_PATHWAY_DIGITAL:
4381                 if ((hdw->hdw_desc->digital_control_scheme ==
4382                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4383                     !hdw->state_encoder_runok) {
4384                         /* This is a quirk.  OnAir hardware won't stream
4385                            digital until the encoder has been run at least
4386                            once, for a minimal period of time (empiricially
4387                            measured to be 1/4 second).  So if we're on
4388                            OnAir hardware and the encoder has never been
4389                            run at all, then start the encoder.  Normal
4390                            state machine logic in the driver will
4391                            automatically handle the remaining bits. */
4392                         return !0;
4393                 }
4394                 break;
4395         default:
4396                 /* For completeness (unknown mode; encoder won't run ever) */
4397                 break;
4398         }
4399         /* If we get here, then we haven't found any reason to run the
4400            encoder, so don't run it. */
4401         return 0;
4402 }
4403
4404
4405 /* Evaluate whether or not state_encoder_run can change */
4406 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4407 {
4408         if (hdw->state_encoder_run) {
4409                 if (!state_check_disable_encoder_run(hdw)) return 0;
4410                 if (hdw->state_encoder_ok) {
4411                         del_timer_sync(&hdw->encoder_run_timer);
4412                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4413                 }
4414                 hdw->state_encoder_run = 0;
4415         } else {
4416                 if (!state_check_enable_encoder_run(hdw)) return 0;
4417                 if (pvr2_encoder_start(hdw) < 0) return !0;
4418                 hdw->state_encoder_run = !0;
4419                 if (!hdw->state_encoder_runok) {
4420                         hdw->encoder_run_timer.expires = jiffies +
4421                                  msecs_to_jiffies(TIME_MSEC_ENCODER_OK);
4422                         add_timer(&hdw->encoder_run_timer);
4423                 }
4424         }
4425         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4426         return !0;
4427 }
4428
4429
4430 /* Timeout function for quiescent timer. */
4431 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4432 {
4433         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4434         hdw->state_decoder_quiescent = !0;
4435         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4436         hdw->state_stale = !0;
4437         schedule_work(&hdw->workpoll);
4438 }
4439
4440
4441 /* Timeout function for decoder stabilization timer. */
4442 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4443 {
4444         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4445         hdw->state_decoder_ready = !0;
4446         trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4447         hdw->state_stale = !0;
4448         schedule_work(&hdw->workpoll);
4449 }
4450
4451
4452 /* Timeout function for encoder wait timer. */
4453 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4454 {
4455         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4456         hdw->state_encoder_waitok = !0;
4457         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4458         hdw->state_stale = !0;
4459         schedule_work(&hdw->workpoll);
4460 }
4461
4462
4463 /* Timeout function for encoder run timer. */
4464 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4465 {
4466         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4467         if (!hdw->state_encoder_runok) {
4468                 hdw->state_encoder_runok = !0;
4469                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4470                 hdw->state_stale = !0;
4471                 schedule_work(&hdw->workpoll);
4472         }
4473 }
4474
4475
4476 /* Evaluate whether or not state_decoder_run can change */
4477 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4478 {
4479         if (hdw->state_decoder_run) {
4480                 if (hdw->state_encoder_ok) {
4481                         if (hdw->state_pipeline_req &&
4482                             !hdw->state_pipeline_pause &&
4483                             hdw->state_pathway_ok) return 0;
4484                 }
4485                 if (!hdw->flag_decoder_missed) {
4486                         pvr2_decoder_enable(hdw,0);
4487                 }
4488                 hdw->state_decoder_quiescent = 0;
4489                 hdw->state_decoder_run = 0;
4490                 /* paranoia - solve race if timer(s) just completed */
4491                 del_timer_sync(&hdw->quiescent_timer);
4492                 /* Kill the stabilization timer, in case we're killing the
4493                    encoder before the previous stabilization interval has
4494                    been properly timed. */
4495                 del_timer_sync(&hdw->decoder_stabilization_timer);
4496                 hdw->state_decoder_ready = 0;
4497         } else {
4498                 if (!hdw->state_decoder_quiescent) {
4499                         if (!timer_pending(&hdw->quiescent_timer)) {
4500                                 /* We don't do something about the
4501                                    quiescent timer until right here because
4502                                    we also want to catch cases where the
4503                                    decoder was already not running (like
4504                                    after initialization) as opposed to
4505                                    knowing that we had just stopped it.
4506                                    The second flag check is here to cover a
4507                                    race - the timer could have run and set
4508                                    this flag just after the previous check
4509                                    but before we did the pending check. */
4510                                 if (!hdw->state_decoder_quiescent) {
4511                                         hdw->quiescent_timer.expires =
4512                                                 jiffies + msecs_to_jiffies(
4513                                                 TIME_MSEC_DECODER_WAIT);
4514                                         add_timer(&hdw->quiescent_timer);
4515                                 }
4516                         }
4517                         /* Don't allow decoder to start again until it has
4518                            been quiesced first.  This little detail should
4519                            hopefully further stabilize the encoder. */
4520                         return 0;
4521                 }
4522                 if (!hdw->state_pathway_ok ||
4523                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4524                     !hdw->state_pipeline_req ||
4525                     hdw->state_pipeline_pause ||
4526                     !hdw->state_pipeline_config ||
4527                     !hdw->state_encoder_config ||
4528                     !hdw->state_encoder_ok) return 0;
4529                 del_timer_sync(&hdw->quiescent_timer);
4530                 if (hdw->flag_decoder_missed) return 0;
4531                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4532                 hdw->state_decoder_quiescent = 0;
4533                 hdw->state_decoder_ready = 0;
4534                 hdw->state_decoder_run = !0;
4535                 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4536                         hdw->decoder_stabilization_timer.expires =
4537                                 jiffies + msecs_to_jiffies(
4538                                 TIME_MSEC_DECODER_STABILIZATION_WAIT);
4539                         add_timer(&hdw->decoder_stabilization_timer);
4540                 } else {
4541                         hdw->state_decoder_ready = !0;
4542                 }
4543         }
4544         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4545         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4546         trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4547         return !0;
4548 }
4549
4550
4551 /* Evaluate whether or not state_usbstream_run can change */
4552 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4553 {
4554         if (hdw->state_usbstream_run) {
4555                 int fl = !0;
4556                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4557                         fl = (hdw->state_encoder_ok &&
4558                               hdw->state_encoder_run);
4559                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4560                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4561                         fl = hdw->state_encoder_ok;
4562                 }
4563                 if (fl &&
4564                     hdw->state_pipeline_req &&
4565                     !hdw->state_pipeline_pause &&
4566                     hdw->state_pathway_ok) {
4567                         return 0;
4568                 }
4569                 pvr2_hdw_cmd_usbstream(hdw,0);
4570                 hdw->state_usbstream_run = 0;
4571         } else {
4572                 if (!hdw->state_pipeline_req ||
4573                     hdw->state_pipeline_pause ||
4574                     !hdw->state_pathway_ok) return 0;
4575                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4576                         if (!hdw->state_encoder_ok ||
4577                             !hdw->state_encoder_run) return 0;
4578                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4579                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4580                         if (!hdw->state_encoder_ok) return 0;
4581                         if (hdw->state_encoder_run) return 0;
4582                         if (hdw->hdw_desc->digital_control_scheme ==
4583                             PVR2_DIGITAL_SCHEME_ONAIR) {
4584                                 /* OnAir digital receivers won't stream
4585                                    unless the analog encoder has run first.
4586                                    Why?  I have no idea.  But don't even
4587                                    try until we know the analog side is
4588                                    known to have run. */
4589                                 if (!hdw->state_encoder_runok) return 0;
4590                         }
4591                 }
4592                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4593                 hdw->state_usbstream_run = !0;
4594         }
4595         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4596         return !0;
4597 }
4598
4599
4600 /* Attempt to configure pipeline, if needed */
4601 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4602 {
4603         if (hdw->state_pipeline_config ||
4604             hdw->state_pipeline_pause) return 0;
4605         pvr2_hdw_commit_execute(hdw);
4606         return !0;
4607 }
4608
4609
4610 /* Update pipeline idle and pipeline pause tracking states based on other
4611    inputs.  This must be called whenever the other relevant inputs have
4612    changed. */
4613 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4614 {
4615         unsigned int st;
4616         int updatedFl = 0;
4617         /* Update pipeline state */
4618         st = !(hdw->state_encoder_run ||
4619                hdw->state_decoder_run ||
4620                hdw->state_usbstream_run ||
4621                (!hdw->state_decoder_quiescent));
4622         if (!st != !hdw->state_pipeline_idle) {
4623                 hdw->state_pipeline_idle = st;
4624                 updatedFl = !0;
4625         }
4626         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4627                 hdw->state_pipeline_pause = 0;
4628                 updatedFl = !0;
4629         }
4630         return updatedFl;
4631 }
4632
4633
4634 typedef int (*state_eval_func)(struct pvr2_hdw *);
4635
4636 /* Set of functions to be run to evaluate various states in the driver. */
4637 static const state_eval_func eval_funcs[] = {
4638         state_eval_pathway_ok,
4639         state_eval_pipeline_config,
4640         state_eval_encoder_ok,
4641         state_eval_encoder_config,
4642         state_eval_decoder_run,
4643         state_eval_encoder_run,
4644         state_eval_usbstream_run,
4645 };
4646
4647
4648 /* Process various states and return true if we did anything interesting. */
4649 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4650 {
4651         unsigned int i;
4652         int state_updated = 0;
4653         int check_flag;
4654
4655         if (!hdw->state_stale) return 0;
4656         if ((hdw->fw1_state != FW1_STATE_OK) ||
4657             !hdw->flag_ok) {
4658                 hdw->state_stale = 0;
4659                 return !0;
4660         }
4661         /* This loop is the heart of the entire driver.  It keeps trying to
4662            evaluate various bits of driver state until nothing changes for
4663            one full iteration.  Each "bit of state" tracks some global
4664            aspect of the driver, e.g. whether decoder should run, if
4665            pipeline is configured, usb streaming is on, etc.  We separately
4666            evaluate each of those questions based on other driver state to
4667            arrive at the correct running configuration. */
4668         do {
4669                 check_flag = 0;
4670                 state_update_pipeline_state(hdw);
4671                 /* Iterate over each bit of state */
4672                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4673                         if ((*eval_funcs[i])(hdw)) {
4674                                 check_flag = !0;
4675                                 state_updated = !0;
4676                                 state_update_pipeline_state(hdw);
4677                         }
4678                 }
4679         } while (check_flag && hdw->flag_ok);
4680         hdw->state_stale = 0;
4681         trace_stbit("state_stale",hdw->state_stale);
4682         return state_updated;
4683 }
4684
4685
4686 static unsigned int print_input_mask(unsigned int msk,
4687                                      char *buf,unsigned int acnt)
4688 {
4689         unsigned int idx,ccnt;
4690         unsigned int tcnt = 0;
4691         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4692                 if (!((1 << idx) & msk)) continue;
4693                 ccnt = scnprintf(buf+tcnt,
4694                                  acnt-tcnt,
4695                                  "%s%s",
4696                                  (tcnt ? ", " : ""),
4697                                  control_values_input[idx]);
4698                 tcnt += ccnt;
4699         }
4700         return tcnt;
4701 }
4702
4703
4704 static const char *pvr2_pathway_state_name(int id)
4705 {
4706         switch (id) {
4707         case PVR2_PATHWAY_ANALOG: return "analog";
4708         case PVR2_PATHWAY_DIGITAL: return "digital";
4709         default: return "unknown";
4710         }
4711 }
4712
4713
4714 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4715                                              char *buf,unsigned int acnt)
4716 {
4717         switch (which) {
4718         case 0:
4719                 return scnprintf(
4720                         buf,acnt,
4721                         "driver:%s%s%s%s%s <mode=%s>",
4722                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4723                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4724                         (hdw->flag_disconnected ? " <disconnected>" :
4725                          " <connected>"),
4726                         (hdw->flag_tripped ? " <tripped>" : ""),
4727                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4728                         pvr2_pathway_state_name(hdw->pathway_state));
4729
4730         case 1:
4731                 return scnprintf(
4732                         buf,acnt,
4733                         "pipeline:%s%s%s%s",
4734                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4735                         (hdw->state_pipeline_config ?
4736                          " <configok>" : " <stale>"),
4737                         (hdw->state_pipeline_req ? " <req>" : ""),
4738                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4739         case 2:
4740                 return scnprintf(
4741                         buf,acnt,
4742                         "worker:%s%s%s%s%s%s%s",
4743                         (hdw->state_decoder_run ?
4744                          (hdw->state_decoder_ready ?
4745                           "<decode:run>" : " <decode:start>") :
4746                          (hdw->state_decoder_quiescent ?
4747                           "" : " <decode:stop>")),
4748                         (hdw->state_decoder_quiescent ?
4749                          " <decode:quiescent>" : ""),
4750                         (hdw->state_encoder_ok ?
4751                          "" : " <encode:init>"),
4752                         (hdw->state_encoder_run ?
4753                          (hdw->state_encoder_runok ?
4754                           " <encode:run>" :
4755                           " <encode:firstrun>") :
4756                          (hdw->state_encoder_runok ?
4757                           " <encode:stop>" :
4758                           " <encode:virgin>")),
4759                         (hdw->state_encoder_config ?
4760                          " <encode:configok>" :
4761                          (hdw->state_encoder_waitok ?
4762                           "" : " <encode:waitok>")),
4763                         (hdw->state_usbstream_run ?
4764                          " <usb:run>" : " <usb:stop>"),
4765                         (hdw->state_pathway_ok ?
4766                          " <pathway:ok>" : ""));
4767         case 3:
4768                 return scnprintf(
4769                         buf,acnt,
4770                         "state: %s",
4771                         pvr2_get_state_name(hdw->master_state));
4772         case 4: {
4773                 unsigned int tcnt = 0;
4774                 unsigned int ccnt;
4775
4776                 ccnt = scnprintf(buf,
4777                                  acnt,
4778                                  "Hardware supported inputs: ");
4779                 tcnt += ccnt;
4780                 tcnt += print_input_mask(hdw->input_avail_mask,
4781                                          buf+tcnt,
4782                                          acnt-tcnt);
4783                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4784                         ccnt = scnprintf(buf+tcnt,
4785                                          acnt-tcnt,
4786                                          "; allowed inputs: ");
4787                         tcnt += ccnt;
4788                         tcnt += print_input_mask(hdw->input_allowed_mask,
4789                                                  buf+tcnt,
4790                                                  acnt-tcnt);
4791                 }
4792                 return tcnt;
4793         }
4794         case 5: {
4795                 struct pvr2_stream_stats stats;
4796                 if (!hdw->vid_stream) break;
4797                 pvr2_stream_get_stats(hdw->vid_stream,
4798                                       &stats,
4799                                       0);
4800                 return scnprintf(
4801                         buf,acnt,
4802                         "Bytes streamed=%u"
4803                         " URBs: queued=%u idle=%u ready=%u"
4804                         " processed=%u failed=%u",
4805                         stats.bytes_processed,
4806                         stats.buffers_in_queue,
4807                         stats.buffers_in_idle,
4808                         stats.buffers_in_ready,
4809                         stats.buffers_processed,
4810                         stats.buffers_failed);
4811         }
4812         case 6: {
4813                 unsigned int id = hdw->ir_scheme_active;
4814                 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4815                                  (id >= ARRAY_SIZE(ir_scheme_names) ?
4816                                   "?" : ir_scheme_names[id]));
4817         }
4818         default: break;
4819         }
4820         return 0;
4821 }
4822
4823
4824 /* Generate report containing info about attached sub-devices and attached
4825    i2c clients, including an indication of which attached i2c clients are
4826    actually sub-devices. */
4827 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4828                                             char *buf, unsigned int acnt)
4829 {
4830         struct v4l2_subdev *sd;
4831         unsigned int tcnt = 0;
4832         unsigned int ccnt;
4833         struct i2c_client *client;
4834         const char *p;
4835         unsigned int id;
4836
4837         ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
4838         tcnt += ccnt;
4839         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4840                 id = sd->grp_id;
4841                 p = NULL;
4842                 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4843                 if (p) {
4844                         ccnt = scnprintf(buf + tcnt, acnt - tcnt, "  %s:", p);
4845                         tcnt += ccnt;
4846                 } else {
4847                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4848                                          "  (unknown id=%u):", id);
4849                         tcnt += ccnt;
4850                 }
4851                 client = v4l2_get_subdevdata(sd);
4852                 if (client) {
4853                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4854                                          " %s @ %02x\n", client->name,
4855                                          client->addr);
4856                         tcnt += ccnt;
4857                 } else {
4858                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4859                                          " no i2c client\n");
4860                         tcnt += ccnt;
4861                 }
4862         }
4863         return tcnt;
4864 }
4865
4866
4867 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4868                                    char *buf,unsigned int acnt)
4869 {
4870         unsigned int bcnt,ccnt,idx;
4871         bcnt = 0;
4872         LOCK_TAKE(hdw->big_lock);
4873         for (idx = 0; ; idx++) {
4874                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4875                 if (!ccnt) break;
4876                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4877                 if (!acnt) break;
4878                 buf[0] = '\n'; ccnt = 1;
4879                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4880         }
4881         ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4882         bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4883         LOCK_GIVE(hdw->big_lock);
4884         return bcnt;
4885 }
4886
4887
4888 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4889 {
4890         char buf[256];
4891         unsigned int idx, ccnt;
4892         unsigned int lcnt, ucnt;
4893
4894         for (idx = 0; ; idx++) {
4895                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4896                 if (!ccnt) break;
4897                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4898         }
4899         ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4900         if (ccnt >= sizeof(buf))
4901                 ccnt = sizeof(buf);
4902
4903         ucnt = 0;
4904         while (ucnt < ccnt) {
4905                 lcnt = 0;
4906                 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4907                         lcnt++;
4908                 }
4909                 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4910                 ucnt += lcnt + 1;
4911         }
4912 }
4913
4914
4915 /* Evaluate and update the driver's current state, taking various actions
4916    as appropriate for the update. */
4917 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4918 {
4919         unsigned int st;
4920         int state_updated = 0;
4921         int callback_flag = 0;
4922         int analog_mode;
4923
4924         pvr2_trace(PVR2_TRACE_STBITS,
4925                    "Drive state check START");
4926         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4927                 pvr2_hdw_state_log_state(hdw);
4928         }
4929
4930         /* Process all state and get back over disposition */
4931         state_updated = pvr2_hdw_state_update(hdw);
4932
4933         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4934
4935         /* Update master state based upon all other states. */
4936         if (!hdw->flag_ok) {
4937                 st = PVR2_STATE_DEAD;
4938         } else if (hdw->fw1_state != FW1_STATE_OK) {
4939                 st = PVR2_STATE_COLD;
4940         } else if ((analog_mode ||
4941                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4942                    !hdw->state_encoder_ok) {
4943                 st = PVR2_STATE_WARM;
4944         } else if (hdw->flag_tripped ||
4945                    (analog_mode && hdw->flag_decoder_missed)) {
4946                 st = PVR2_STATE_ERROR;
4947         } else if (hdw->state_usbstream_run &&
4948                    (!analog_mode ||
4949                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4950                 st = PVR2_STATE_RUN;
4951         } else {
4952                 st = PVR2_STATE_READY;
4953         }
4954         if (hdw->master_state != st) {
4955                 pvr2_trace(PVR2_TRACE_STATE,
4956                            "Device state change from %s to %s",
4957                            pvr2_get_state_name(hdw->master_state),
4958                            pvr2_get_state_name(st));
4959                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4960                 hdw->master_state = st;
4961                 state_updated = !0;
4962                 callback_flag = !0;
4963         }
4964         if (state_updated) {
4965                 /* Trigger anyone waiting on any state changes here. */
4966                 wake_up(&hdw->state_wait_data);
4967         }
4968
4969         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4970                 pvr2_hdw_state_log_state(hdw);
4971         }
4972         pvr2_trace(PVR2_TRACE_STBITS,
4973                    "Drive state check DONE callback=%d",callback_flag);
4974
4975         return callback_flag;
4976 }
4977
4978
4979 /* Cause kernel thread to check / update driver state */
4980 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4981 {
4982         if (hdw->state_stale) return;
4983         hdw->state_stale = !0;
4984         trace_stbit("state_stale",hdw->state_stale);
4985         schedule_work(&hdw->workpoll);
4986 }
4987
4988
4989 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4990 {
4991         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4992 }
4993
4994
4995 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4996 {
4997         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4998 }
4999
5000
5001 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5002 {
5003         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5004 }
5005
5006
5007 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5008 {
5009         u32 cval,nval;
5010         int ret;
5011         if (~msk) {
5012                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5013                 if (ret) return ret;
5014                 nval = (cval & ~msk) | (val & msk);
5015                 pvr2_trace(PVR2_TRACE_GPIO,
5016                            "GPIO direction changing 0x%x:0x%x"
5017                            " from 0x%x to 0x%x",
5018                            msk,val,cval,nval);
5019         } else {
5020                 nval = val;
5021                 pvr2_trace(PVR2_TRACE_GPIO,
5022                            "GPIO direction changing to 0x%x",nval);
5023         }
5024         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5025 }
5026
5027
5028 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5029 {
5030         u32 cval,nval;
5031         int ret;
5032         if (~msk) {
5033                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5034                 if (ret) return ret;
5035                 nval = (cval & ~msk) | (val & msk);
5036                 pvr2_trace(PVR2_TRACE_GPIO,
5037                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5038                            msk,val,cval,nval);
5039         } else {
5040                 nval = val;
5041                 pvr2_trace(PVR2_TRACE_GPIO,
5042                            "GPIO output changing to 0x%x",nval);
5043         }
5044         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5045 }
5046
5047
5048 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5049 {
5050         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5051         memset(vtp, 0, sizeof(*vtp));
5052         vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
5053                 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
5054         hdw->tuner_signal_stale = 0;
5055         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5056            using v4l2-subdev - therefore we can't support that AT ALL right
5057            now.  (Of course, no sub-drivers seem to implement it either.
5058            But now it's a a chicken and egg problem...) */
5059         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
5060         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5061                    " type=%u strength=%u audio=0x%x cap=0x%x"
5062                    " low=%u hi=%u",
5063                    vtp->type,
5064                    vtp->signal, vtp->rxsubchans, vtp->capability,
5065                    vtp->rangelow, vtp->rangehigh);
5066
5067         /* We have to do this to avoid getting into constant polling if
5068            there's nobody to answer a poll of cropcap info. */
5069         hdw->cropcap_stale = 0;
5070 }
5071
5072
5073 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5074 {
5075         return hdw->input_avail_mask;
5076 }
5077
5078
5079 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5080 {
5081         return hdw->input_allowed_mask;
5082 }
5083
5084
5085 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5086 {
5087         if (hdw->input_val != v) {
5088                 hdw->input_val = v;
5089                 hdw->input_dirty = !0;
5090         }
5091
5092         /* Handle side effects - if we switch to a mode that needs the RF
5093            tuner, then select the right frequency choice as well and mark
5094            it dirty. */
5095         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5096                 hdw->freqSelector = 0;
5097                 hdw->freqDirty = !0;
5098         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5099                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5100                 hdw->freqSelector = 1;
5101                 hdw->freqDirty = !0;
5102         }
5103         return 0;
5104 }
5105
5106
5107 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5108                                unsigned int change_mask,
5109                                unsigned int change_val)
5110 {
5111         int ret = 0;
5112         unsigned int nv,m,idx;
5113         LOCK_TAKE(hdw->big_lock);
5114         do {
5115                 nv = hdw->input_allowed_mask & ~change_mask;
5116                 nv |= (change_val & change_mask);
5117                 nv &= hdw->input_avail_mask;
5118                 if (!nv) {
5119                         /* No legal modes left; return error instead. */
5120                         ret = -EPERM;
5121                         break;
5122                 }
5123                 hdw->input_allowed_mask = nv;
5124                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5125                         /* Current mode is still in the allowed mask, so
5126                            we're done. */
5127                         break;
5128                 }
5129                 /* Select and switch to a mode that is still in the allowed
5130                    mask */
5131                 if (!hdw->input_allowed_mask) {
5132                         /* Nothing legal; give up */
5133                         break;
5134                 }
5135                 m = hdw->input_allowed_mask;
5136                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5137                         if (!((1 << idx) & m)) continue;
5138                         pvr2_hdw_set_input(hdw,idx);
5139                         break;
5140                 }
5141         } while (0);
5142         LOCK_GIVE(hdw->big_lock);
5143         return ret;
5144 }
5145
5146
5147 /* Find I2C address of eeprom */
5148 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5149 {
5150         int result;
5151         LOCK_TAKE(hdw->ctl_lock); do {
5152                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5153                 result = pvr2_send_request(hdw,
5154                                            hdw->cmd_buffer,1,
5155                                            hdw->cmd_buffer,1);
5156                 if (result < 0) break;
5157                 result = hdw->cmd_buffer[0];
5158         } while(0); LOCK_GIVE(hdw->ctl_lock);
5159         return result;
5160 }