drivers/media/usb/pvrusb2/pvrusb2-hdw.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  */
   6
   7 #include <linux/errno.h>
   8 #include <linux/string.h>
   9 #include <linux/slab.h>
  10 #include <linux/module.h>
  11 #include <linux/firmware.h>
  12 #include <linux/videodev2.h>
  13 #include <media/v4l2-common.h>
  14 #include <media/tuner.h>
  15 #include "pvrusb2.h"
  16 #include "pvrusb2-std.h"
  17 #include "pvrusb2-util.h"
  18 #include "pvrusb2-hdw.h"
  19 #include "pvrusb2-i2c-core.h"
  20 #include "pvrusb2-eeprom.h"
  21 #include "pvrusb2-hdw-internal.h"
  22 #include "pvrusb2-encoder.h"
  23 #include "pvrusb2-debug.h"
  24 #include "pvrusb2-fx2-cmd.h"
  25 #include "pvrusb2-wm8775.h"
  26 #include "pvrusb2-video-v4l.h"
  27 #include "pvrusb2-cx2584x-v4l.h"
  28 #include "pvrusb2-cs53l32a.h"
  29 #include "pvrusb2-audio.h"
  30
  31 #define TV_MIN_FREQ     55250000L
  32 #define TV_MAX_FREQ    850000000L
  33
  34 /* This defines a minimum interval that the decoder must remain quiet
  35    before we are allowed to start it running. */
  36 #define TIME_MSEC_DECODER_WAIT 50
  37
  38 /* This defines a minimum interval that the decoder must be allowed to run
  39    before we can safely begin using its streaming output. */
  40 #define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
  41
  42 /* This defines a minimum interval that the encoder must remain quiet
  43    before we are allowed to configure it. */
  44 #define TIME_MSEC_ENCODER_WAIT 50
  45
  46 /* This defines the minimum interval that the encoder must successfully run
  47    before we consider that the encoder has run at least once since its
  48    firmware has been loaded.  This measurement is in important for cases
  49    where we can't do something until we know that the encoder has been run
  50    at least once. */
  51 #define TIME_MSEC_ENCODER_OK 250
  52
  53 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  54 static DEFINE_MUTEX(pvr2_unit_mtx);
  55
  56 static int ctlchg;
  57 static int procreload;
  58 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  59 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  60 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  61 static int init_pause_msec;
  62
  63 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  64 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  65 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  66 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  67 module_param(procreload, int, S_IRUGO|S_IWUSR);
  68 MODULE_PARM_DESC(procreload,
  69                  "Attempt init failure recovery with firmware reload");
  70 module_param_array(tuner,    int, NULL, 0444);
  71 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  72 module_param_array(video_std,    int, NULL, 0444);
  73 MODULE_PARM_DESC(video_std,"specify initial video standard");
  74 module_param_array(tolerance,    int, NULL, 0444);
  75 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  76
  77 /* US Broadcast channel 3 (61.25 MHz), to help with testing */
  78 static int default_tv_freq    = 61250000L;
  79 /* 104.3 MHz, a usable FM station for my area */
  80 static int default_radio_freq = 104300000L;
  81
  82 module_param_named(tv_freq, default_tv_freq, int, 0444);
  83 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  84 module_param_named(radio_freq, default_radio_freq, int, 0444);
  85 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  86
  87 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  88 #define PVR2_CTL_READ_ENDPOINT   0x81
  89
  90 #define PVR2_GPIO_IN 0x9008
  91 #define PVR2_GPIO_OUT 0x900c
  92 #define PVR2_GPIO_DIR 0x9020
  93
  94 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
  95
  96 #define PVR2_FIRMWARE_ENDPOINT   0x02
  97
  98 /* size of a firmware chunk */
  99 #define FIRMWARE_CHUNK_SIZE 0x2000
 100
 101 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 102                                         struct v4l2_subdev *);
 103
 104 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 105         [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 106         [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 107         [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 108         [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 109         [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
 110 };
 111
 112 static const char *module_names[] = {
 113         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 114         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 115         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 116         [PVR2_CLIENT_ID_TUNER] = "tuner",
 117         [PVR2_CLIENT_ID_DEMOD] = "tuner",
 118         [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
 119         [PVR2_CLIENT_ID_WM8775] = "wm8775",
 120 };
 121
 122
 123 static const unsigned char *module_i2c_addresses[] = {
 124         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 125         [PVR2_CLIENT_ID_DEMOD] = "\x43",
 126         [PVR2_CLIENT_ID_MSP3400] = "\x40",
 127         [PVR2_CLIENT_ID_SAA7115] = "\x21",
 128         [PVR2_CLIENT_ID_WM8775] = "\x1b",
 129         [PVR2_CLIENT_ID_CX25840] = "\x44",
 130         [PVR2_CLIENT_ID_CS53L32A] = "\x11",
 131 };
 132
 133
 134 static const char *ir_scheme_names[] = {
 135         [PVR2_IR_SCHEME_NONE] = "none",
 136         [PVR2_IR_SCHEME_29XXX] = "29xxx",
 137         [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
 138         [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
 139         [PVR2_IR_SCHEME_ZILOG] = "Zilog",
 140 };
 141
 142
 143 /* Define the list of additional controls we'll dynamically construct based
 144    on query of the cx2341x module. */
 145 struct pvr2_mpeg_ids {
 146         const char *strid;
 147         int id;
 148 };
 149 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 150         {
 151                 .strid = "audio_layer",
 152                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 153         },{
 154                 .strid = "audio_bitrate",
 155                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 156         },{
 157                 /* Already using audio_mode elsewhere :-( */
 158                 .strid = "mpeg_audio_mode",
 159                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 160         },{
 161                 .strid = "mpeg_audio_mode_extension",
 162                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 163         },{
 164                 .strid = "audio_emphasis",
 165                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 166         },{
 167                 .strid = "audio_crc",
 168                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 169         },{
 170                 .strid = "video_aspect",
 171                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 172         },{
 173                 .strid = "video_b_frames",
 174                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 175         },{
 176                 .strid = "video_gop_size",
 177                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 178         },{
 179                 .strid = "video_gop_closure",
 180                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 181         },{
 182                 .strid = "video_bitrate_mode",
 183                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 184         },{
 185                 .strid = "video_bitrate",
 186                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 187         },{
 188                 .strid = "video_bitrate_peak",
 189                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 190         },{
 191                 .strid = "video_temporal_decimation",
 192                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 193         },{
 194                 .strid = "stream_type",
 195                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 196         },{
 197                 .strid = "video_spatial_filter_mode",
 198                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 199         },{
 200                 .strid = "video_spatial_filter",
 201                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 202         },{
 203                 .strid = "video_luma_spatial_filter_type",
 204                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 205         },{
 206                 .strid = "video_chroma_spatial_filter_type",
 207                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 208         },{
 209                 .strid = "video_temporal_filter_mode",
 210                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 211         },{
 212                 .strid = "video_temporal_filter",
 213                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 214         },{
 215                 .strid = "video_median_filter_type",
 216                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 217         },{
 218                 .strid = "video_luma_median_filter_top",
 219                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 220         },{
 221                 .strid = "video_luma_median_filter_bottom",
 222                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 223         },{
 224                 .strid = "video_chroma_median_filter_top",
 225                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 226         },{
 227                 .strid = "video_chroma_median_filter_bottom",
 228                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 229         }
 230 };
 231 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 232
 233
 234 static const char *control_values_srate[] = {
 235         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 236         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 237         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 238 };
 239
 240
 241
 242 static const char *control_values_input[] = {
 243         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 244         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 245         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 246         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 247         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 248 };
 249
 250
 251 static const char *control_values_audiomode[] = {
 252         [V4L2_TUNER_MODE_MONO]   = "Mono",
 253         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 254         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 255         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 256         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 257 };
 258
 259
 260 static const char *control_values_hsm[] = {
 261         [PVR2_CVAL_HSM_FAIL] = "Fail",
 262         [PVR2_CVAL_HSM_HIGH] = "High",
 263         [PVR2_CVAL_HSM_FULL] = "Full",
 264 };
 265
 266
 267 static const char *pvr2_state_names[] = {
 268         [PVR2_STATE_NONE] =    "none",
 269         [PVR2_STATE_DEAD] =    "dead",
 270         [PVR2_STATE_COLD] =    "cold",
 271         [PVR2_STATE_WARM] =    "warm",
 272         [PVR2_STATE_ERROR] =   "error",
 273         [PVR2_STATE_READY] =   "ready",
 274         [PVR2_STATE_RUN] =     "run",
 275 };
 276
 277
 278 struct pvr2_fx2cmd_descdef {
 279         unsigned char id;
 280         unsigned char *desc;
 281 };
 282
 283 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 284         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 285         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 286         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 287         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 288         {FX2CMD_REG_WRITE, "write encoder register"},
 289         {FX2CMD_REG_READ, "read encoder register"},
 290         {FX2CMD_MEMSEL, "encoder memsel"},
 291         {FX2CMD_I2C_WRITE, "i2c write"},
 292         {FX2CMD_I2C_READ, "i2c read"},
 293         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 294         {FX2CMD_STREAMING_ON, "stream on"},
 295         {FX2CMD_STREAMING_OFF, "stream off"},
 296         {FX2CMD_FWPOST1, "fwpost1"},
 297         {FX2CMD_POWER_OFF, "power off"},
 298         {FX2CMD_POWER_ON, "power on"},
 299         {FX2CMD_DEEP_RESET, "deep reset"},
 300         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 301         {FX2CMD_GET_IR_CODE, "get IR code"},
 302         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 303         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 304         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 305         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 306         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 307         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 308         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 309         {FX2CMD_HCW_DEMOD_RESET_PIN, "hcw demod reset pin"},
 310         {FX2CMD_HCW_MAKO_SLEEP_PIN, "hcw mako sleep pin"},
 311 };
 312
 313
 314 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 315 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 316 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 317 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 318 static void pvr2_hdw_worker_poll(struct work_struct *work);
 319 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 320 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 321 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 322 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 323 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 324 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 325 static void pvr2_hdw_quiescent_timeout(struct timer_list *);
 326 static void pvr2_hdw_decoder_stabilization_timeout(struct timer_list *);
 327 static void pvr2_hdw_encoder_wait_timeout(struct timer_list *);
 328 static void pvr2_hdw_encoder_run_timeout(struct timer_list *);
 329 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 330 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 331                                 unsigned int timeout,int probe_fl,
 332                                 void *write_data,unsigned int write_len,
 333                                 void *read_data,unsigned int read_len);
 334 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 335 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw);
 336
 337 static void trace_stbit(const char *name,int val)
 338 {
 339         pvr2_trace(PVR2_TRACE_STBITS,
 340                    "State bit %s <-- %s",
 341                    name,(val ? "true" : "false"));
 342 }
 343
 344 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 345 {
 346         struct pvr2_hdw *hdw = cptr->hdw;
 347         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 348                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 349         } else {
 350                 *vp = 0;
 351         }
 352         return 0;
 353 }
 354
 355 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 356 {
 357         struct pvr2_hdw *hdw = cptr->hdw;
 358         unsigned int slotId = hdw->freqProgSlot;
 359         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 360                 hdw->freqTable[slotId-1] = v;
 361                 /* Handle side effects correctly - if we're tuned to this
 362                    slot, then forgot the slot id relation since the stored
 363                    frequency has been changed. */
 364                 if (hdw->freqSelector) {
 365                         if (hdw->freqSlotRadio == slotId) {
 366                                 hdw->freqSlotRadio = 0;
 367                         }
 368                 } else {
 369                         if (hdw->freqSlotTelevision == slotId) {
 370                                 hdw->freqSlotTelevision = 0;
 371                         }
 372                 }
 373         }
 374         return 0;
 375 }
 376
 377 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 378 {
 379         *vp = cptr->hdw->freqProgSlot;
 380         return 0;
 381 }
 382
 383 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 384 {
 385         struct pvr2_hdw *hdw = cptr->hdw;
 386         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 387                 hdw->freqProgSlot = v;
 388         }
 389         return 0;
 390 }
 391
 392 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 393 {
 394         struct pvr2_hdw *hdw = cptr->hdw;
 395         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 396         return 0;
 397 }
 398
 399 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 400 {
 401         unsigned freq = 0;
 402         struct pvr2_hdw *hdw = cptr->hdw;
 403         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 404         if (slotId > 0) {
 405                 freq = hdw->freqTable[slotId-1];
 406                 if (!freq) return 0;
 407                 pvr2_hdw_set_cur_freq(hdw,freq);
 408         }
 409         if (hdw->freqSelector) {
 410                 hdw->freqSlotRadio = slotId;
 411         } else {
 412                 hdw->freqSlotTelevision = slotId;
 413         }
 414         return 0;
 415 }
 416
 417 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 418 {
 419         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 420         return 0;
 421 }
 422
 423 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 424 {
 425         return cptr->hdw->freqDirty != 0;
 426 }
 427
 428 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 429 {
 430         cptr->hdw->freqDirty = 0;
 431 }
 432
 433 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 434 {
 435         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 436         return 0;
 437 }
 438
 439 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 440 {
 441         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 442         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 443         if (stat != 0) {
 444                 return stat;
 445         }
 446         *left = cap->bounds.left;
 447         return 0;
 448 }
 449
 450 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 451 {
 452         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 453         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 454         if (stat != 0) {
 455                 return stat;
 456         }
 457         *left = cap->bounds.left;
 458         if (cap->bounds.width > cptr->hdw->cropw_val) {
 459                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 460         }
 461         return 0;
 462 }
 463
 464 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 465 {
 466         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 467         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 468         if (stat != 0) {
 469                 return stat;
 470         }
 471         *top = cap->bounds.top;
 472         return 0;
 473 }
 474
 475 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 476 {
 477         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 478         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 479         if (stat != 0) {
 480                 return stat;
 481         }
 482         *top = cap->bounds.top;
 483         if (cap->bounds.height > cptr->hdw->croph_val) {
 484                 *top += cap->bounds.height - cptr->hdw->croph_val;
 485         }
 486         return 0;
 487 }
 488
 489 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
 490 {
 491         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 492         int stat, bleftend, cleft;
 493
 494         stat = pvr2_hdw_check_cropcap(cptr->hdw);
 495         if (stat != 0) {
 496                 return stat;
 497         }
 498         bleftend = cap->bounds.left+cap->bounds.width;
 499         cleft = cptr->hdw->cropl_val;
 500
 501         *width = cleft < bleftend ? bleftend-cleft : 0;
 502         return 0;
 503 }
 504
 505 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
 506 {
 507         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 508         int stat, btopend, ctop;
 509
 510         stat = pvr2_hdw_check_cropcap(cptr->hdw);
 511         if (stat != 0) {
 512                 return stat;
 513         }
 514         btopend = cap->bounds.top+cap->bounds.height;
 515         ctop = cptr->hdw->cropt_val;
 516
 517         *height = ctop < btopend ? btopend-ctop : 0;
 518         return 0;
 519 }
 520
 521 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 522 {
 523         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 524         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 525         if (stat != 0) {
 526                 return stat;
 527         }
 528         *val = cap->bounds.left;
 529         return 0;
 530 }
 531
 532 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 533 {
 534         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 535         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 536         if (stat != 0) {
 537                 return stat;
 538         }
 539         *val = cap->bounds.top;
 540         return 0;
 541 }
 542
 543 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 544 {
 545         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 546         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 547         if (stat != 0) {
 548                 return stat;
 549         }
 550         *val = cap->bounds.width;
 551         return 0;
 552 }
 553
 554 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 555 {
 556         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 557         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 558         if (stat != 0) {
 559                 return stat;
 560         }
 561         *val = cap->bounds.height;
 562         return 0;
 563 }
 564
 565 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 566 {
 567         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 568         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 569         if (stat != 0) {
 570                 return stat;
 571         }
 572         *val = cap->defrect.left;
 573         return 0;
 574 }
 575
 576 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 577 {
 578         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 579         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 580         if (stat != 0) {
 581                 return stat;
 582         }
 583         *val = cap->defrect.top;
 584         return 0;
 585 }
 586
 587 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 588 {
 589         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 590         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 591         if (stat != 0) {
 592                 return stat;
 593         }
 594         *val = cap->defrect.width;
 595         return 0;
 596 }
 597
 598 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 599 {
 600         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 601         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 602         if (stat != 0) {
 603                 return stat;
 604         }
 605         *val = cap->defrect.height;
 606         return 0;
 607 }
 608
 609 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 610 {
 611         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 612         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 613         if (stat != 0) {
 614                 return stat;
 615         }
 616         *val = cap->pixelaspect.numerator;
 617         return 0;
 618 }
 619
 620 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 621 {
 622         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 623         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 624         if (stat != 0) {
 625                 return stat;
 626         }
 627         *val = cap->pixelaspect.denominator;
 628         return 0;
 629 }
 630
 631 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 632 {
 633         /* Actual maximum depends on the video standard in effect. */
 634         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 635                 *vp = 480;
 636         } else {
 637                 *vp = 576;
 638         }
 639         return 0;
 640 }
 641
 642 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 643 {
 644         /* Actual minimum depends on device digitizer type. */
 645         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 646                 *vp = 75;
 647         } else {
 648                 *vp = 17;
 649         }
 650         return 0;
 651 }
 652
 653 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 654 {
 655         *vp = cptr->hdw->input_val;
 656         return 0;
 657 }
 658
 659 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 660 {
 661         if (v < 0 || v > PVR2_CVAL_INPUT_MAX)
 662                 return 0;
 663         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 664 }
 665
 666 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 667 {
 668         return pvr2_hdw_set_input(cptr->hdw,v);
 669 }
 670
 671 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 672 {
 673         return cptr->hdw->input_dirty != 0;
 674 }
 675
 676 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 677 {
 678         cptr->hdw->input_dirty = 0;
 679 }
 680
 681
 682 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 683 {
 684         unsigned long fv;
 685         struct pvr2_hdw *hdw = cptr->hdw;
 686         if (hdw->tuner_signal_stale) {
 687                 pvr2_hdw_status_poll(hdw);
 688         }
 689         fv = hdw->tuner_signal_info.rangehigh;
 690         if (!fv) {
 691                 /* Safety fallback */
 692                 *vp = TV_MAX_FREQ;
 693                 return 0;
 694         }
 695         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 696                 fv = (fv * 125) / 2;
 697         } else {
 698                 fv = fv * 62500;
 699         }
 700         *vp = fv;
 701         return 0;
 702 }
 703
 704 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 705 {
 706         unsigned long fv;
 707         struct pvr2_hdw *hdw = cptr->hdw;
 708         if (hdw->tuner_signal_stale) {
 709                 pvr2_hdw_status_poll(hdw);
 710         }
 711         fv = hdw->tuner_signal_info.rangelow;
 712         if (!fv) {
 713                 /* Safety fallback */
 714                 *vp = TV_MIN_FREQ;
 715                 return 0;
 716         }
 717         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 718                 fv = (fv * 125) / 2;
 719         } else {
 720                 fv = fv * 62500;
 721         }
 722         *vp = fv;
 723         return 0;
 724 }
 725
 726 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 727 {
 728         return cptr->hdw->enc_stale != 0;
 729 }
 730
 731 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 732 {
 733         cptr->hdw->enc_stale = 0;
 734         cptr->hdw->enc_unsafe_stale = 0;
 735 }
 736
 737 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 738 {
 739         int ret;
 740         struct v4l2_ext_controls cs;
 741         struct v4l2_ext_control c1;
 742         memset(&cs,0,sizeof(cs));
 743         memset(&c1,0,sizeof(c1));
 744         cs.controls = &c1;
 745         cs.count = 1;
 746         c1.id = cptr->info->v4l_id;
 747         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 748                                 VIDIOC_G_EXT_CTRLS);
 749         if (ret) return ret;
 750         *vp = c1.value;
 751         return 0;
 752 }
 753
 754 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 755 {
 756         int ret;
 757         struct pvr2_hdw *hdw = cptr->hdw;
 758         struct v4l2_ext_controls cs;
 759         struct v4l2_ext_control c1;
 760         memset(&cs,0,sizeof(cs));
 761         memset(&c1,0,sizeof(c1));
 762         cs.controls = &c1;
 763         cs.count = 1;
 764         c1.id = cptr->info->v4l_id;
 765         c1.value = v;
 766         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 767                                 hdw->state_encoder_run, &cs,
 768                                 VIDIOC_S_EXT_CTRLS);
 769         if (ret == -EBUSY) {
 770                 /* Oops.  cx2341x is telling us it's not safe to change
 771                    this control while we're capturing.  Make a note of this
 772                    fact so that the pipeline will be stopped the next time
 773                    controls are committed.  Then go on ahead and store this
 774                    change anyway. */
 775                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 776                                         0, &cs,
 777                                         VIDIOC_S_EXT_CTRLS);
 778                 if (!ret) hdw->enc_unsafe_stale = !0;
 779         }
 780         if (ret) return ret;
 781         hdw->enc_stale = !0;
 782         return 0;
 783 }
 784
 785 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 786 {
 787         struct v4l2_queryctrl qctrl;
 788         struct pvr2_ctl_info *info;
 789         qctrl.id = cptr->info->v4l_id;
 790         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 791         /* Strip out the const so we can adjust a function pointer.  It's
 792            OK to do this here because we know this is a dynamically created
 793            control, so the underlying storage for the info pointer is (a)
 794            private to us, and (b) not in read-only storage.  Either we do
 795            this or we significantly complicate the underlying control
 796            implementation. */
 797         info = (struct pvr2_ctl_info *)(cptr->info);
 798         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 799                 if (info->set_value) {
 800                         info->set_value = NULL;
 801                 }
 802         } else {
 803                 if (!(info->set_value)) {
 804                         info->set_value = ctrl_cx2341x_set;
 805                 }
 806         }
 807         return qctrl.flags;
 808 }
 809
 810 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 811 {
 812         *vp = cptr->hdw->state_pipeline_req;
 813         return 0;
 814 }
 815
 816 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 817 {
 818         *vp = cptr->hdw->master_state;
 819         return 0;
 820 }
 821
 822 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 823 {
 824         int result = pvr2_hdw_is_hsm(cptr->hdw);
 825         *vp = PVR2_CVAL_HSM_FULL;
 826         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 827         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 828         return 0;
 829 }
 830
 831 static int ctrl_stddetect_get(struct pvr2_ctrl *cptr, int *vp)
 832 {
 833         *vp = pvr2_hdw_get_detected_std(cptr->hdw);
 834         return 0;
 835 }
 836
 837 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 838 {
 839         *vp = cptr->hdw->std_mask_avail;
 840         return 0;
 841 }
 842
 843 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 844 {
 845         struct pvr2_hdw *hdw = cptr->hdw;
 846         v4l2_std_id ns;
 847         ns = hdw->std_mask_avail;
 848         ns = (ns & ~m) | (v & m);
 849         if (ns == hdw->std_mask_avail) return 0;
 850         hdw->std_mask_avail = ns;
 851         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
 852         return 0;
 853 }
 854
 855 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 856                                char *bufPtr,unsigned int bufSize,
 857                                unsigned int *len)
 858 {
 859         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 860         return 0;
 861 }
 862
 863 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 864                                const char *bufPtr,unsigned int bufSize,
 865                                int *mskp,int *valp)
 866 {
 867         int ret;
 868         v4l2_std_id id;
 869         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 870         if (ret < 0) return ret;
 871         if (mskp) *mskp = id;
 872         if (valp) *valp = id;
 873         return 0;
 874 }
 875
 876 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 877 {
 878         *vp = cptr->hdw->std_mask_cur;
 879         return 0;
 880 }
 881
 882 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 883 {
 884         struct pvr2_hdw *hdw = cptr->hdw;
 885         v4l2_std_id ns;
 886         ns = hdw->std_mask_cur;
 887         ns = (ns & ~m) | (v & m);
 888         if (ns == hdw->std_mask_cur) return 0;
 889         hdw->std_mask_cur = ns;
 890         hdw->std_dirty = !0;
 891         return 0;
 892 }
 893
 894 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 895 {
 896         return cptr->hdw->std_dirty != 0;
 897 }
 898
 899 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 900 {
 901         cptr->hdw->std_dirty = 0;
 902 }
 903
 904 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 905 {
 906         struct pvr2_hdw *hdw = cptr->hdw;
 907         pvr2_hdw_status_poll(hdw);
 908         *vp = hdw->tuner_signal_info.signal;
 909         return 0;
 910 }
 911
 912 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 913 {
 914         int val = 0;
 915         unsigned int subchan;
 916         struct pvr2_hdw *hdw = cptr->hdw;
 917         pvr2_hdw_status_poll(hdw);
 918         subchan = hdw->tuner_signal_info.rxsubchans;
 919         if (subchan & V4L2_TUNER_SUB_MONO) {
 920                 val |= (1 << V4L2_TUNER_MODE_MONO);
 921         }
 922         if (subchan & V4L2_TUNER_SUB_STEREO) {
 923                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 924         }
 925         if (subchan & V4L2_TUNER_SUB_LANG1) {
 926                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 927         }
 928         if (subchan & V4L2_TUNER_SUB_LANG2) {
 929                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 930         }
 931         *vp = val;
 932         return 0;
 933 }
 934
 935
 936 #define DEFINT(vmin,vmax) \
 937         .type = pvr2_ctl_int, \
 938         .def.type_int.min_value = vmin, \
 939         .def.type_int.max_value = vmax
 940
 941 #define DEFENUM(tab) \
 942         .type = pvr2_ctl_enum, \
 943         .def.type_enum.count = ARRAY_SIZE(tab), \
 944         .def.type_enum.value_names = tab
 945
 946 #define DEFBOOL \
 947         .type = pvr2_ctl_bool
 948
 949 #define DEFMASK(msk,tab) \
 950         .type = pvr2_ctl_bitmask, \
 951         .def.type_bitmask.valid_bits = msk, \
 952         .def.type_bitmask.bit_names = tab
 953
 954 #define DEFREF(vname) \
 955         .set_value = ctrl_set_##vname, \
 956         .get_value = ctrl_get_##vname, \
 957         .is_dirty = ctrl_isdirty_##vname, \
 958         .clear_dirty = ctrl_cleardirty_##vname
 959
 960
 961 #define VCREATE_FUNCS(vname) \
 962 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 963 {*vp = cptr->hdw->vname##_val; return 0;} \
 964 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 965 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 966 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 967 {return cptr->hdw->vname##_dirty != 0;} \
 968 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 969 {cptr->hdw->vname##_dirty = 0;}
 970
 971 VCREATE_FUNCS(brightness)
 972 VCREATE_FUNCS(contrast)
 973 VCREATE_FUNCS(saturation)
 974 VCREATE_FUNCS(hue)
 975 VCREATE_FUNCS(volume)
 976 VCREATE_FUNCS(balance)
 977 VCREATE_FUNCS(bass)
 978 VCREATE_FUNCS(treble)
 979 VCREATE_FUNCS(mute)
 980 VCREATE_FUNCS(cropl)
 981 VCREATE_FUNCS(cropt)
 982 VCREATE_FUNCS(cropw)
 983 VCREATE_FUNCS(croph)
 984 VCREATE_FUNCS(audiomode)
 985 VCREATE_FUNCS(res_hor)
 986 VCREATE_FUNCS(res_ver)
 987 VCREATE_FUNCS(srate)
 988
 989 /* Table definition of all controls which can be manipulated */
 990 static const struct pvr2_ctl_info control_defs[] = {
 991         {
 992                 .v4l_id = V4L2_CID_BRIGHTNESS,
 993                 .desc = "Brightness",
 994                 .name = "brightness",
 995                 .default_value = 128,
 996                 DEFREF(brightness),
 997                 DEFINT(0,255),
 998         },{
 999                 .v4l_id = V4L2_CID_CONTRAST,
1000                 .desc = "Contrast",
1001                 .name = "contrast",
1002                 .default_value = 68,
1003                 DEFREF(contrast),
1004                 DEFINT(0,127),
1005         },{
1006                 .v4l_id = V4L2_CID_SATURATION,
1007                 .desc = "Saturation",
1008                 .name = "saturation",
1009                 .default_value = 64,
1010                 DEFREF(saturation),
1011                 DEFINT(0,127),
1012         },{
1013                 .v4l_id = V4L2_CID_HUE,
1014                 .desc = "Hue",
1015                 .name = "hue",
1016                 .default_value = 0,
1017                 DEFREF(hue),
1018                 DEFINT(-128,127),
1019         },{
1020                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1021                 .desc = "Volume",
1022                 .name = "volume",
1023                 .default_value = 62000,
1024                 DEFREF(volume),
1025                 DEFINT(0,65535),
1026         },{
1027                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1028                 .desc = "Balance",
1029                 .name = "balance",
1030                 .default_value = 0,
1031                 DEFREF(balance),
1032                 DEFINT(-32768,32767),
1033         },{
1034                 .v4l_id = V4L2_CID_AUDIO_BASS,
1035                 .desc = "Bass",
1036                 .name = "bass",
1037                 .default_value = 0,
1038                 DEFREF(bass),
1039                 DEFINT(-32768,32767),
1040         },{
1041                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1042                 .desc = "Treble",
1043                 .name = "treble",
1044                 .default_value = 0,
1045                 DEFREF(treble),
1046                 DEFINT(-32768,32767),
1047         },{
1048                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1049                 .desc = "Mute",
1050                 .name = "mute",
1051                 .default_value = 0,
1052                 DEFREF(mute),
1053                 DEFBOOL,
1054         }, {
1055                 .desc = "Capture crop left margin",
1056                 .name = "crop_left",
1057                 .internal_id = PVR2_CID_CROPL,
1058                 .default_value = 0,
1059                 DEFREF(cropl),
1060                 DEFINT(-129, 340),
1061                 .get_min_value = ctrl_cropl_min_get,
1062                 .get_max_value = ctrl_cropl_max_get,
1063                 .get_def_value = ctrl_get_cropcapdl,
1064         }, {
1065                 .desc = "Capture crop top margin",
1066                 .name = "crop_top",
1067                 .internal_id = PVR2_CID_CROPT,
1068                 .default_value = 0,
1069                 DEFREF(cropt),
1070                 DEFINT(-35, 544),
1071                 .get_min_value = ctrl_cropt_min_get,
1072                 .get_max_value = ctrl_cropt_max_get,
1073                 .get_def_value = ctrl_get_cropcapdt,
1074         }, {
1075                 .desc = "Capture crop width",
1076                 .name = "crop_width",
1077                 .internal_id = PVR2_CID_CROPW,
1078                 .default_value = 720,
1079                 DEFREF(cropw),
1080                 DEFINT(0, 864),
1081                 .get_max_value = ctrl_cropw_max_get,
1082                 .get_def_value = ctrl_get_cropcapdw,
1083         }, {
1084                 .desc = "Capture crop height",
1085                 .name = "crop_height",
1086                 .internal_id = PVR2_CID_CROPH,
1087                 .default_value = 480,
1088                 DEFREF(croph),
1089                 DEFINT(0, 576),
1090                 .get_max_value = ctrl_croph_max_get,
1091                 .get_def_value = ctrl_get_cropcapdh,
1092         }, {
1093                 .desc = "Capture capability pixel aspect numerator",
1094                 .name = "cropcap_pixel_numerator",
1095                 .internal_id = PVR2_CID_CROPCAPPAN,
1096                 .get_value = ctrl_get_cropcappan,
1097         }, {
1098                 .desc = "Capture capability pixel aspect denominator",
1099                 .name = "cropcap_pixel_denominator",
1100                 .internal_id = PVR2_CID_CROPCAPPAD,
1101                 .get_value = ctrl_get_cropcappad,
1102         }, {
1103                 .desc = "Capture capability bounds top",
1104                 .name = "cropcap_bounds_top",
1105                 .internal_id = PVR2_CID_CROPCAPBT,
1106                 .get_value = ctrl_get_cropcapbt,
1107         }, {
1108                 .desc = "Capture capability bounds left",
1109                 .name = "cropcap_bounds_left",
1110                 .internal_id = PVR2_CID_CROPCAPBL,
1111                 .get_value = ctrl_get_cropcapbl,
1112         }, {
1113                 .desc = "Capture capability bounds width",
1114                 .name = "cropcap_bounds_width",
1115                 .internal_id = PVR2_CID_CROPCAPBW,
1116                 .get_value = ctrl_get_cropcapbw,
1117         }, {
1118                 .desc = "Capture capability bounds height",
1119                 .name = "cropcap_bounds_height",
1120                 .internal_id = PVR2_CID_CROPCAPBH,
1121                 .get_value = ctrl_get_cropcapbh,
1122         },{
1123                 .desc = "Video Source",
1124                 .name = "input",
1125                 .internal_id = PVR2_CID_INPUT,
1126                 .default_value = PVR2_CVAL_INPUT_TV,
1127                 .check_value = ctrl_check_input,
1128                 DEFREF(input),
1129                 DEFENUM(control_values_input),
1130         },{
1131                 .desc = "Audio Mode",
1132                 .name = "audio_mode",
1133                 .internal_id = PVR2_CID_AUDIOMODE,
1134                 .default_value = V4L2_TUNER_MODE_STEREO,
1135                 DEFREF(audiomode),
1136                 DEFENUM(control_values_audiomode),
1137         },{
1138                 .desc = "Horizontal capture resolution",
1139                 .name = "resolution_hor",
1140                 .internal_id = PVR2_CID_HRES,
1141                 .default_value = 720,
1142                 DEFREF(res_hor),
1143                 DEFINT(19,720),
1144         },{
1145                 .desc = "Vertical capture resolution",
1146                 .name = "resolution_ver",
1147                 .internal_id = PVR2_CID_VRES,
1148                 .default_value = 480,
1149                 DEFREF(res_ver),
1150                 DEFINT(17,576),
1151                 /* Hook in check for video standard and adjust maximum
1152                    depending on the standard. */
1153                 .get_max_value = ctrl_vres_max_get,
1154                 .get_min_value = ctrl_vres_min_get,
1155         },{
1156                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1157                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1158                 .desc = "Audio Sampling Frequency",
1159                 .name = "srate",
1160                 DEFREF(srate),
1161                 DEFENUM(control_values_srate),
1162         },{
1163                 .desc = "Tuner Frequency (Hz)",
1164                 .name = "frequency",
1165                 .internal_id = PVR2_CID_FREQUENCY,
1166                 .default_value = 0,
1167                 .set_value = ctrl_freq_set,
1168                 .get_value = ctrl_freq_get,
1169                 .is_dirty = ctrl_freq_is_dirty,
1170                 .clear_dirty = ctrl_freq_clear_dirty,
1171                 DEFINT(0,0),
1172                 /* Hook in check for input value (tv/radio) and adjust
1173                    max/min values accordingly */
1174                 .get_max_value = ctrl_freq_max_get,
1175                 .get_min_value = ctrl_freq_min_get,
1176         },{
1177                 .desc = "Channel",
1178                 .name = "channel",
1179                 .set_value = ctrl_channel_set,
1180                 .get_value = ctrl_channel_get,
1181                 DEFINT(0,FREQTABLE_SIZE),
1182         },{
1183                 .desc = "Channel Program Frequency",
1184                 .name = "freq_table_value",
1185                 .set_value = ctrl_channelfreq_set,
1186                 .get_value = ctrl_channelfreq_get,
1187                 DEFINT(0,0),
1188                 /* Hook in check for input value (tv/radio) and adjust
1189                    max/min values accordingly */
1190                 .get_max_value = ctrl_freq_max_get,
1191                 .get_min_value = ctrl_freq_min_get,
1192         },{
1193                 .desc = "Channel Program ID",
1194                 .name = "freq_table_channel",
1195                 .set_value = ctrl_channelprog_set,
1196                 .get_value = ctrl_channelprog_get,
1197                 DEFINT(0,FREQTABLE_SIZE),
1198         },{
1199                 .desc = "Streaming Enabled",
1200                 .name = "streaming_enabled",
1201                 .get_value = ctrl_streamingenabled_get,
1202                 DEFBOOL,
1203         },{
1204                 .desc = "USB Speed",
1205                 .name = "usb_speed",
1206                 .get_value = ctrl_hsm_get,
1207                 DEFENUM(control_values_hsm),
1208         },{
1209                 .desc = "Master State",
1210                 .name = "master_state",
1211                 .get_value = ctrl_masterstate_get,
1212                 DEFENUM(pvr2_state_names),
1213         },{
1214                 .desc = "Signal Present",
1215                 .name = "signal_present",
1216                 .get_value = ctrl_signal_get,
1217                 DEFINT(0,65535),
1218         },{
1219                 .desc = "Audio Modes Present",
1220                 .name = "audio_modes_present",
1221                 .get_value = ctrl_audio_modes_present_get,
1222                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1223                    v4l.  Nothing outside of this module cares about this,
1224                    but I reuse it in order to also reuse the
1225                    control_values_audiomode string table. */
1226                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1227                          (1 << V4L2_TUNER_MODE_STEREO)|
1228                          (1 << V4L2_TUNER_MODE_LANG1)|
1229                          (1 << V4L2_TUNER_MODE_LANG2)),
1230                         control_values_audiomode),
1231         },{
1232                 .desc = "Video Standards Available Mask",
1233                 .name = "video_standard_mask_available",
1234                 .internal_id = PVR2_CID_STDAVAIL,
1235                 .skip_init = !0,
1236                 .get_value = ctrl_stdavail_get,
1237                 .set_value = ctrl_stdavail_set,
1238                 .val_to_sym = ctrl_std_val_to_sym,
1239                 .sym_to_val = ctrl_std_sym_to_val,
1240                 .type = pvr2_ctl_bitmask,
1241         },{
1242                 .desc = "Video Standards In Use Mask",
1243                 .name = "video_standard_mask_active",
1244                 .internal_id = PVR2_CID_STDCUR,
1245                 .skip_init = !0,
1246                 .get_value = ctrl_stdcur_get,
1247                 .set_value = ctrl_stdcur_set,
1248                 .is_dirty = ctrl_stdcur_is_dirty,
1249                 .clear_dirty = ctrl_stdcur_clear_dirty,
1250                 .val_to_sym = ctrl_std_val_to_sym,
1251                 .sym_to_val = ctrl_std_sym_to_val,
1252                 .type = pvr2_ctl_bitmask,
1253         },{
1254                 .desc = "Video Standards Detected Mask",
1255                 .name = "video_standard_mask_detected",
1256                 .internal_id = PVR2_CID_STDDETECT,
1257                 .skip_init = !0,
1258                 .get_value = ctrl_stddetect_get,
1259                 .val_to_sym = ctrl_std_val_to_sym,
1260                 .sym_to_val = ctrl_std_sym_to_val,
1261                 .type = pvr2_ctl_bitmask,
1262         }
1263 };
1264
1265 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1266
1267
1268 const char *pvr2_config_get_name(enum pvr2_config cfg)
1269 {
1270         switch (cfg) {
1271         case pvr2_config_empty: return "empty";
1272         case pvr2_config_mpeg: return "mpeg";
1273         case pvr2_config_vbi: return "vbi";
1274         case pvr2_config_pcm: return "pcm";
1275         case pvr2_config_rawvideo: return "raw video";
1276         }
1277         return "<unknown>";
1278 }
1279
1280
1281 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1282 {
1283         return hdw->usb_dev;
1284 }
1285
1286
1287 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1288 {
1289         return hdw->serial_number;
1290 }
1291
1292
1293 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1294 {
1295         return hdw->bus_info;
1296 }
1297
1298
1299 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1300 {
1301         return hdw->identifier;
1302 }
1303
1304
1305 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1306 {
1307         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1308 }
1309
1310 /* Set the currently tuned frequency and account for all possible
1311    driver-core side effects of this action. */
1312 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1313 {
1314         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1315                 if (hdw->freqSelector) {
1316                         /* Swing over to radio frequency selection */
1317                         hdw->freqSelector = 0;
1318                         hdw->freqDirty = !0;
1319                 }
1320                 if (hdw->freqValRadio != val) {
1321                         hdw->freqValRadio = val;
1322                         hdw->freqSlotRadio = 0;
1323                         hdw->freqDirty = !0;
1324                 }
1325         } else {
1326                 if (!(hdw->freqSelector)) {
1327                         /* Swing over to television frequency selection */
1328                         hdw->freqSelector = 1;
1329                         hdw->freqDirty = !0;
1330                 }
1331                 if (hdw->freqValTelevision != val) {
1332                         hdw->freqValTelevision = val;
1333                         hdw->freqSlotTelevision = 0;
1334                         hdw->freqDirty = !0;
1335                 }
1336         }
1337 }
1338
1339 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1340 {
1341         return hdw->unit_number;
1342 }
1343
1344
1345 /* Attempt to locate one of the given set of files.  Messages are logged
1346    appropriate to what has been found.  The return value will be 0 or
1347    greater on success (it will be the index of the file name found) and
1348    fw_entry will be filled in.  Otherwise a negative error is returned on
1349    failure.  If the return value is -ENOENT then no viable firmware file
1350    could be located. */
1351 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1352                                 const struct firmware **fw_entry,
1353                                 const char *fwtypename,
1354                                 unsigned int fwcount,
1355                                 const char *fwnames[])
1356 {
1357         unsigned int idx;
1358         int ret = -EINVAL;
1359         for (idx = 0; idx < fwcount; idx++) {
1360                 ret = reject_firmware(fw_entry,
1361                                        fwnames[idx],
1362                                        &hdw->usb_dev->dev);
1363                 if (!ret) {
1364                         trace_firmware("Located %s firmware: %s; uploading...",
1365                                        fwtypename,
1366                                        fwnames[idx]);
1367                         return idx;
1368                 }
1369                 if (ret == -ENOENT) continue;
1370                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1371                            "request_firmware fatal error with code=%d",ret);
1372                 return ret;
1373         }
1374         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1375                    "***WARNING*** Device %s firmware seems to be missing.",
1376                    fwtypename);
1377         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1378                    "Did you install the pvrusb2 firmware files in their proper location?");
1379         if (fwcount == 1) {
1380                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1381                            "request_firmware unable to locate %s file %s",
1382                            fwtypename,fwnames[0]);
1383         } else {
1384                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1385                            "request_firmware unable to locate one of the following %s files:",
1386                            fwtypename);
1387                 for (idx = 0; idx < fwcount; idx++) {
1388                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1389                                    "reject_firmware: Failed to find %s",
1390                                    fwnames[idx]);
1391                 }
1392         }
1393         return ret;
1394 }
1395
1396
1397 /*
1398  * pvr2_upload_firmware1().
1399  *
1400  * Send the 8051 firmware to the device.  After the upload, arrange for
1401  * device to re-enumerate.
1402  *
1403  * NOTE : the pointer to the firmware data given by reject_firmware()
1404  * is not suitable for an usb transaction.
1405  *
1406  */
1407 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1408 {
1409         const struct firmware *fw_entry = NULL;
1410         void  *fw_ptr;
1411         unsigned int pipe;
1412         unsigned int fwsize;
1413         int ret;
1414         u16 address;
1415
1416         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1417                 hdw->fw1_state = FW1_STATE_OK;
1418                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1419                            "Connected device type defines no firmware to upload; ignoring firmware");
1420                 return -ENOTTY;
1421         }
1422
1423         hdw->fw1_state = FW1_STATE_FAILED; // default result
1424
1425         trace_firmware("pvr2_upload_firmware1");
1426
1427         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1428                                    hdw->hdw_desc->fx2_firmware.cnt,
1429                                    hdw->hdw_desc->fx2_firmware.lst);
1430         if (ret < 0) {
1431                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1432                 return ret;
1433         }
1434
1435         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1436
1437         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1438         fwsize = fw_entry->size;
1439
1440         if ((fwsize != 0x2000) &&
1441             (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1442                 if (hdw->hdw_desc->flag_fx2_16kb) {
1443                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1444                                    "Wrong fx2 firmware size (expected 8192 or 16384, got %u)",
1445                                    fwsize);
1446                 } else {
1447                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1448                                    "Wrong fx2 firmware size (expected 8192, got %u)",
1449                                    fwsize);
1450                 }
1451                 release_firmware(fw_entry);
1452                 return -ENOMEM;
1453         }
1454
1455         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1456         if (fw_ptr == NULL){
1457                 release_firmware(fw_entry);
1458                 return -ENOMEM;
1459         }
1460
1461         /* We have to hold the CPU during firmware upload. */
1462         pvr2_hdw_cpureset_assert(hdw,1);
1463
1464         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1465            chunk. */
1466
1467         ret = 0;
1468         for (address = 0; address < fwsize; address += 0x800) {
1469                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1470                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1471                                        0, fw_ptr, 0x800, HZ);
1472         }
1473
1474         trace_firmware("Upload done, releasing device's CPU");
1475
1476         /* Now release the CPU.  It will disconnect and reconnect later. */
1477         pvr2_hdw_cpureset_assert(hdw,0);
1478
1479         kfree(fw_ptr);
1480         release_firmware(fw_entry);
1481
1482         trace_firmware("Upload done (%d bytes sent)",ret);
1483
1484         /* We should have written fwsize bytes */
1485         if (ret == fwsize) {
1486                 hdw->fw1_state = FW1_STATE_RELOAD;
1487                 return 0;
1488         }
1489
1490         return -EIO;
1491 }
1492
1493
1494 /*
1495  * pvr2_upload_firmware2()
1496  *
1497  * This uploads encoder firmware on endpoint 2.
1498  *
1499  */
1500
1501 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1502 {
1503         const struct firmware *fw_entry = NULL;
1504         void  *fw_ptr;
1505         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1506         int actual_length;
1507         int ret = 0;
1508         int fwidx;
1509         static const char *fw_files[] = {
1510                 CX2341X_FIRM_ENC_FILENAME,
1511         };
1512
1513         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1514                 return 0;
1515         }
1516
1517         trace_firmware("pvr2_upload_firmware2");
1518
1519         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1520                                    ARRAY_SIZE(fw_files), fw_files);
1521         if (ret < 0) return ret;
1522         fwidx = ret;
1523         ret = 0;
1524         /* Since we're about to completely reinitialize the encoder,
1525            invalidate our cached copy of its configuration state.  Next
1526            time we configure the encoder, then we'll fully configure it. */
1527         hdw->enc_cur_valid = 0;
1528
1529         /* Encoder is about to be reset so note that as far as we're
1530            concerned now, the encoder has never been run. */
1531         del_timer_sync(&hdw->encoder_run_timer);
1532         if (hdw->state_encoder_runok) {
1533                 hdw->state_encoder_runok = 0;
1534                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1535         }
1536
1537         /* First prepare firmware loading */
1538         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1539         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1540         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1541         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1542         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1543         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1544         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1545         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1546         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1547         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1548         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1549         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1550         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1551         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1552         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1553         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1554         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1555         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1556
1557         if (ret) {
1558                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1559                            "firmware2 upload prep failed, ret=%d",ret);
1560                 release_firmware(fw_entry);
1561                 goto done;
1562         }
1563
1564         /* Now send firmware */
1565
1566         fw_len = fw_entry->size;
1567
1568         if (fw_len % sizeof(u32)) {
1569                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1570                            "size of %s firmware must be a multiple of %zu bytes",
1571                            fw_files[fwidx],sizeof(u32));
1572                 release_firmware(fw_entry);
1573                 ret = -EINVAL;
1574                 goto done;
1575         }
1576
1577         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1578         if (fw_ptr == NULL){
1579                 release_firmware(fw_entry);
1580                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1581                            "failed to allocate memory for firmware2 upload");
1582                 ret = -ENOMEM;
1583                 goto done;
1584         }
1585
1586         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1587
1588         fw_done = 0;
1589         for (fw_done = 0; fw_done < fw_len;) {
1590                 bcnt = fw_len - fw_done;
1591                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1592                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1593                 /* Usbsnoop log shows that we must swap bytes... */
1594                 /* Some background info: The data being swapped here is a
1595                    firmware image destined for the mpeg encoder chip that
1596                    lives at the other end of a USB endpoint.  The encoder
1597                    chip always talks in 32 bit chunks and its storage is
1598                    organized into 32 bit words.  However from the file
1599                    system to the encoder chip everything is purely a byte
1600                    stream.  The firmware file's contents are always 32 bit
1601                    swapped from what the encoder expects.  Thus the need
1602                    always exists to swap the bytes regardless of the endian
1603                    type of the host processor and therefore swab32() makes
1604                    the most sense. */
1605                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1606                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1607
1608                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1609                                     &actual_length, HZ);
1610                 ret |= (actual_length != bcnt);
1611                 if (ret) break;
1612                 fw_done += bcnt;
1613         }
1614
1615         trace_firmware("upload of %s : %i / %i ",
1616                        fw_files[fwidx],fw_done,fw_len);
1617
1618         kfree(fw_ptr);
1619         release_firmware(fw_entry);
1620
1621         if (ret) {
1622                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1623                            "firmware2 upload transfer failure");
1624                 goto done;
1625         }
1626
1627         /* Finish upload */
1628
1629         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1630         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1631         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1632
1633         if (ret) {
1634                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1635                            "firmware2 upload post-proc failure");
1636         }
1637
1638  done:
1639         if (hdw->hdw_desc->signal_routing_scheme ==
1640             PVR2_ROUTING_SCHEME_GOTVIEW) {
1641                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1642                    hardware. */
1643                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1644         }
1645         return ret;
1646 }
1647
1648
1649 static const char *pvr2_get_state_name(unsigned int st)
1650 {
1651         if (st < ARRAY_SIZE(pvr2_state_names)) {
1652                 return pvr2_state_names[st];
1653         }
1654         return "???";
1655 }
1656
1657 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1658 {
1659         /* Even though we really only care about the video decoder chip at
1660            this point, we'll broadcast stream on/off to all sub-devices
1661            anyway, just in case somebody else wants to hear the
1662            command... */
1663         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1664                    (enablefl ? "on" : "off"));
1665         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1666         v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1667         if (hdw->decoder_client_id) {
1668                 /* We get here if the encoder has been noticed.  Otherwise
1669                    we'll issue a warning to the user (which should
1670                    normally never happen). */
1671                 return 0;
1672         }
1673         if (!hdw->flag_decoder_missed) {
1674                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1675                            "***WARNING*** No decoder present");
1676                 hdw->flag_decoder_missed = !0;
1677                 trace_stbit("flag_decoder_missed",
1678                             hdw->flag_decoder_missed);
1679         }
1680         return -EIO;
1681 }
1682
1683
1684 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1685 {
1686         return hdw->master_state;
1687 }
1688
1689
1690 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1691 {
1692         if (!hdw->flag_tripped) return 0;
1693         hdw->flag_tripped = 0;
1694         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1695                    "Clearing driver error status");
1696         return !0;
1697 }
1698
1699
1700 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1701 {
1702         int fl;
1703         LOCK_TAKE(hdw->big_lock); do {
1704                 fl = pvr2_hdw_untrip_unlocked(hdw);
1705         } while (0); LOCK_GIVE(hdw->big_lock);
1706         if (fl) pvr2_hdw_state_sched(hdw);
1707         return 0;
1708 }
1709
1710
1711
1712
1713 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1714 {
1715         return hdw->state_pipeline_req != 0;
1716 }
1717
1718
1719 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1720 {
1721         int ret,st;
1722         LOCK_TAKE(hdw->big_lock); do {
1723                 pvr2_hdw_untrip_unlocked(hdw);
1724                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1725                         hdw->state_pipeline_req = enable_flag != 0;
1726                         pvr2_trace(PVR2_TRACE_START_STOP,
1727                                    "/*--TRACE_STREAM--*/ %s",
1728                                    enable_flag ? "enable" : "disable");
1729                 }
1730                 pvr2_hdw_state_sched(hdw);
1731         } while (0); LOCK_GIVE(hdw->big_lock);
1732         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1733         if (enable_flag) {
1734                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1735                         if (st != PVR2_STATE_READY) return -EIO;
1736                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1737                 }
1738         }
1739         return 0;
1740 }
1741
1742
1743 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1744 {
1745         int fl;
1746         LOCK_TAKE(hdw->big_lock);
1747         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1748                 hdw->desired_stream_type = config;
1749                 hdw->state_pipeline_config = 0;
1750                 trace_stbit("state_pipeline_config",
1751                             hdw->state_pipeline_config);
1752                 pvr2_hdw_state_sched(hdw);
1753         }
1754         LOCK_GIVE(hdw->big_lock);
1755         if (fl) return 0;
1756         return pvr2_hdw_wait(hdw,0);
1757 }
1758
1759
1760 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1761 {
1762         int unit_number = hdw->unit_number;
1763         int tp = -1;
1764         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1765                 tp = tuner[unit_number];
1766         }
1767         if (tp < 0) return -EINVAL;
1768         hdw->tuner_type = tp;
1769         hdw->tuner_updated = !0;
1770         return 0;
1771 }
1772
1773
1774 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1775 {
1776         int unit_number = hdw->unit_number;
1777         int tp = 0;
1778         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1779                 tp = video_std[unit_number];
1780                 if (tp) return tp;
1781         }
1782         return 0;
1783 }
1784
1785
1786 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1787 {
1788         int unit_number = hdw->unit_number;
1789         int tp = 0;
1790         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1791                 tp = tolerance[unit_number];
1792         }
1793         return tp;
1794 }
1795
1796
1797 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1798 {
1799         /* Try a harmless request to fetch the eeprom's address over
1800            endpoint 1.  See what happens.  Only the full FX2 image can
1801            respond to this.  If this probe fails then likely the FX2
1802            firmware needs be loaded. */
1803         int result;
1804         LOCK_TAKE(hdw->ctl_lock); do {
1805                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1806                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1807                                            hdw->cmd_buffer,1,
1808                                            hdw->cmd_buffer,1);
1809                 if (result < 0) break;
1810         } while(0); LOCK_GIVE(hdw->ctl_lock);
1811         if (result) {
1812                 pvr2_trace(PVR2_TRACE_INIT,
1813                            "Probe of device endpoint 1 result status %d",
1814                            result);
1815         } else {
1816                 pvr2_trace(PVR2_TRACE_INIT,
1817                            "Probe of device endpoint 1 succeeded");
1818         }
1819         return result == 0;
1820 }
1821
1822 struct pvr2_std_hack {
1823         v4l2_std_id pat;  /* Pattern to match */
1824         v4l2_std_id msk;  /* Which bits we care about */
1825         v4l2_std_id std;  /* What additional standards or default to set */
1826 };
1827
1828 /* This data structure labels specific combinations of standards from
1829    tveeprom that we'll try to recognize.  If we recognize one, then assume
1830    a specified default standard to use.  This is here because tveeprom only
1831    tells us about available standards not the intended default standard (if
1832    any) for the device in question.  We guess the default based on what has
1833    been reported as available.  Note that this is only for guessing a
1834    default - which can always be overridden explicitly - and if the user
1835    has otherwise named a default then that default will always be used in
1836    place of this table. */
1837 static const struct pvr2_std_hack std_eeprom_maps[] = {
1838         {       /* PAL(B/G) */
1839                 .pat = V4L2_STD_B|V4L2_STD_GH,
1840                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1841         },
1842         {       /* NTSC(M) */
1843                 .pat = V4L2_STD_MN,
1844                 .std = V4L2_STD_NTSC_M,
1845         },
1846         {       /* PAL(I) */
1847                 .pat = V4L2_STD_PAL_I,
1848                 .std = V4L2_STD_PAL_I,
1849         },
1850         {       /* SECAM(L/L') */
1851                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1852                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1853         },
1854         {       /* PAL(D/D1/K) */
1855                 .pat = V4L2_STD_DK,
1856                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1857         },
1858 };
1859
1860 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1861 {
1862         char buf[40];
1863         unsigned int bcnt;
1864         v4l2_std_id std1,std2,std3;
1865
1866         std1 = get_default_standard(hdw);
1867         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1868
1869         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1870         pvr2_trace(PVR2_TRACE_STD,
1871                    "Supported video standard(s) reported available in hardware: %.*s",
1872                    bcnt,buf);
1873
1874         hdw->std_mask_avail = hdw->std_mask_eeprom;
1875
1876         std2 = (std1|std3) & ~hdw->std_mask_avail;
1877         if (std2) {
1878                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1879                 pvr2_trace(PVR2_TRACE_STD,
1880                            "Expanding supported video standards to include: %.*s",
1881                            bcnt,buf);
1882                 hdw->std_mask_avail |= std2;
1883         }
1884
1885         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1886
1887         if (std1) {
1888                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1889                 pvr2_trace(PVR2_TRACE_STD,
1890                            "Initial video standard forced to %.*s",
1891                            bcnt,buf);
1892                 hdw->std_mask_cur = std1;
1893                 hdw->std_dirty = !0;
1894                 return;
1895         }
1896         if (std3) {
1897                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1898                 pvr2_trace(PVR2_TRACE_STD,
1899                            "Initial video standard (determined by device type): %.*s",
1900                            bcnt, buf);
1901                 hdw->std_mask_cur = std3;
1902                 hdw->std_dirty = !0;
1903                 return;
1904         }
1905
1906         {
1907                 unsigned int idx;
1908                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1909                         if (std_eeprom_maps[idx].msk ?
1910                             ((std_eeprom_maps[idx].pat ^
1911                              hdw->std_mask_eeprom) &
1912                              std_eeprom_maps[idx].msk) :
1913                             (std_eeprom_maps[idx].pat !=
1914                              hdw->std_mask_eeprom)) continue;
1915                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1916                                                   std_eeprom_maps[idx].std);
1917                         pvr2_trace(PVR2_TRACE_STD,
1918                                    "Initial video standard guessed as %.*s",
1919                                    bcnt,buf);
1920                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1921                         hdw->std_dirty = !0;
1922                         return;
1923                 }
1924         }
1925
1926 }
1927
1928
1929 static unsigned int pvr2_copy_i2c_addr_list(
1930         unsigned short *dst, const unsigned char *src,
1931         unsigned int dst_max)
1932 {
1933         unsigned int cnt = 0;
1934         if (!src) return 0;
1935         while (src[cnt] && (cnt + 1) < dst_max) {
1936                 dst[cnt] = src[cnt];
1937                 cnt++;
1938         }
1939         dst[cnt] = I2C_CLIENT_END;
1940         return cnt;
1941 }
1942
1943
1944 static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
1945 {
1946         /*
1947           Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
1948           for cx25840 causes that module to correctly set up its video
1949           scaling.  This is really a problem in the cx25840 module itself,
1950           but we work around it here.  The problem has not been seen in
1951           ivtv because there VBI is supported and set up.  We don't do VBI
1952           here (at least not yet) and thus we never attempted to even set
1953           it up.
1954         */
1955         struct v4l2_format fmt;
1956         if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
1957                 /* We're not using a cx25840 so don't enable the hack */
1958                 return;
1959         }
1960
1961         pvr2_trace(PVR2_TRACE_INIT,
1962                    "Module ID %u: Executing cx25840 VBI hack",
1963                    hdw->decoder_client_id);
1964         memset(&fmt, 0, sizeof(fmt));
1965         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
1966         fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
1967         fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
1968         v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
1969                              vbi, s_sliced_fmt, &fmt.fmt.sliced);
1970 }
1971
1972
1973 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1974                                 const struct pvr2_device_client_desc *cd)
1975 {
1976         const char *fname;
1977         unsigned char mid;
1978         struct v4l2_subdev *sd;
1979         unsigned int i2ccnt;
1980         const unsigned char *p;
1981         /* Arbitrary count - max # i2c addresses we will probe */
1982         unsigned short i2caddr[25];
1983
1984         mid = cd->module_id;
1985         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
1986         if (!fname) {
1987                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1988                            "Module ID %u for device %s has no name?  The driver might have a configuration problem.",
1989                            mid,
1990                            hdw->hdw_desc->description);
1991                 return -EINVAL;
1992         }
1993         pvr2_trace(PVR2_TRACE_INIT,
1994                    "Module ID %u (%s) for device %s being loaded...",
1995                    mid, fname,
1996                    hdw->hdw_desc->description);
1997
1998         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
1999                                          ARRAY_SIZE(i2caddr));
2000         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2001                          module_i2c_addresses[mid] : NULL) != NULL)) {
2002                 /* Second chance: Try default i2c address list */
2003                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2004                                                  ARRAY_SIZE(i2caddr));
2005                 if (i2ccnt) {
2006                         pvr2_trace(PVR2_TRACE_INIT,
2007                                    "Module ID %u: Using default i2c address list",
2008                                    mid);
2009                 }
2010         }
2011
2012         if (!i2ccnt) {
2013                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2014                            "Module ID %u (%s) for device %s: No i2c addresses.  The driver might have a configuration problem.",
2015                            mid, fname, hdw->hdw_desc->description);
2016                 return -EINVAL;
2017         }
2018
2019         if (i2ccnt == 1) {
2020                 pvr2_trace(PVR2_TRACE_INIT,
2021                            "Module ID %u: Setting up with specified i2c address 0x%x",
2022                            mid, i2caddr[0]);
2023                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2024                                          fname, i2caddr[0], NULL);
2025         } else {
2026                 pvr2_trace(PVR2_TRACE_INIT,
2027                            "Module ID %u: Setting up with address probe list",
2028                            mid);
2029                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2030                                          fname, 0, i2caddr);
2031         }
2032
2033         if (!sd) {
2034                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2035                            "Module ID %u (%s) for device %s failed to load.  Possible missing sub-device kernel module or initialization failure within module.",
2036                            mid, fname, hdw->hdw_desc->description);
2037                 return -EIO;
2038         }
2039
2040         /* Tag this sub-device instance with the module ID we know about.
2041            In other places we'll use that tag to determine if the instance
2042            requires special handling. */
2043         sd->grp_id = mid;
2044
2045         pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2046
2047
2048         /* client-specific setup... */
2049         switch (mid) {
2050         case PVR2_CLIENT_ID_CX25840:
2051         case PVR2_CLIENT_ID_SAA7115:
2052                 hdw->decoder_client_id = mid;
2053                 break;
2054         default: break;
2055         }
2056
2057         return 0;
2058 }
2059
2060
2061 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2062 {
2063         unsigned int idx;
2064         const struct pvr2_string_table *cm;
2065         const struct pvr2_device_client_table *ct;
2066         int okFl = !0;
2067
2068         cm = &hdw->hdw_desc->client_modules;
2069         for (idx = 0; idx < cm->cnt; idx++) {
2070                 request_module(cm->lst[idx]);
2071         }
2072
2073         ct = &hdw->hdw_desc->client_table;
2074         for (idx = 0; idx < ct->cnt; idx++) {
2075                 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2076         }
2077         if (!okFl) {
2078                 hdw->flag_modulefail = !0;
2079                 pvr2_hdw_render_useless(hdw);
2080         }
2081 }
2082
2083
2084 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2085 {
2086         int ret;
2087         unsigned int idx;
2088         struct pvr2_ctrl *cptr;
2089         int reloadFl = 0;
2090         if (hdw->hdw_desc->fx2_firmware.cnt) {
2091                 if (!reloadFl) {
2092                         reloadFl =
2093                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2094                                  == 0);
2095                         if (reloadFl) {
2096                                 pvr2_trace(PVR2_TRACE_INIT,
2097                                            "USB endpoint config looks strange; possibly firmware needs to be loaded");
2098                         }
2099                 }
2100                 if (!reloadFl) {
2101                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2102                         if (reloadFl) {
2103                                 pvr2_trace(PVR2_TRACE_INIT,
2104                                            "Check for FX2 firmware failed; possibly firmware needs to be loaded");
2105                         }
2106                 }
2107                 if (reloadFl) {
2108                         if (pvr2_upload_firmware1(hdw) != 0) {
2109                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2110                                            "Failure uploading firmware1");
2111                         }
2112                         return;
2113                 }
2114         }
2115         hdw->fw1_state = FW1_STATE_OK;
2116
2117         if (!pvr2_hdw_dev_ok(hdw)) return;
2118
2119         hdw->force_dirty = !0;
2120
2121         if (!hdw->hdw_desc->flag_no_powerup) {
2122                 pvr2_hdw_cmd_powerup(hdw);
2123                 if (!pvr2_hdw_dev_ok(hdw)) return;
2124         }
2125
2126         /* Take the IR chip out of reset, if appropriate */
2127         if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2128                 pvr2_issue_simple_cmd(hdw,
2129                                       FX2CMD_HCW_ZILOG_RESET |
2130                                       (1 << 8) |
2131                                       ((0) << 16));
2132         }
2133
2134         /* This step MUST happen after the earlier powerup step */
2135         pvr2_i2c_core_init(hdw);
2136         if (!pvr2_hdw_dev_ok(hdw)) return;
2137
2138         /* Reset demod only on Hauppauge 160xxx platform */
2139         if (le16_to_cpu(hdw->usb_dev->descriptor.idVendor) == 0x2040 &&
2140             (le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7502 ||
2141              le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7510)) {
2142                 pr_info("%s(): resetting 160xxx demod\n", __func__);
2143                 /* TODO: not sure this is proper place to reset once only */
2144                 pvr2_issue_simple_cmd(hdw,
2145                                       FX2CMD_HCW_DEMOD_RESET_PIN |
2146                                       (1 << 8) |
2147                                       ((0) << 16));
2148                 usleep_range(10000, 10500);
2149                 pvr2_issue_simple_cmd(hdw,
2150                                       FX2CMD_HCW_DEMOD_RESET_PIN |
2151                                       (1 << 8) |
2152                                       ((1) << 16));
2153                 usleep_range(10000, 10500);
2154         }
2155
2156         pvr2_hdw_load_modules(hdw);
2157         if (!pvr2_hdw_dev_ok(hdw)) return;
2158
2159         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2160
2161         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2162                 cptr = hdw->controls + idx;
2163                 if (cptr->info->skip_init) continue;
2164                 if (!cptr->info->set_value) continue;
2165                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2166         }
2167
2168         pvr2_hdw_cx25840_vbi_hack(hdw);
2169
2170         /* Set up special default values for the television and radio
2171            frequencies here.  It's not really important what these defaults
2172            are, but I set them to something usable in the Chicago area just
2173            to make driver testing a little easier. */
2174
2175         hdw->freqValTelevision = default_tv_freq;
2176         hdw->freqValRadio = default_radio_freq;
2177
2178         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2179         // thread-safe against the normal pvr2_send_request() mechanism.
2180         // (We should make it thread safe).
2181
2182         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2183                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2184                 if (!pvr2_hdw_dev_ok(hdw)) return;
2185                 if (ret < 0) {
2186                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2187                                    "Unable to determine location of eeprom, skipping");
2188                 } else {
2189                         hdw->eeprom_addr = ret;
2190                         pvr2_eeprom_analyze(hdw);
2191                         if (!pvr2_hdw_dev_ok(hdw)) return;
2192                 }
2193         } else {
2194                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2195                 hdw->tuner_updated = !0;
2196                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2197         }
2198
2199         if (hdw->serial_number) {
2200                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2201                                 "sn-%lu", hdw->serial_number);
2202         } else if (hdw->unit_number >= 0) {
2203                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2204                                 "unit-%c",
2205                                 hdw->unit_number + 'a');
2206         } else {
2207                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2208                                 "unit-??");
2209         }
2210         hdw->identifier[idx] = 0;
2211
2212         pvr2_hdw_setup_std(hdw);
2213
2214         if (!get_default_tuner_type(hdw)) {
2215                 pvr2_trace(PVR2_TRACE_INIT,
2216                            "pvr2_hdw_setup: Tuner type overridden to %d",
2217                            hdw->tuner_type);
2218         }
2219
2220
2221         if (!pvr2_hdw_dev_ok(hdw)) return;
2222
2223         if (hdw->hdw_desc->signal_routing_scheme ==
2224             PVR2_ROUTING_SCHEME_GOTVIEW) {
2225                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2226                    hardware. */
2227                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2228         }
2229
2230         pvr2_hdw_commit_setup(hdw);
2231
2232         hdw->vid_stream = pvr2_stream_create();
2233         if (!pvr2_hdw_dev_ok(hdw)) return;
2234         pvr2_trace(PVR2_TRACE_INIT,
2235                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2236         if (hdw->vid_stream) {
2237                 idx = get_default_error_tolerance(hdw);
2238                 if (idx) {
2239                         pvr2_trace(PVR2_TRACE_INIT,
2240                                    "pvr2_hdw_setup: video stream %p setting tolerance %u",
2241                                    hdw->vid_stream,idx);
2242                 }
2243                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2244                                   PVR2_VID_ENDPOINT,idx);
2245         }
2246
2247         if (!pvr2_hdw_dev_ok(hdw)) return;
2248
2249         hdw->flag_init_ok = !0;
2250
2251         pvr2_hdw_state_sched(hdw);
2252 }
2253
2254
2255 /* Set up the structure and attempt to put the device into a usable state.
2256    This can be a time-consuming operation, which is why it is not done
2257    internally as part of the create() step. */
2258 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2259 {
2260         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2261         do {
2262                 pvr2_hdw_setup_low(hdw);
2263                 pvr2_trace(PVR2_TRACE_INIT,
2264                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2265                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2266                 if (pvr2_hdw_dev_ok(hdw)) {
2267                         if (hdw->flag_init_ok) {
2268                                 pvr2_trace(
2269                                         PVR2_TRACE_INFO,
2270                                         "Device initialization completed successfully.");
2271                                 break;
2272                         }
2273                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2274                                 pvr2_trace(
2275                                         PVR2_TRACE_INFO,
2276                                         "Device microcontroller firmware (re)loaded; it should now reset and reconnect.");
2277                                 break;
2278                         }
2279                         pvr2_trace(
2280                                 PVR2_TRACE_ERROR_LEGS,
2281                                 "Device initialization was not successful.");
2282                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2283                                 pvr2_trace(
2284                                         PVR2_TRACE_ERROR_LEGS,
2285                                         "Giving up since device microcontroller firmware appears to be missing.");
2286                                 break;
2287                         }
2288                 }
2289                 if (hdw->flag_modulefail) {
2290                         pvr2_trace(
2291                                 PVR2_TRACE_ERROR_LEGS,
2292                                 "***WARNING*** pvrusb2 driver initialization failed due to the failure of one or more sub-device kernel modules.");
2293                         pvr2_trace(
2294                                 PVR2_TRACE_ERROR_LEGS,
2295                                 "You need to resolve the failing condition before this driver can function.  There should be some earlier messages giving more information about the problem.");
2296                         break;
2297                 }
2298                 if (procreload) {
2299                         pvr2_trace(
2300                                 PVR2_TRACE_ERROR_LEGS,
2301                                 "Attempting pvrusb2 recovery by reloading primary firmware.");
2302                         pvr2_trace(
2303                                 PVR2_TRACE_ERROR_LEGS,
2304                                 "If this works, device should disconnect and reconnect in a sane state.");
2305                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2306                         pvr2_upload_firmware1(hdw);
2307                 } else {
2308                         pvr2_trace(
2309                                 PVR2_TRACE_ERROR_LEGS,
2310                                 "***WARNING*** pvrusb2 device hardware appears to be jammed and I can't clear it.");
2311                         pvr2_trace(
2312                                 PVR2_TRACE_ERROR_LEGS,
2313                                 "You might need to power cycle the pvrusb2 device in order to recover.");
2314                 }
2315         } while (0);
2316         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2317 }
2318
2319
2320 /* Perform second stage initialization.  Set callback pointer first so that
2321    we can avoid a possible initialization race (if the kernel thread runs
2322    before the callback has been set). */
2323 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2324                         void (*callback_func)(void *),
2325                         void *callback_data)
2326 {
2327         LOCK_TAKE(hdw->big_lock); do {
2328                 if (hdw->flag_disconnected) {
2329                         /* Handle a race here: If we're already
2330                            disconnected by this point, then give up.  If we
2331                            get past this then we'll remain connected for
2332                            the duration of initialization since the entire
2333                            initialization sequence is now protected by the
2334                            big_lock. */
2335                         break;
2336                 }
2337                 hdw->state_data = callback_data;
2338                 hdw->state_func = callback_func;
2339                 pvr2_hdw_setup(hdw);
2340         } while (0); LOCK_GIVE(hdw->big_lock);
2341         return hdw->flag_init_ok;
2342 }
2343
2344
2345 /* Create, set up, and return a structure for interacting with the
2346    underlying hardware.  */
2347 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2348                                  const struct usb_device_id *devid)
2349 {
2350         unsigned int idx,cnt1,cnt2,m;
2351         struct pvr2_hdw *hdw = NULL;
2352         int valid_std_mask;
2353         struct pvr2_ctrl *cptr;
2354         struct usb_device *usb_dev;
2355         const struct pvr2_device_desc *hdw_desc;
2356         __u8 ifnum;
2357         struct v4l2_queryctrl qctrl;
2358         struct pvr2_ctl_info *ciptr;
2359
2360         usb_dev = interface_to_usbdev(intf);
2361
2362         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2363
2364         if (hdw_desc == NULL) {
2365                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create: No device description pointer, unable to continue.");
2366                 pvr2_trace(PVR2_TRACE_INIT,
2367                            "If you have a new device type, please contact Mike Isely <isely@pobox.com> to get it included in the driver");
2368                 goto fail;
2369         }
2370
2371         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2372         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2373                    hdw,hdw_desc->description);
2374         pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
2375                 hdw_desc->description);
2376         if (hdw_desc->flag_is_experimental) {
2377                 pvr2_trace(PVR2_TRACE_INFO, "**********");
2378                 pvr2_trace(PVR2_TRACE_INFO,
2379                            "***WARNING*** Support for this device (%s) is experimental.",
2380                                                               hdw_desc->description);
2381                 pvr2_trace(PVR2_TRACE_INFO,
2382                            "Important functionality might not be entirely working.");
2383                 pvr2_trace(PVR2_TRACE_INFO,
2384                            "Please consider contacting the driver author to help with further stabilization of the driver.");
2385                 pvr2_trace(PVR2_TRACE_INFO, "**********");
2386         }
2387         if (!hdw) goto fail;
2388
2389         timer_setup(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout, 0);
2390
2391         timer_setup(&hdw->decoder_stabilization_timer,
2392                     pvr2_hdw_decoder_stabilization_timeout, 0);
2393
2394         timer_setup(&hdw->encoder_wait_timer, pvr2_hdw_encoder_wait_timeout,
2395                     0);
2396
2397         timer_setup(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout, 0);
2398
2399         hdw->master_state = PVR2_STATE_DEAD;
2400
2401         init_waitqueue_head(&hdw->state_wait_data);
2402
2403         hdw->tuner_signal_stale = !0;
2404         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2405
2406         /* Calculate which inputs are OK */
2407         m = 0;
2408         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2409         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2410                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2411         }
2412         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2413         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2414         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2415         hdw->input_avail_mask = m;
2416         hdw->input_allowed_mask = hdw->input_avail_mask;
2417
2418         /* If not a hybrid device, pathway_state never changes.  So
2419            initialize it here to what it should forever be. */
2420         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2421                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2422         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2423                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2424         }
2425
2426         hdw->control_cnt = CTRLDEF_COUNT;
2427         hdw->control_cnt += MPEGDEF_COUNT;
2428         hdw->controls = kcalloc(hdw->control_cnt, sizeof(struct pvr2_ctrl),
2429                                 GFP_KERNEL);
2430         if (!hdw->controls) goto fail;
2431         hdw->hdw_desc = hdw_desc;
2432         hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2433         for (idx = 0; idx < hdw->control_cnt; idx++) {
2434                 cptr = hdw->controls + idx;
2435                 cptr->hdw = hdw;
2436         }
2437         for (idx = 0; idx < 32; idx++) {
2438                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2439         }
2440         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2441                 cptr = hdw->controls + idx;
2442                 cptr->info = control_defs+idx;
2443         }
2444
2445         /* Ensure that default input choice is a valid one. */
2446         m = hdw->input_avail_mask;
2447         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2448                 if (!((1 << idx) & m)) continue;
2449                 hdw->input_val = idx;
2450                 break;
2451         }
2452
2453         /* Define and configure additional controls from cx2341x module. */
2454         hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT,
2455                                       sizeof(*(hdw->mpeg_ctrl_info)),
2456                                       GFP_KERNEL);
2457         if (!hdw->mpeg_ctrl_info) goto fail;
2458         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2459                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2460                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2461                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2462                 ciptr->name = mpeg_ids[idx].strid;
2463                 ciptr->v4l_id = mpeg_ids[idx].id;
2464                 ciptr->skip_init = !0;
2465                 ciptr->get_value = ctrl_cx2341x_get;
2466                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2467                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2468                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2469                 qctrl.id = ciptr->v4l_id;
2470                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2471                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2472                         ciptr->set_value = ctrl_cx2341x_set;
2473                 }
2474                 strscpy(hdw->mpeg_ctrl_info[idx].desc, qctrl.name,
2475                         sizeof(hdw->mpeg_ctrl_info[idx].desc));
2476                 ciptr->default_value = qctrl.default_value;
2477                 switch (qctrl.type) {
2478                 default:
2479                 case V4L2_CTRL_TYPE_INTEGER:
2480                         ciptr->type = pvr2_ctl_int;
2481                         ciptr->def.type_int.min_value = qctrl.minimum;
2482                         ciptr->def.type_int.max_value = qctrl.maximum;
2483                         break;
2484                 case V4L2_CTRL_TYPE_BOOLEAN:
2485                         ciptr->type = pvr2_ctl_bool;
2486                         break;
2487                 case V4L2_CTRL_TYPE_MENU:
2488                         ciptr->type = pvr2_ctl_enum;
2489                         ciptr->def.type_enum.value_names =
2490                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2491                                                                 ciptr->v4l_id);
2492                         for (cnt1 = 0;
2493                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2494                              cnt1++) { }
2495                         ciptr->def.type_enum.count = cnt1;
2496                         break;
2497                 }
2498                 cptr->info = ciptr;
2499         }
2500
2501         // Initialize control data regarding video standard masks
2502         valid_std_mask = pvr2_std_get_usable();
2503         for (idx = 0; idx < 32; idx++) {
2504                 if (!(valid_std_mask & (1 << idx))) continue;
2505                 cnt1 = pvr2_std_id_to_str(
2506                         hdw->std_mask_names[idx],
2507                         sizeof(hdw->std_mask_names[idx])-1,
2508                         1 << idx);
2509                 hdw->std_mask_names[idx][cnt1] = 0;
2510         }
2511         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2512         if (cptr) {
2513                 memcpy(&hdw->std_info_avail,cptr->info,
2514                        sizeof(hdw->std_info_avail));
2515                 cptr->info = &hdw->std_info_avail;
2516                 hdw->std_info_avail.def.type_bitmask.bit_names =
2517                         hdw->std_mask_ptrs;
2518                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2519                         valid_std_mask;
2520         }
2521         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2522         if (cptr) {
2523                 memcpy(&hdw->std_info_cur,cptr->info,
2524                        sizeof(hdw->std_info_cur));
2525                 cptr->info = &hdw->std_info_cur;
2526                 hdw->std_info_cur.def.type_bitmask.bit_names =
2527                         hdw->std_mask_ptrs;
2528                 hdw->std_info_cur.def.type_bitmask.valid_bits =
2529                         valid_std_mask;
2530         }
2531         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT);
2532         if (cptr) {
2533                 memcpy(&hdw->std_info_detect,cptr->info,
2534                        sizeof(hdw->std_info_detect));
2535                 cptr->info = &hdw->std_info_detect;
2536                 hdw->std_info_detect.def.type_bitmask.bit_names =
2537                         hdw->std_mask_ptrs;
2538                 hdw->std_info_detect.def.type_bitmask.valid_bits =
2539                         valid_std_mask;
2540         }
2541
2542         hdw->cropcap_stale = !0;
2543         hdw->eeprom_addr = -1;
2544         hdw->unit_number = -1;
2545         hdw->v4l_minor_number_video = -1;
2546         hdw->v4l_minor_number_vbi = -1;
2547         hdw->v4l_minor_number_radio = -1;
2548         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2549         if (!hdw->ctl_write_buffer) goto fail;
2550         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2551         if (!hdw->ctl_read_buffer) goto fail;
2552         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2553         if (!hdw->ctl_write_urb) goto fail;
2554         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2555         if (!hdw->ctl_read_urb) goto fail;
2556
2557         if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2558                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2559                            "Error registering with v4l core, giving up");
2560                 goto fail;
2561         }
2562         mutex_lock(&pvr2_unit_mtx);
2563         do {
2564                 for (idx = 0; idx < PVR_NUM; idx++) {
2565                         if (unit_pointers[idx]) continue;
2566                         hdw->unit_number = idx;
2567                         unit_pointers[idx] = hdw;
2568                         break;
2569                 }
2570         } while (0);
2571         mutex_unlock(&pvr2_unit_mtx);
2572
2573         cnt1 = 0;
2574         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2575         cnt1 += cnt2;
2576         if (hdw->unit_number >= 0) {
2577                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2578                                  ('a' + hdw->unit_number));
2579                 cnt1 += cnt2;
2580         }
2581         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2582         hdw->name[cnt1] = 0;
2583
2584         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2585
2586         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2587                    hdw->unit_number,hdw->name);
2588
2589         hdw->tuner_type = -1;
2590         hdw->flag_ok = !0;
2591
2592         hdw->usb_intf = intf;
2593         hdw->usb_dev = usb_dev;
2594
2595         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2596
2597         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2598         usb_set_interface(hdw->usb_dev,ifnum,0);
2599
2600         mutex_init(&hdw->ctl_lock_mutex);
2601         mutex_init(&hdw->big_lock_mutex);
2602
2603         return hdw;
2604  fail:
2605         if (hdw) {
2606                 del_timer_sync(&hdw->quiescent_timer);
2607                 del_timer_sync(&hdw->decoder_stabilization_timer);
2608                 del_timer_sync(&hdw->encoder_run_timer);
2609                 del_timer_sync(&hdw->encoder_wait_timer);
2610                 flush_work(&hdw->workpoll);
2611                 usb_free_urb(hdw->ctl_read_urb);
2612                 usb_free_urb(hdw->ctl_write_urb);
2613                 kfree(hdw->ctl_read_buffer);
2614                 kfree(hdw->ctl_write_buffer);
2615                 kfree(hdw->controls);
2616                 kfree(hdw->mpeg_ctrl_info);
2617                 kfree(hdw);
2618         }
2619         return NULL;
2620 }
2621
2622
2623 /* Remove _all_ associations between this driver and the underlying USB
2624    layer. */
2625 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2626 {
2627         if (hdw->flag_disconnected) return;
2628         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2629         if (hdw->ctl_read_urb) {
2630                 usb_kill_urb(hdw->ctl_read_urb);
2631                 usb_free_urb(hdw->ctl_read_urb);
2632                 hdw->ctl_read_urb = NULL;
2633         }
2634         if (hdw->ctl_write_urb) {
2635                 usb_kill_urb(hdw->ctl_write_urb);
2636                 usb_free_urb(hdw->ctl_write_urb);
2637                 hdw->ctl_write_urb = NULL;
2638         }
2639         if (hdw->ctl_read_buffer) {
2640                 kfree(hdw->ctl_read_buffer);
2641                 hdw->ctl_read_buffer = NULL;
2642         }
2643         if (hdw->ctl_write_buffer) {
2644                 kfree(hdw->ctl_write_buffer);
2645                 hdw->ctl_write_buffer = NULL;
2646         }
2647         hdw->flag_disconnected = !0;
2648         /* If we don't do this, then there will be a dangling struct device
2649            reference to our disappearing device persisting inside the V4L
2650            core... */
2651         v4l2_device_disconnect(&hdw->v4l2_dev);
2652         hdw->usb_dev = NULL;
2653         hdw->usb_intf = NULL;
2654         pvr2_hdw_render_useless(hdw);
2655 }
2656
2657 void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev)
2658 {
2659         vdev->v4l2_dev = &hdw->v4l2_dev;
2660 }
2661
2662 /* Destroy hardware interaction structure */
2663 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2664 {
2665         if (!hdw) return;
2666         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2667         flush_work(&hdw->workpoll);
2668         del_timer_sync(&hdw->quiescent_timer);
2669         del_timer_sync(&hdw->decoder_stabilization_timer);
2670         del_timer_sync(&hdw->encoder_run_timer);
2671         del_timer_sync(&hdw->encoder_wait_timer);
2672         if (hdw->fw_buffer) {
2673                 kfree(hdw->fw_buffer);
2674                 hdw->fw_buffer = NULL;
2675         }
2676         if (hdw->vid_stream) {
2677                 pvr2_stream_destroy(hdw->vid_stream);
2678                 hdw->vid_stream = NULL;
2679         }
2680         pvr2_i2c_core_done(hdw);
2681         v4l2_device_unregister(&hdw->v4l2_dev);
2682         pvr2_hdw_remove_usb_stuff(hdw);
2683         mutex_lock(&pvr2_unit_mtx);
2684         do {
2685                 if ((hdw->unit_number >= 0) &&
2686                     (hdw->unit_number < PVR_NUM) &&
2687                     (unit_pointers[hdw->unit_number] == hdw)) {
2688                         unit_pointers[hdw->unit_number] = NULL;
2689                 }
2690         } while (0);
2691         mutex_unlock(&pvr2_unit_mtx);
2692         kfree(hdw->controls);
2693         kfree(hdw->mpeg_ctrl_info);
2694         kfree(hdw);
2695 }
2696
2697
2698 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2699 {
2700         return (hdw && hdw->flag_ok);
2701 }
2702
2703
2704 /* Called when hardware has been unplugged */
2705 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2706 {
2707         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2708         LOCK_TAKE(hdw->big_lock);
2709         LOCK_TAKE(hdw->ctl_lock);
2710         pvr2_hdw_remove_usb_stuff(hdw);
2711         LOCK_GIVE(hdw->ctl_lock);
2712         LOCK_GIVE(hdw->big_lock);
2713 }
2714
2715
2716 /* Get the number of defined controls */
2717 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2718 {
2719         return hdw->control_cnt;
2720 }
2721
2722
2723 /* Retrieve a control handle given its index (0..count-1) */
2724 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2725                                              unsigned int idx)
2726 {
2727         if (idx >= hdw->control_cnt) return NULL;
2728         return hdw->controls + idx;
2729 }
2730
2731
2732 /* Retrieve a control handle given its index (0..count-1) */
2733 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2734                                           unsigned int ctl_id)
2735 {
2736         struct pvr2_ctrl *cptr;
2737         unsigned int idx;
2738         int i;
2739
2740         /* This could be made a lot more efficient, but for now... */
2741         for (idx = 0; idx < hdw->control_cnt; idx++) {
2742                 cptr = hdw->controls + idx;
2743                 i = cptr->info->internal_id;
2744                 if (i && (i == ctl_id)) return cptr;
2745         }
2746         return NULL;
2747 }
2748
2749
2750 /* Given a V4L ID, retrieve the control structure associated with it. */
2751 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2752 {
2753         struct pvr2_ctrl *cptr;
2754         unsigned int idx;
2755         int i;
2756
2757         /* This could be made a lot more efficient, but for now... */
2758         for (idx = 0; idx < hdw->control_cnt; idx++) {
2759                 cptr = hdw->controls + idx;
2760                 i = cptr->info->v4l_id;
2761                 if (i && (i == ctl_id)) return cptr;
2762         }
2763         return NULL;
2764 }
2765
2766
2767 /* Given a V4L ID for its immediate predecessor, retrieve the control
2768    structure associated with it. */
2769 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2770                                             unsigned int ctl_id)
2771 {
2772         struct pvr2_ctrl *cptr,*cp2;
2773         unsigned int idx;
2774         int i;
2775
2776         /* This could be made a lot more efficient, but for now... */
2777         cp2 = NULL;
2778         for (idx = 0; idx < hdw->control_cnt; idx++) {
2779                 cptr = hdw->controls + idx;
2780                 i = cptr->info->v4l_id;
2781                 if (!i) continue;
2782                 if (i <= ctl_id) continue;
2783                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2784                 cp2 = cptr;
2785         }
2786         return cp2;
2787         return NULL;
2788 }
2789
2790
2791 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2792 {
2793         switch (tp) {
2794         case pvr2_ctl_int: return "integer";
2795         case pvr2_ctl_enum: return "enum";
2796         case pvr2_ctl_bool: return "boolean";
2797         case pvr2_ctl_bitmask: return "bitmask";
2798         }
2799         return "";
2800 }
2801
2802
2803 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2804                                     const char *name, int val)
2805 {
2806         struct v4l2_control ctrl;
2807         struct v4l2_subdev *sd;
2808
2809         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2810         memset(&ctrl, 0, sizeof(ctrl));
2811         ctrl.id = id;
2812         ctrl.value = val;
2813
2814         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev)
2815                 v4l2_s_ctrl(NULL, sd->ctrl_handler, &ctrl);
2816 }
2817
2818 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2819         if ((hdw)->lab##_dirty || (hdw)->force_dirty) {         \
2820                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2821         }
2822
2823 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw)
2824 {
2825         v4l2_std_id std;
2826         std = (v4l2_std_id)hdw->std_mask_avail;
2827         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2828                              video, querystd, &std);
2829         return std;
2830 }
2831
2832 /* Execute whatever commands are required to update the state of all the
2833    sub-devices so that they match our current control values. */
2834 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2835 {
2836         struct v4l2_subdev *sd;
2837         unsigned int id;
2838         pvr2_subdev_update_func fp;
2839
2840         pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2841
2842         if (hdw->tuner_updated || hdw->force_dirty) {
2843                 struct tuner_setup setup;
2844                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2845                            hdw->tuner_type);
2846                 if (((int)(hdw->tuner_type)) >= 0) {
2847                         memset(&setup, 0, sizeof(setup));
2848                         setup.addr = ADDR_UNSET;
2849                         setup.type = hdw->tuner_type;
2850                         setup.mode_mask = T_RADIO | T_ANALOG_TV;
2851                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2852                                              tuner, s_type_addr, &setup);
2853                 }
2854         }
2855
2856         if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
2857                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2858                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2859                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2860                                              tuner, s_radio);
2861                 } else {
2862                         v4l2_std_id vs;
2863                         vs = hdw->std_mask_cur;
2864                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2865                                              video, s_std, vs);
2866                         pvr2_hdw_cx25840_vbi_hack(hdw);
2867                 }
2868                 hdw->tuner_signal_stale = !0;
2869                 hdw->cropcap_stale = !0;
2870         }
2871
2872         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2873         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2874         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2875         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2876         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2877         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2878         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2879         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2880         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2881
2882         if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2883                 struct v4l2_tuner vt;
2884                 memset(&vt, 0, sizeof(vt));
2885                 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
2886                         V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2887                 vt.audmode = hdw->audiomode_val;
2888                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2889         }
2890
2891         if (hdw->freqDirty || hdw->force_dirty) {
2892                 unsigned long fv;
2893                 struct v4l2_frequency freq;
2894                 fv = pvr2_hdw_get_cur_freq(hdw);
2895                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2896                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2897                 memset(&freq, 0, sizeof(freq));
2898                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2899                         /* ((fv * 1000) / 62500) */
2900                         freq.frequency = (fv * 2) / 125;
2901                 } else {
2902                         freq.frequency = fv / 62500;
2903                 }
2904                 /* tuner-core currently doesn't seem to care about this, but
2905                    let's set it anyway for completeness. */
2906                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2907                         freq.type = V4L2_TUNER_RADIO;
2908                 } else {
2909                         freq.type = V4L2_TUNER_ANALOG_TV;
2910                 }
2911                 freq.tuner = 0;
2912                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2913                                      s_frequency, &freq);
2914         }
2915
2916         if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2917                 struct v4l2_subdev_format format = {
2918                         .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2919                 };
2920
2921                 format.format.width = hdw->res_hor_val;
2922                 format.format.height = hdw->res_ver_val;
2923                 format.format.code = MEDIA_BUS_FMT_FIXED;
2924                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2925                            format.format.width, format.format.height);
2926                 v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt,
2927                                      NULL, &format);
2928         }
2929
2930         if (hdw->srate_dirty || hdw->force_dirty) {
2931                 u32 val;
2932                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
2933                            hdw->srate_val);
2934                 switch (hdw->srate_val) {
2935                 default:
2936                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
2937                         val = 48000;
2938                         break;
2939                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
2940                         val = 44100;
2941                         break;
2942                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
2943                         val = 32000;
2944                         break;
2945                 }
2946                 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2947                                      audio, s_clock_freq, val);
2948         }
2949
2950         /* Unable to set crop parameters; there is apparently no equivalent
2951            for VIDIOC_S_CROP */
2952
2953         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
2954                 id = sd->grp_id;
2955                 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
2956                 fp = pvr2_module_update_functions[id];
2957                 if (!fp) continue;
2958                 (*fp)(hdw, sd);
2959         }
2960
2961         if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2962                 pvr2_hdw_status_poll(hdw);
2963         }
2964 }
2965
2966
2967 /* Figure out if we need to commit control changes.  If so, mark internal
2968    state flags to indicate this fact and return true.  Otherwise do nothing
2969    else and return false. */
2970 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2971 {
2972         unsigned int idx;
2973         struct pvr2_ctrl *cptr;
2974         int value;
2975         int commit_flag = hdw->force_dirty;
2976         char buf[100];
2977         unsigned int bcnt,ccnt;
2978
2979         for (idx = 0; idx < hdw->control_cnt; idx++) {
2980                 cptr = hdw->controls + idx;
2981                 if (!cptr->info->is_dirty) continue;
2982                 if (!cptr->info->is_dirty(cptr)) continue;
2983                 commit_flag = !0;
2984
2985                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2986                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2987                                  cptr->info->name);
2988                 value = 0;
2989                 cptr->info->get_value(cptr,&value);
2990                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2991                                                 buf+bcnt,
2992                                                 sizeof(buf)-bcnt,&ccnt);
2993                 bcnt += ccnt;
2994                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2995                                   get_ctrl_typename(cptr->info->type));
2996                 pvr2_trace(PVR2_TRACE_CTL,
2997                            "/*--TRACE_COMMIT--*/ %.*s",
2998                            bcnt,buf);
2999         }
3000
3001         if (!commit_flag) {
3002                 /* Nothing has changed */
3003                 return 0;
3004         }
3005
3006         hdw->state_pipeline_config = 0;
3007         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3008         pvr2_hdw_state_sched(hdw);
3009
3010         return !0;
3011 }
3012
3013
3014 /* Perform all operations needed to commit all control changes.  This must
3015    be performed in synchronization with the pipeline state and is thus
3016    expected to be called as part of the driver's worker thread.  Return
3017    true if commit successful, otherwise return false to indicate that
3018    commit isn't possible at this time. */
3019 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3020 {
3021         unsigned int idx;
3022         struct pvr2_ctrl *cptr;
3023         int disruptive_change;
3024
3025         if (hdw->input_dirty && hdw->state_pathway_ok &&
3026             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3027               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3028              hdw->pathway_state)) {
3029                 /* Change of mode being asked for... */
3030                 hdw->state_pathway_ok = 0;
3031                 trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3032         }
3033         if (!hdw->state_pathway_ok) {
3034                 /* Can't commit anything until pathway is ok. */
3035                 return 0;
3036         }
3037
3038         /* Handle some required side effects when the video standard is
3039            changed.... */
3040         if (hdw->std_dirty) {
3041                 int nvres;
3042                 int gop_size;
3043                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3044                         nvres = 480;
3045                         gop_size = 15;
3046                 } else {
3047                         nvres = 576;
3048                         gop_size = 12;
3049                 }
3050                 /* Rewrite the vertical resolution to be appropriate to the
3051                    video standard that has been selected. */
3052                 if (nvres != hdw->res_ver_val) {
3053                         hdw->res_ver_val = nvres;
3054                         hdw->res_ver_dirty = !0;
3055                 }
3056                 /* Rewrite the GOP size to be appropriate to the video
3057                    standard that has been selected. */
3058                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3059                         struct v4l2_ext_controls cs;
3060                         struct v4l2_ext_control c1;
3061                         memset(&cs, 0, sizeof(cs));
3062                         memset(&c1, 0, sizeof(c1));
3063                         cs.controls = &c1;
3064                         cs.count = 1;
3065                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3066                         c1.value = gop_size;
3067                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3068                                           VIDIOC_S_EXT_CTRLS);
3069                 }
3070         }
3071
3072         /* The broadcast decoder can only scale down, so if
3073          * res_*_dirty && crop window < output format ==> enlarge crop.
3074          *
3075          * The mpeg encoder receives fields of res_hor_val dots and
3076          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3077          */
3078         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3079                 hdw->cropw_val = hdw->res_hor_val;
3080                 hdw->cropw_dirty = !0;
3081         } else if (hdw->cropw_dirty) {
3082                 hdw->res_hor_dirty = !0;           /* must rescale */
3083                 hdw->res_hor_val = min(720, hdw->cropw_val);
3084         }
3085         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3086                 hdw->croph_val = hdw->res_ver_val;
3087                 hdw->croph_dirty = !0;
3088         } else if (hdw->croph_dirty) {
3089                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3090                 hdw->res_ver_dirty = !0;
3091                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3092         }
3093
3094         /* If any of the below has changed, then we can't do the update
3095            while the pipeline is running.  Pipeline must be paused first
3096            and decoder -> encoder connection be made quiescent before we
3097            can proceed. */
3098         disruptive_change =
3099                 (hdw->std_dirty ||
3100                  hdw->enc_unsafe_stale ||
3101                  hdw->srate_dirty ||
3102                  hdw->res_ver_dirty ||
3103                  hdw->res_hor_dirty ||
3104                  hdw->cropw_dirty ||
3105                  hdw->croph_dirty ||
3106                  hdw->input_dirty ||
3107                  (hdw->active_stream_type != hdw->desired_stream_type));
3108         if (disruptive_change && !hdw->state_pipeline_idle) {
3109                 /* Pipeline is not idle; we can't proceed.  Arrange to
3110                    cause pipeline to stop so that we can try this again
3111                    later.... */
3112                 hdw->state_pipeline_pause = !0;
3113                 return 0;
3114         }
3115
3116         if (hdw->srate_dirty) {
3117                 /* Write new sample rate into control structure since
3118                  * the master copy is stale.  We must track srate
3119                  * separate from the mpeg control structure because
3120                  * other logic also uses this value. */
3121                 struct v4l2_ext_controls cs;
3122                 struct v4l2_ext_control c1;
3123                 memset(&cs,0,sizeof(cs));
3124                 memset(&c1,0,sizeof(c1));
3125                 cs.controls = &c1;
3126                 cs.count = 1;
3127                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3128                 c1.value = hdw->srate_val;
3129                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3130         }
3131
3132         if (hdw->active_stream_type != hdw->desired_stream_type) {
3133                 /* Handle any side effects of stream config here */
3134                 hdw->active_stream_type = hdw->desired_stream_type;
3135         }
3136
3137         if (hdw->hdw_desc->signal_routing_scheme ==
3138             PVR2_ROUTING_SCHEME_GOTVIEW) {
3139                 u32 b;
3140                 /* Handle GOTVIEW audio switching */
3141                 pvr2_hdw_gpio_get_out(hdw,&b);
3142                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3143                         /* Set GPIO 11 */
3144                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3145                 } else {
3146                         /* Clear GPIO 11 */
3147                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3148                 }
3149         }
3150
3151         /* Check and update state for all sub-devices. */
3152         pvr2_subdev_update(hdw);
3153
3154         hdw->tuner_updated = 0;
3155         hdw->force_dirty = 0;
3156         for (idx = 0; idx < hdw->control_cnt; idx++) {
3157                 cptr = hdw->controls + idx;
3158                 if (!cptr->info->clear_dirty) continue;
3159                 cptr->info->clear_dirty(cptr);
3160         }
3161
3162         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3163             hdw->state_encoder_run) {
3164                 /* If encoder isn't running or it can't be touched, then
3165                    this will get worked out later when we start the
3166                    encoder. */
3167                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3168         }
3169
3170         hdw->state_pipeline_config = !0;
3171         /* Hardware state may have changed in a way to cause the cropping
3172            capabilities to have changed.  So mark it stale, which will
3173            cause a later re-fetch. */
3174         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3175         return !0;
3176 }
3177
3178
3179 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3180 {
3181         int fl;
3182         LOCK_TAKE(hdw->big_lock);
3183         fl = pvr2_hdw_commit_setup(hdw);
3184         LOCK_GIVE(hdw->big_lock);
3185         if (!fl) return 0;
3186         return pvr2_hdw_wait(hdw,0);
3187 }
3188
3189
3190 static void pvr2_hdw_worker_poll(struct work_struct *work)
3191 {
3192         int fl = 0;
3193         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3194         LOCK_TAKE(hdw->big_lock); do {
3195                 fl = pvr2_hdw_state_eval(hdw);
3196         } while (0); LOCK_GIVE(hdw->big_lock);
3197         if (fl && hdw->state_func) {
3198                 hdw->state_func(hdw->state_data);
3199         }
3200 }
3201
3202
3203 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3204 {
3205         return wait_event_interruptible(
3206                 hdw->state_wait_data,
3207                 (hdw->state_stale == 0) &&
3208                 (!state || (hdw->master_state != state)));
3209 }
3210
3211
3212 /* Return name for this driver instance */
3213 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3214 {
3215         return hdw->name;
3216 }
3217
3218
3219 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3220 {
3221         return hdw->hdw_desc->description;
3222 }
3223
3224
3225 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3226 {
3227         return hdw->hdw_desc->shortname;
3228 }
3229
3230
3231 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3232 {
3233         int result;
3234         LOCK_TAKE(hdw->ctl_lock); do {
3235                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3236                 result = pvr2_send_request(hdw,
3237                                            hdw->cmd_buffer,1,
3238                                            hdw->cmd_buffer,1);
3239                 if (result < 0) break;
3240                 result = (hdw->cmd_buffer[0] != 0);
3241         } while(0); LOCK_GIVE(hdw->ctl_lock);
3242         return result;
3243 }
3244
3245
3246 /* Execute poll of tuner status */
3247 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3248 {
3249         LOCK_TAKE(hdw->big_lock); do {
3250                 pvr2_hdw_status_poll(hdw);
3251         } while (0); LOCK_GIVE(hdw->big_lock);
3252 }
3253
3254
3255 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3256 {
3257         if (!hdw->cropcap_stale) {
3258                 return 0;
3259         }
3260         pvr2_hdw_status_poll(hdw);
3261         if (hdw->cropcap_stale) {
3262                 return -EIO;
3263         }
3264         return 0;
3265 }
3266
3267
3268 /* Return information about cropping capabilities */
3269 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3270 {
3271         int stat = 0;
3272         LOCK_TAKE(hdw->big_lock);
3273         stat = pvr2_hdw_check_cropcap(hdw);
3274         if (!stat) {
3275                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3276         }
3277         LOCK_GIVE(hdw->big_lock);
3278         return stat;
3279 }
3280
3281
3282 /* Return information about the tuner */
3283 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3284 {
3285         LOCK_TAKE(hdw->big_lock); do {
3286                 if (hdw->tuner_signal_stale) {
3287                         pvr2_hdw_status_poll(hdw);
3288                 }
3289                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3290         } while (0); LOCK_GIVE(hdw->big_lock);
3291         return 0;
3292 }
3293
3294
3295 /* Get handle to video output stream */
3296 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3297 {
3298         return hp->vid_stream;
3299 }
3300
3301
3302 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3303 {
3304         int nr = pvr2_hdw_get_unit_number(hdw);
3305         LOCK_TAKE(hdw->big_lock);
3306         do {
3307                 pr_info("pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3308                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3309                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3310                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3311                 pvr2_hdw_state_log_state(hdw);
3312                 pr_info("pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3313         } while (0);
3314         LOCK_GIVE(hdw->big_lock);
3315 }
3316
3317
3318 /* Grab EEPROM contents, needed for direct method. */
3319 #define EEPROM_SIZE 8192
3320 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3321 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3322 {
3323         struct i2c_msg msg[2];
3324         u8 *eeprom;
3325         u8 iadd[2];
3326         u8 addr;
3327         u16 eepromSize;
3328         unsigned int offs;
3329         int ret;
3330         int mode16 = 0;
3331         unsigned pcnt,tcnt;
3332         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3333         if (!eeprom) {
3334                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3335                            "Failed to allocate memory required to read eeprom");
3336                 return NULL;
3337         }
3338
3339         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3340                      hdw->eeprom_addr);
3341         addr = hdw->eeprom_addr;
3342         /* Seems that if the high bit is set, then the *real* eeprom
3343            address is shifted right now bit position (noticed this in
3344            newer PVR USB2 hardware) */
3345         if (addr & 0x80) addr >>= 1;
3346
3347         /* FX2 documentation states that a 16bit-addressed eeprom is
3348            expected if the I2C address is an odd number (yeah, this is
3349            strange but it's what they do) */
3350         mode16 = (addr & 1);
3351         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3352         trace_eeprom("Examining %d byte eeprom at location 0x%x using %d bit addressing",
3353                      eepromSize, addr,
3354                      mode16 ? 16 : 8);
3355
3356         msg[0].addr = addr;
3357         msg[0].flags = 0;
3358         msg[0].len = mode16 ? 2 : 1;
3359         msg[0].buf = iadd;
3360         msg[1].addr = addr;
3361         msg[1].flags = I2C_M_RD;
3362
3363         /* We have to do the actual eeprom data fetch ourselves, because
3364            (1) we're only fetching part of the eeprom, and (2) if we were
3365            getting the whole thing our I2C driver can't grab it in one
3366            pass - which is what tveeprom is otherwise going to attempt */
3367         memset(eeprom,0,EEPROM_SIZE);
3368         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3369                 pcnt = 16;
3370                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3371                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3372                 if (mode16) {
3373                         iadd[0] = offs >> 8;
3374                         iadd[1] = offs;
3375                 } else {
3376                         iadd[0] = offs;
3377                 }
3378                 msg[1].len = pcnt;
3379                 msg[1].buf = eeprom+tcnt;
3380                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3381                                         msg,ARRAY_SIZE(msg))) != 2) {
3382                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3383                                    "eeprom fetch set offs err=%d",ret);
3384                         kfree(eeprom);
3385                         return NULL;
3386                 }
3387         }
3388         return eeprom;
3389 }
3390
3391
3392 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3393                                 int mode,
3394                                 int enable_flag)
3395 {
3396         int ret;
3397         u16 address;
3398         unsigned int pipe;
3399         LOCK_TAKE(hdw->big_lock); do {
3400                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3401
3402                 if (!enable_flag) {
3403                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3404                                    "Cleaning up after CPU firmware fetch");
3405                         kfree(hdw->fw_buffer);
3406                         hdw->fw_buffer = NULL;
3407                         hdw->fw_size = 0;
3408                         if (hdw->fw_cpu_flag) {
3409                                 /* Now release the CPU.  It will disconnect
3410                                    and reconnect later. */
3411                                 pvr2_hdw_cpureset_assert(hdw,0);
3412                         }
3413                         break;
3414                 }
3415
3416                 hdw->fw_cpu_flag = (mode != 2);
3417                 if (hdw->fw_cpu_flag) {
3418                         hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3419                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3420                                    "Preparing to suck out CPU firmware (size=%u)",
3421                                    hdw->fw_size);
3422                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3423                         if (!hdw->fw_buffer) {
3424                                 hdw->fw_size = 0;
3425                                 break;
3426                         }
3427
3428                         /* We have to hold the CPU during firmware upload. */
3429                         pvr2_hdw_cpureset_assert(hdw,1);
3430
3431                         /* download the firmware from address 0000-1fff in 2048
3432                            (=0x800) bytes chunk. */
3433
3434                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3435                                    "Grabbing CPU firmware");
3436                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3437                         for(address = 0; address < hdw->fw_size;
3438                             address += 0x800) {
3439                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3440                                                       0xa0,0xc0,
3441                                                       address,0,
3442                                                       hdw->fw_buffer+address,
3443                                                       0x800,HZ);
3444                                 if (ret < 0) break;
3445                         }
3446
3447                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3448                                    "Done grabbing CPU firmware");
3449                 } else {
3450                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3451                                    "Sucking down EEPROM contents");
3452                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3453                         if (!hdw->fw_buffer) {
3454                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3455                                            "EEPROM content suck failed.");
3456                                 break;
3457                         }
3458                         hdw->fw_size = EEPROM_SIZE;
3459                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3460                                    "Done sucking down EEPROM contents");
3461                 }
3462
3463         } while (0); LOCK_GIVE(hdw->big_lock);
3464 }
3465
3466
3467 /* Return true if we're in a mode for retrieval CPU firmware */
3468 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3469 {
3470         return hdw->fw_buffer != NULL;
3471 }
3472
3473
3474 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3475                        char *buf,unsigned int cnt)
3476 {
3477         int ret = -EINVAL;
3478         LOCK_TAKE(hdw->big_lock); do {
3479                 if (!buf) break;
3480                 if (!cnt) break;
3481
3482                 if (!hdw->fw_buffer) {
3483                         ret = -EIO;
3484                         break;
3485                 }
3486
3487                 if (offs >= hdw->fw_size) {
3488                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3489                                    "Read firmware data offs=%d EOF",
3490                                    offs);
3491                         ret = 0;
3492                         break;
3493                 }
3494
3495                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3496
3497                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3498
3499                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3500                            "Read firmware data offs=%d cnt=%d",
3501                            offs,cnt);
3502                 ret = cnt;
3503         } while (0); LOCK_GIVE(hdw->big_lock);
3504
3505         return ret;
3506 }
3507
3508
3509 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3510                                   enum pvr2_v4l_type index)
3511 {
3512         switch (index) {
3513         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3514         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3515         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3516         default: return -1;
3517         }
3518 }
3519
3520
3521 /* Store a v4l minor device number */
3522 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3523                                      enum pvr2_v4l_type index,int v)
3524 {
3525         switch (index) {
3526         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break;
3527         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break;
3528         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break;
3529         default: break;
3530         }
3531 }
3532
3533
3534 static void pvr2_ctl_write_complete(struct urb *urb)
3535 {
3536         struct pvr2_hdw *hdw = urb->context;
3537         hdw->ctl_write_pend_flag = 0;
3538         if (hdw->ctl_read_pend_flag) return;
3539         complete(&hdw->ctl_done);
3540 }
3541
3542
3543 static void pvr2_ctl_read_complete(struct urb *urb)
3544 {
3545         struct pvr2_hdw *hdw = urb->context;
3546         hdw->ctl_read_pend_flag = 0;
3547         if (hdw->ctl_write_pend_flag) return;
3548         complete(&hdw->ctl_done);
3549 }
3550
3551 struct hdw_timer {
3552         struct timer_list timer;
3553         struct pvr2_hdw *hdw;
3554 };
3555
3556 static void pvr2_ctl_timeout(struct timer_list *t)
3557 {
3558         struct hdw_timer *timer = from_timer(timer, t, timer);
3559         struct pvr2_hdw *hdw = timer->hdw;
3560
3561         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3562                 hdw->ctl_timeout_flag = !0;
3563                 if (hdw->ctl_write_pend_flag)
3564                         usb_unlink_urb(hdw->ctl_write_urb);
3565                 if (hdw->ctl_read_pend_flag)
3566                         usb_unlink_urb(hdw->ctl_read_urb);
3567         }
3568 }
3569
3570
3571 /* Issue a command and get a response from the device.  This extended
3572    version includes a probe flag (which if set means that device errors
3573    should not be logged or treated as fatal) and a timeout in jiffies.
3574    This can be used to non-lethally probe the health of endpoint 1. */
3575 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3576                                 unsigned int timeout,int probe_fl,
3577                                 void *write_data,unsigned int write_len,
3578                                 void *read_data,unsigned int read_len)
3579 {
3580         unsigned int idx;
3581         int status = 0;
3582         struct hdw_timer timer = {
3583                 .hdw = hdw,
3584         };
3585
3586         if (!hdw->ctl_lock_held) {
3587                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3588                            "Attempted to execute control transfer without lock!!");
3589                 return -EDEADLK;
3590         }
3591         if (!hdw->flag_ok && !probe_fl) {
3592                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3593                            "Attempted to execute control transfer when device not ok");
3594                 return -EIO;
3595         }
3596         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3597                 if (!probe_fl) {
3598                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3599                                    "Attempted to execute control transfer when USB is disconnected");
3600                 }
3601                 return -ENOTTY;
3602         }
3603
3604         /* Ensure that we have sane parameters */
3605         if (!write_data) write_len = 0;
3606         if (!read_data) read_len = 0;
3607         if (write_len > PVR2_CTL_BUFFSIZE) {
3608                 pvr2_trace(
3609                         PVR2_TRACE_ERROR_LEGS,
3610                         "Attempted to execute %d byte control-write transfer (limit=%d)",
3611                         write_len,PVR2_CTL_BUFFSIZE);
3612                 return -EINVAL;
3613         }
3614         if (read_len > PVR2_CTL_BUFFSIZE) {
3615                 pvr2_trace(
3616                         PVR2_TRACE_ERROR_LEGS,
3617                         "Attempted to execute %d byte control-read transfer (limit=%d)",
3618                         write_len,PVR2_CTL_BUFFSIZE);
3619                 return -EINVAL;
3620         }
3621         if ((!write_len) && (!read_len)) {
3622                 pvr2_trace(
3623                         PVR2_TRACE_ERROR_LEGS,
3624                         "Attempted to execute null control transfer?");
3625                 return -EINVAL;
3626         }
3627
3628
3629         hdw->cmd_debug_state = 1;
3630         if (write_len && write_data)
3631                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3632         else
3633                 hdw->cmd_debug_code = 0;
3634         hdw->cmd_debug_write_len = write_len;
3635         hdw->cmd_debug_read_len = read_len;
3636
3637         /* Initialize common stuff */
3638         init_completion(&hdw->ctl_done);
3639         hdw->ctl_timeout_flag = 0;
3640         hdw->ctl_write_pend_flag = 0;
3641         hdw->ctl_read_pend_flag = 0;
3642         timer_setup_on_stack(&timer.timer, pvr2_ctl_timeout, 0);
3643         timer.timer.expires = jiffies + timeout;
3644
3645         if (write_len && write_data) {
3646                 hdw->cmd_debug_state = 2;
3647                 /* Transfer write data to internal buffer */
3648                 for (idx = 0; idx < write_len; idx++) {
3649                         hdw->ctl_write_buffer[idx] =
3650                                 ((unsigned char *)write_data)[idx];
3651                 }
3652                 /* Initiate a write request */
3653                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3654                                   hdw->usb_dev,
3655                                   usb_sndbulkpipe(hdw->usb_dev,
3656                                                   PVR2_CTL_WRITE_ENDPOINT),
3657                                   hdw->ctl_write_buffer,
3658                                   write_len,
3659                                   pvr2_ctl_write_complete,
3660                                   hdw);
3661                 hdw->ctl_write_urb->actual_length = 0;
3662                 hdw->ctl_write_pend_flag = !0;
3663                 if (usb_urb_ep_type_check(hdw->ctl_write_urb)) {
3664                         pvr2_trace(
3665                                 PVR2_TRACE_ERROR_LEGS,
3666                                 "Invalid write control endpoint");
3667                         return -EINVAL;
3668                 }
3669                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3670                 if (status < 0) {
3671                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3672                                    "Failed to submit write-control URB status=%d",
3673 status);
3674                         hdw->ctl_write_pend_flag = 0;
3675                         goto done;
3676                 }
3677         }
3678
3679         if (read_len) {
3680                 hdw->cmd_debug_state = 3;
3681                 memset(hdw->ctl_read_buffer,0x43,read_len);
3682                 /* Initiate a read request */
3683                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3684                                   hdw->usb_dev,
3685                                   usb_rcvbulkpipe(hdw->usb_dev,
3686                                                   PVR2_CTL_READ_ENDPOINT),
3687                                   hdw->ctl_read_buffer,
3688                                   read_len,
3689                                   pvr2_ctl_read_complete,
3690                                   hdw);
3691                 hdw->ctl_read_urb->actual_length = 0;
3692                 hdw->ctl_read_pend_flag = !0;
3693                 if (usb_urb_ep_type_check(hdw->ctl_read_urb)) {
3694                         pvr2_trace(
3695                                 PVR2_TRACE_ERROR_LEGS,
3696                                 "Invalid read control endpoint");
3697                         return -EINVAL;
3698                 }
3699                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3700                 if (status < 0) {
3701                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3702                                    "Failed to submit read-control URB status=%d",
3703 status);
3704                         hdw->ctl_read_pend_flag = 0;
3705                         goto done;
3706                 }
3707         }
3708
3709         /* Start timer */
3710         add_timer(&timer.timer);
3711
3712         /* Now wait for all I/O to complete */
3713         hdw->cmd_debug_state = 4;
3714         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3715                 wait_for_completion(&hdw->ctl_done);
3716         }
3717         hdw->cmd_debug_state = 5;
3718
3719         /* Stop timer */
3720         del_timer_sync(&timer.timer);
3721
3722         hdw->cmd_debug_state = 6;
3723         status = 0;
3724
3725         if (hdw->ctl_timeout_flag) {
3726                 status = -ETIMEDOUT;
3727                 if (!probe_fl) {
3728                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3729                                    "Timed out control-write");
3730                 }
3731                 goto done;
3732         }
3733
3734         if (write_len) {
3735                 /* Validate results of write request */
3736                 if ((hdw->ctl_write_urb->status != 0) &&
3737                     (hdw->ctl_write_urb->status != -ENOENT) &&
3738                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3739                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3740                         /* USB subsystem is reporting some kind of failure
3741                            on the write */
3742                         status = hdw->ctl_write_urb->status;
3743                         if (!probe_fl) {
3744                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3745                                            "control-write URB failure, status=%d",
3746                                            status);
3747                         }
3748                         goto done;
3749                 }
3750                 if (hdw->ctl_write_urb->actual_length < write_len) {
3751                         /* Failed to write enough data */
3752                         status = -EIO;
3753                         if (!probe_fl) {
3754                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3755                                            "control-write URB short, expected=%d got=%d",
3756                                            write_len,
3757                                            hdw->ctl_write_urb->actual_length);
3758                         }
3759                         goto done;
3760                 }
3761         }
3762         if (read_len && read_data) {
3763                 /* Validate results of read request */
3764                 if ((hdw->ctl_read_urb->status != 0) &&
3765                     (hdw->ctl_read_urb->status != -ENOENT) &&
3766                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3767                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3768                         /* USB subsystem is reporting some kind of failure
3769                            on the read */
3770                         status = hdw->ctl_read_urb->status;
3771                         if (!probe_fl) {
3772                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3773                                            "control-read URB failure, status=%d",
3774                                            status);
3775                         }
3776                         goto done;
3777                 }
3778                 if (hdw->ctl_read_urb->actual_length < read_len) {
3779                         /* Failed to read enough data */
3780                         status = -EIO;
3781                         if (!probe_fl) {
3782                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3783                                            "control-read URB short, expected=%d got=%d",
3784                                            read_len,
3785                                            hdw->ctl_read_urb->actual_length);
3786                         }
3787                         goto done;
3788                 }
3789                 /* Transfer retrieved data out from internal buffer */
3790                 for (idx = 0; idx < read_len; idx++) {
3791                         ((unsigned char *)read_data)[idx] =
3792                                 hdw->ctl_read_buffer[idx];
3793                 }
3794         }
3795
3796  done:
3797
3798         hdw->cmd_debug_state = 0;
3799         if ((status < 0) && (!probe_fl)) {
3800                 pvr2_hdw_render_useless(hdw);
3801         }
3802         destroy_timer_on_stack(&timer.timer);
3803
3804         return status;
3805 }
3806
3807
3808 int pvr2_send_request(struct pvr2_hdw *hdw,
3809                       void *write_data,unsigned int write_len,
3810                       void *read_data,unsigned int read_len)
3811 {
3812         return pvr2_send_request_ex(hdw,HZ*4,0,
3813                                     write_data,write_len,
3814                                     read_data,read_len);
3815 }
3816
3817
3818 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3819 {
3820         int ret;
3821         unsigned int cnt = 1;
3822         unsigned int args = 0;
3823         LOCK_TAKE(hdw->ctl_lock);
3824         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3825         args = (cmdcode >> 8) & 0xffu;
3826         args = (args > 2) ? 2 : args;
3827         if (args) {
3828                 cnt += args;
3829                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3830                 if (args > 1) {
3831                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3832                 }
3833         }
3834         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3835                 unsigned int idx;
3836                 unsigned int ccnt,bcnt;
3837                 char tbuf[50];
3838                 cmdcode &= 0xffu;
3839                 bcnt = 0;
3840                 ccnt = scnprintf(tbuf+bcnt,
3841                                  sizeof(tbuf)-bcnt,
3842                                  "Sending FX2 command 0x%x",cmdcode);
3843                 bcnt += ccnt;
3844                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3845                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3846                                 ccnt = scnprintf(tbuf+bcnt,
3847                                                  sizeof(tbuf)-bcnt,
3848                                                  " \"%s\"",
3849                                                  pvr2_fx2cmd_desc[idx].desc);
3850                                 bcnt += ccnt;
3851                                 break;
3852                         }
3853                 }
3854                 if (args) {
3855                         ccnt = scnprintf(tbuf+bcnt,
3856                                          sizeof(tbuf)-bcnt,
3857                                          " (%u",hdw->cmd_buffer[1]);
3858                         bcnt += ccnt;
3859                         if (args > 1) {
3860                                 ccnt = scnprintf(tbuf+bcnt,
3861                                                  sizeof(tbuf)-bcnt,
3862                                                  ",%u",hdw->cmd_buffer[2]);
3863                                 bcnt += ccnt;
3864                         }
3865                         ccnt = scnprintf(tbuf+bcnt,
3866                                          sizeof(tbuf)-bcnt,
3867                                          ")");
3868                         bcnt += ccnt;
3869                 }
3870                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3871         }
3872         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3873         LOCK_GIVE(hdw->ctl_lock);
3874         return ret;
3875 }
3876
3877
3878 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3879 {
3880         int ret;
3881
3882         LOCK_TAKE(hdw->ctl_lock);
3883
3884         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3885         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3886         hdw->cmd_buffer[5] = 0;
3887         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3888         hdw->cmd_buffer[7] = reg & 0xff;
3889
3890
3891         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3892
3893         LOCK_GIVE(hdw->ctl_lock);
3894
3895         return ret;
3896 }
3897
3898
3899 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3900 {
3901         int ret = 0;
3902
3903         LOCK_TAKE(hdw->ctl_lock);
3904
3905         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3906         hdw->cmd_buffer[1] = 0;
3907         hdw->cmd_buffer[2] = 0;
3908         hdw->cmd_buffer[3] = 0;
3909         hdw->cmd_buffer[4] = 0;
3910         hdw->cmd_buffer[5] = 0;
3911         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3912         hdw->cmd_buffer[7] = reg & 0xff;
3913
3914         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3915         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3916
3917         LOCK_GIVE(hdw->ctl_lock);
3918
3919         return ret;
3920 }
3921
3922
3923 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3924 {
3925         if (!hdw->flag_ok) return;
3926         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3927                    "Device being rendered inoperable");
3928         if (hdw->vid_stream) {
3929                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3930         }
3931         hdw->flag_ok = 0;
3932         trace_stbit("flag_ok",hdw->flag_ok);
3933         pvr2_hdw_state_sched(hdw);
3934 }
3935
3936
3937 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3938 {
3939         int ret;
3940         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3941         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3942         if (ret == 0) {
3943                 ret = usb_reset_device(hdw->usb_dev);
3944                 usb_unlock_device(hdw->usb_dev);
3945         } else {
3946                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3947                            "Failed to lock USB device ret=%d",ret);
3948         }
3949         if (init_pause_msec) {
3950                 pvr2_trace(PVR2_TRACE_INFO,
3951                            "Waiting %u msec for hardware to settle",
3952                            init_pause_msec);
3953                 msleep(init_pause_msec);
3954         }
3955
3956 }
3957
3958
3959 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3960 {
3961         char *da;
3962         unsigned int pipe;
3963         int ret;
3964
3965         if (!hdw->usb_dev) return;
3966
3967         da = kmalloc(16, GFP_KERNEL);
3968
3969         if (da == NULL) {
3970                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3971                            "Unable to allocate memory to control CPU reset");
3972                 return;
3973         }
3974
3975         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3976
3977         da[0] = val ? 0x01 : 0x00;
3978
3979         /* Write the CPUCS register on the 8051.  The lsb of the register
3980            is the reset bit; a 1 asserts reset while a 0 clears it. */
3981         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3982         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3983         if (ret < 0) {
3984                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3985                            "cpureset_assert(%d) error=%d",val,ret);
3986                 pvr2_hdw_render_useless(hdw);
3987         }
3988
3989         kfree(da);
3990 }
3991
3992
3993 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3994 {
3995         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
3996 }
3997
3998
3999 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4000 {
4001         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4002 }
4003
4004
4005
4006 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4007 {
4008         pvr2_trace(PVR2_TRACE_INIT,
4009                    "Requesting decoder reset");
4010         if (hdw->decoder_client_id) {
4011                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4012                                      core, reset, 0);
4013                 pvr2_hdw_cx25840_vbi_hack(hdw);
4014                 return 0;
4015         }
4016         pvr2_trace(PVR2_TRACE_INIT,
4017                    "Unable to reset decoder: nothing attached");
4018         return -ENOTTY;
4019 }
4020
4021
4022 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4023 {
4024         hdw->flag_ok = !0;
4025
4026         /* Use this for Hauppauge 160xxx only */
4027         if (le16_to_cpu(hdw->usb_dev->descriptor.idVendor) == 0x2040 &&
4028             (le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7502 ||
4029              le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7510)) {
4030                 pr_debug("%s(): resetting demod on Hauppauge 160xxx platform skipped\n",
4031                          __func__);
4032                 /* Can't reset 160xxx or it will trash Demod tristate */
4033                 return pvr2_issue_simple_cmd(hdw,
4034                                              FX2CMD_HCW_MAKO_SLEEP_PIN |
4035                                              (1 << 8) |
4036                                              ((onoff ? 1 : 0) << 16));
4037         }
4038
4039         return pvr2_issue_simple_cmd(hdw,
4040                                      FX2CMD_HCW_DEMOD_RESETIN |
4041                                      (1 << 8) |
4042                                      ((onoff ? 1 : 0) << 16));
4043 }
4044
4045
4046 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4047 {
4048         hdw->flag_ok = !0;
4049         return pvr2_issue_simple_cmd(hdw,(onoff ?
4050                                           FX2CMD_ONAIR_DTV_POWER_ON :
4051                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4052 }
4053
4054
4055 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4056                                                 int onoff)
4057 {
4058         return pvr2_issue_simple_cmd(hdw,(onoff ?
4059                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4060                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4061 }
4062
4063
4064 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4065 {
4066         int cmode;
4067         /* Compare digital/analog desired setting with current setting.  If
4068            they don't match, fix it... */
4069         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4070         if (cmode == hdw->pathway_state) {
4071                 /* They match; nothing to do */
4072                 return;
4073         }
4074
4075         switch (hdw->hdw_desc->digital_control_scheme) {
4076         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4077                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4078                 if (cmode == PVR2_PATHWAY_ANALOG) {
4079                         /* If moving to analog mode, also force the decoder
4080                            to reset.  If no decoder is attached, then it's
4081                            ok to ignore this because if/when the decoder
4082                            attaches, it will reset itself at that time. */
4083                         pvr2_hdw_cmd_decoder_reset(hdw);
4084                 }
4085                 break;
4086         case PVR2_DIGITAL_SCHEME_ONAIR:
4087                 /* Supposedly we should always have the power on whether in
4088                    digital or analog mode.  But for now do what appears to
4089                    work... */
4090                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4091                 break;
4092         default: break;
4093         }
4094
4095         pvr2_hdw_untrip_unlocked(hdw);
4096         hdw->pathway_state = cmode;
4097 }
4098
4099
4100 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4101 {
4102         /* change some GPIO data
4103          *
4104          * note: bit d7 of dir appears to control the LED,
4105          * so we shut it off here.
4106          *
4107          */
4108         if (onoff) {
4109                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4110         } else {
4111                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4112         }
4113         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4114 }
4115
4116
4117 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4118
4119 static led_method_func led_methods[] = {
4120         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4121 };
4122
4123
4124 /* Toggle LED */
4125 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4126 {
4127         unsigned int scheme_id;
4128         led_method_func fp;
4129
4130         if ((!onoff) == (!hdw->led_on)) return;
4131
4132         hdw->led_on = onoff != 0;
4133
4134         scheme_id = hdw->hdw_desc->led_scheme;
4135         if (scheme_id < ARRAY_SIZE(led_methods)) {
4136                 fp = led_methods[scheme_id];
4137         } else {
4138                 fp = NULL;
4139         }
4140
4141         if (fp) (*fp)(hdw,onoff);
4142 }
4143
4144
4145 /* Stop / start video stream transport */
4146 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4147 {
4148         int ret;
4149
4150         /* If we're in analog mode, then just issue the usual analog
4151            command. */
4152         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4153                 return pvr2_issue_simple_cmd(hdw,
4154                                              (runFl ?
4155                                               FX2CMD_STREAMING_ON :
4156                                               FX2CMD_STREAMING_OFF));
4157                 /*Note: Not reached */
4158         }
4159
4160         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4161                 /* Whoops, we don't know what mode we're in... */
4162                 return -EINVAL;
4163         }
4164
4165         /* To get here we have to be in digital mode.  The mechanism here
4166            is unfortunately different for different vendors.  So we switch
4167            on the device's digital scheme attribute in order to figure out
4168            what to do. */
4169         switch (hdw->hdw_desc->digital_control_scheme) {
4170         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4171                 return pvr2_issue_simple_cmd(hdw,
4172                                              (runFl ?
4173                                               FX2CMD_HCW_DTV_STREAMING_ON :
4174                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4175         case PVR2_DIGITAL_SCHEME_ONAIR:
4176                 ret = pvr2_issue_simple_cmd(hdw,
4177                                             (runFl ?
4178                                              FX2CMD_STREAMING_ON :
4179                                              FX2CMD_STREAMING_OFF));
4180                 if (ret) return ret;
4181                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4182         default:
4183                 return -EINVAL;
4184         }
4185 }
4186
4187
4188 /* Evaluate whether or not state_pathway_ok can change */
4189 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4190 {
4191         if (hdw->state_pathway_ok) {
4192                 /* Nothing to do if pathway is already ok */
4193                 return 0;
4194         }
4195         if (!hdw->state_pipeline_idle) {
4196                 /* Not allowed to change anything if pipeline is not idle */
4197                 return 0;
4198         }
4199         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4200         hdw->state_pathway_ok = !0;
4201         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4202         return !0;
4203 }
4204
4205
4206 /* Evaluate whether or not state_encoder_ok can change */
4207 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4208 {
4209         if (hdw->state_encoder_ok) return 0;
4210         if (hdw->flag_tripped) return 0;
4211         if (hdw->state_encoder_run) return 0;
4212         if (hdw->state_encoder_config) return 0;
4213         if (hdw->state_decoder_run) return 0;
4214         if (hdw->state_usbstream_run) return 0;
4215         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4216                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4217         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4218                 return 0;
4219         }
4220
4221         if (pvr2_upload_firmware2(hdw) < 0) {
4222                 hdw->flag_tripped = !0;
4223                 trace_stbit("flag_tripped",hdw->flag_tripped);
4224                 return !0;
4225         }
4226         hdw->state_encoder_ok = !0;
4227         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4228         return !0;
4229 }
4230
4231
4232 /* Evaluate whether or not state_encoder_config can change */
4233 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4234 {
4235         if (hdw->state_encoder_config) {
4236                 if (hdw->state_encoder_ok) {
4237                         if (hdw->state_pipeline_req &&
4238                             !hdw->state_pipeline_pause) return 0;
4239                 }
4240                 hdw->state_encoder_config = 0;
4241                 hdw->state_encoder_waitok = 0;
4242                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4243                 /* paranoia - solve race if timer just completed */
4244                 del_timer_sync(&hdw->encoder_wait_timer);
4245         } else {
4246                 if (!hdw->state_pathway_ok ||
4247                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4248                     !hdw->state_encoder_ok ||
4249                     !hdw->state_pipeline_idle ||
4250                     hdw->state_pipeline_pause ||
4251                     !hdw->state_pipeline_req ||
4252                     !hdw->state_pipeline_config) {
4253                         /* We must reset the enforced wait interval if
4254                            anything has happened that might have disturbed
4255                            the encoder.  This should be a rare case. */
4256                         if (timer_pending(&hdw->encoder_wait_timer)) {
4257                                 del_timer_sync(&hdw->encoder_wait_timer);
4258                         }
4259                         if (hdw->state_encoder_waitok) {
4260                                 /* Must clear the state - therefore we did
4261                                    something to a state bit and must also
4262                                    return true. */
4263                                 hdw->state_encoder_waitok = 0;
4264                                 trace_stbit("state_encoder_waitok",
4265                                             hdw->state_encoder_waitok);
4266                                 return !0;
4267                         }
4268                         return 0;
4269                 }
4270                 if (!hdw->state_encoder_waitok) {
4271                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4272                                 /* waitok flag wasn't set and timer isn't
4273                                    running.  Check flag once more to avoid
4274                                    a race then start the timer.  This is
4275                                    the point when we measure out a minimal
4276                                    quiet interval before doing something to
4277                                    the encoder. */
4278                                 if (!hdw->state_encoder_waitok) {
4279                                         hdw->encoder_wait_timer.expires =
4280                                                 jiffies + msecs_to_jiffies(
4281                                                 TIME_MSEC_ENCODER_WAIT);
4282                                         add_timer(&hdw->encoder_wait_timer);
4283                                 }
4284                         }
4285                         /* We can't continue until we know we have been
4286                            quiet for the interval measured by this
4287                            timer. */
4288                         return 0;
4289                 }
4290                 pvr2_encoder_configure(hdw);
4291                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4292         }
4293         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4294         return !0;
4295 }
4296
4297
4298 /* Return true if the encoder should not be running. */
4299 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4300 {
4301         if (!hdw->state_encoder_ok) {
4302                 /* Encoder isn't healthy at the moment, so stop it. */
4303                 return !0;
4304         }
4305         if (!hdw->state_pathway_ok) {
4306                 /* Mode is not understood at the moment (i.e. it wants to
4307                    change), so encoder must be stopped. */
4308                 return !0;
4309         }
4310
4311         switch (hdw->pathway_state) {
4312         case PVR2_PATHWAY_ANALOG:
4313                 if (!hdw->state_decoder_run) {
4314                         /* We're in analog mode and the decoder is not
4315                            running; thus the encoder should be stopped as
4316                            well. */
4317                         return !0;
4318                 }
4319                 break;
4320         case PVR2_PATHWAY_DIGITAL:
4321                 if (hdw->state_encoder_runok) {
4322                         /* This is a funny case.  We're in digital mode so
4323                            really the encoder should be stopped.  However
4324                            if it really is running, only kill it after
4325                            runok has been set.  This gives a chance for the
4326                            onair quirk to function (encoder must run
4327                            briefly first, at least once, before onair
4328                            digital streaming can work). */
4329                         return !0;
4330                 }
4331                 break;
4332         default:
4333                 /* Unknown mode; so encoder should be stopped. */
4334                 return !0;
4335         }
4336
4337         /* If we get here, we haven't found a reason to stop the
4338            encoder. */
4339         return 0;
4340 }
4341
4342
4343 /* Return true if the encoder should be running. */
4344 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4345 {
4346         if (!hdw->state_encoder_ok) {
4347                 /* Don't run the encoder if it isn't healthy... */
4348                 return 0;
4349         }
4350         if (!hdw->state_pathway_ok) {
4351                 /* Don't run the encoder if we don't (yet) know what mode
4352                    we need to be in... */
4353                 return 0;
4354         }
4355
4356         switch (hdw->pathway_state) {
4357         case PVR2_PATHWAY_ANALOG:
4358                 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
4359                         /* In analog mode, if the decoder is running, then
4360                            run the encoder. */
4361                         return !0;
4362                 }
4363                 break;
4364         case PVR2_PATHWAY_DIGITAL:
4365                 if ((hdw->hdw_desc->digital_control_scheme ==
4366                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4367                     !hdw->state_encoder_runok) {
4368                         /* This is a quirk.  OnAir hardware won't stream
4369                            digital until the encoder has been run at least
4370                            once, for a minimal period of time (empiricially
4371                            measured to be 1/4 second).  So if we're on
4372                            OnAir hardware and the encoder has never been
4373                            run at all, then start the encoder.  Normal
4374                            state machine logic in the driver will
4375                            automatically handle the remaining bits. */
4376                         return !0;
4377                 }
4378                 break;
4379         default:
4380                 /* For completeness (unknown mode; encoder won't run ever) */
4381                 break;
4382         }
4383         /* If we get here, then we haven't found any reason to run the
4384            encoder, so don't run it. */
4385         return 0;
4386 }
4387
4388
4389 /* Evaluate whether or not state_encoder_run can change */
4390 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4391 {
4392         if (hdw->state_encoder_run) {
4393                 if (!state_check_disable_encoder_run(hdw)) return 0;
4394                 if (hdw->state_encoder_ok) {
4395                         del_timer_sync(&hdw->encoder_run_timer);
4396                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4397                 }
4398                 hdw->state_encoder_run = 0;
4399         } else {
4400                 if (!state_check_enable_encoder_run(hdw)) return 0;
4401                 if (pvr2_encoder_start(hdw) < 0) return !0;
4402                 hdw->state_encoder_run = !0;
4403                 if (!hdw->state_encoder_runok) {
4404                         hdw->encoder_run_timer.expires = jiffies +
4405                                  msecs_to_jiffies(TIME_MSEC_ENCODER_OK);
4406                         add_timer(&hdw->encoder_run_timer);
4407                 }
4408         }
4409         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4410         return !0;
4411 }
4412
4413
4414 /* Timeout function for quiescent timer. */
4415 static void pvr2_hdw_quiescent_timeout(struct timer_list *t)
4416 {
4417         struct pvr2_hdw *hdw = from_timer(hdw, t, quiescent_timer);
4418         hdw->state_decoder_quiescent = !0;
4419         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4420         hdw->state_stale = !0;
4421         schedule_work(&hdw->workpoll);
4422 }
4423
4424
4425 /* Timeout function for decoder stabilization timer. */
4426 static void pvr2_hdw_decoder_stabilization_timeout(struct timer_list *t)
4427 {
4428         struct pvr2_hdw *hdw = from_timer(hdw, t, decoder_stabilization_timer);
4429         hdw->state_decoder_ready = !0;
4430         trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4431         hdw->state_stale = !0;
4432         schedule_work(&hdw->workpoll);
4433 }
4434
4435
4436 /* Timeout function for encoder wait timer. */
4437 static void pvr2_hdw_encoder_wait_timeout(struct timer_list *t)
4438 {
4439         struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_wait_timer);
4440         hdw->state_encoder_waitok = !0;
4441         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4442         hdw->state_stale = !0;
4443         schedule_work(&hdw->workpoll);
4444 }
4445
4446
4447 /* Timeout function for encoder run timer. */
4448 static void pvr2_hdw_encoder_run_timeout(struct timer_list *t)
4449 {
4450         struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_run_timer);
4451         if (!hdw->state_encoder_runok) {
4452                 hdw->state_encoder_runok = !0;
4453                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4454                 hdw->state_stale = !0;
4455                 schedule_work(&hdw->workpoll);
4456         }
4457 }
4458
4459
4460 /* Evaluate whether or not state_decoder_run can change */
4461 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4462 {
4463         if (hdw->state_decoder_run) {
4464                 if (hdw->state_encoder_ok) {
4465                         if (hdw->state_pipeline_req &&
4466                             !hdw->state_pipeline_pause &&
4467                             hdw->state_pathway_ok) return 0;
4468                 }
4469                 if (!hdw->flag_decoder_missed) {
4470                         pvr2_decoder_enable(hdw,0);
4471                 }
4472                 hdw->state_decoder_quiescent = 0;
4473                 hdw->state_decoder_run = 0;
4474                 /* paranoia - solve race if timer(s) just completed */
4475                 del_timer_sync(&hdw->quiescent_timer);
4476                 /* Kill the stabilization timer, in case we're killing the
4477                    encoder before the previous stabilization interval has
4478                    been properly timed. */
4479                 del_timer_sync(&hdw->decoder_stabilization_timer);
4480                 hdw->state_decoder_ready = 0;
4481         } else {
4482                 if (!hdw->state_decoder_quiescent) {
4483                         if (!timer_pending(&hdw->quiescent_timer)) {
4484                                 /* We don't do something about the
4485                                    quiescent timer until right here because
4486                                    we also want to catch cases where the
4487                                    decoder was already not running (like
4488                                    after initialization) as opposed to
4489                                    knowing that we had just stopped it.
4490                                    The second flag check is here to cover a
4491                                    race - the timer could have run and set
4492                                    this flag just after the previous check
4493                                    but before we did the pending check. */
4494                                 if (!hdw->state_decoder_quiescent) {
4495                                         hdw->quiescent_timer.expires =
4496                                                 jiffies + msecs_to_jiffies(
4497                                                 TIME_MSEC_DECODER_WAIT);
4498                                         add_timer(&hdw->quiescent_timer);
4499                                 }
4500                         }
4501                         /* Don't allow decoder to start again until it has
4502                            been quiesced first.  This little detail should
4503                            hopefully further stabilize the encoder. */
4504                         return 0;
4505                 }
4506                 if (!hdw->state_pathway_ok ||
4507                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4508                     !hdw->state_pipeline_req ||
4509                     hdw->state_pipeline_pause ||
4510                     !hdw->state_pipeline_config ||
4511                     !hdw->state_encoder_config ||
4512                     !hdw->state_encoder_ok) return 0;
4513                 del_timer_sync(&hdw->quiescent_timer);
4514                 if (hdw->flag_decoder_missed) return 0;
4515                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4516                 hdw->state_decoder_quiescent = 0;
4517                 hdw->state_decoder_ready = 0;
4518                 hdw->state_decoder_run = !0;
4519                 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4520                         hdw->decoder_stabilization_timer.expires =
4521                                 jiffies + msecs_to_jiffies(
4522                                 TIME_MSEC_DECODER_STABILIZATION_WAIT);
4523                         add_timer(&hdw->decoder_stabilization_timer);
4524                 } else {
4525                         hdw->state_decoder_ready = !0;
4526                 }
4527         }
4528         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4529         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4530         trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4531         return !0;
4532 }
4533
4534
4535 /* Evaluate whether or not state_usbstream_run can change */
4536 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4537 {
4538         if (hdw->state_usbstream_run) {
4539                 int fl = !0;
4540                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4541                         fl = (hdw->state_encoder_ok &&
4542                               hdw->state_encoder_run);
4543                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4544                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4545                         fl = hdw->state_encoder_ok;
4546                 }
4547                 if (fl &&
4548                     hdw->state_pipeline_req &&
4549                     !hdw->state_pipeline_pause &&
4550                     hdw->state_pathway_ok) {
4551                         return 0;
4552                 }
4553                 pvr2_hdw_cmd_usbstream(hdw,0);
4554                 hdw->state_usbstream_run = 0;
4555         } else {
4556                 if (!hdw->state_pipeline_req ||
4557                     hdw->state_pipeline_pause ||
4558                     !hdw->state_pathway_ok) return 0;
4559                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4560                         if (!hdw->state_encoder_ok ||
4561                             !hdw->state_encoder_run) return 0;
4562                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4563                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4564                         if (!hdw->state_encoder_ok) return 0;
4565                         if (hdw->state_encoder_run) return 0;
4566                         if (hdw->hdw_desc->digital_control_scheme ==
4567                             PVR2_DIGITAL_SCHEME_ONAIR) {
4568                                 /* OnAir digital receivers won't stream
4569                                    unless the analog encoder has run first.
4570                                    Why?  I have no idea.  But don't even
4571                                    try until we know the analog side is
4572                                    known to have run. */
4573                                 if (!hdw->state_encoder_runok) return 0;
4574                         }
4575                 }
4576                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4577                 hdw->state_usbstream_run = !0;
4578         }
4579         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4580         return !0;
4581 }
4582
4583
4584 /* Attempt to configure pipeline, if needed */
4585 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4586 {
4587         if (hdw->state_pipeline_config ||
4588             hdw->state_pipeline_pause) return 0;
4589         pvr2_hdw_commit_execute(hdw);
4590         return !0;
4591 }
4592
4593
4594 /* Update pipeline idle and pipeline pause tracking states based on other
4595    inputs.  This must be called whenever the other relevant inputs have
4596    changed. */
4597 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4598 {
4599         unsigned int st;
4600         int updatedFl = 0;
4601         /* Update pipeline state */
4602         st = !(hdw->state_encoder_run ||
4603                hdw->state_decoder_run ||
4604                hdw->state_usbstream_run ||
4605                (!hdw->state_decoder_quiescent));
4606         if (!st != !hdw->state_pipeline_idle) {
4607                 hdw->state_pipeline_idle = st;
4608                 updatedFl = !0;
4609         }
4610         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4611                 hdw->state_pipeline_pause = 0;
4612                 updatedFl = !0;
4613         }
4614         return updatedFl;
4615 }
4616
4617
4618 typedef int (*state_eval_func)(struct pvr2_hdw *);
4619
4620 /* Set of functions to be run to evaluate various states in the driver. */
4621 static const state_eval_func eval_funcs[] = {
4622         state_eval_pathway_ok,
4623         state_eval_pipeline_config,
4624         state_eval_encoder_ok,
4625         state_eval_encoder_config,
4626         state_eval_decoder_run,
4627         state_eval_encoder_run,
4628         state_eval_usbstream_run,
4629 };
4630
4631
4632 /* Process various states and return true if we did anything interesting. */
4633 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4634 {
4635         unsigned int i;
4636         int state_updated = 0;
4637         int check_flag;
4638
4639         if (!hdw->state_stale) return 0;
4640         if ((hdw->fw1_state != FW1_STATE_OK) ||
4641             !hdw->flag_ok) {
4642                 hdw->state_stale = 0;
4643                 return !0;
4644         }
4645         /* This loop is the heart of the entire driver.  It keeps trying to
4646            evaluate various bits of driver state until nothing changes for
4647            one full iteration.  Each "bit of state" tracks some global
4648            aspect of the driver, e.g. whether decoder should run, if
4649            pipeline is configured, usb streaming is on, etc.  We separately
4650            evaluate each of those questions based on other driver state to
4651            arrive at the correct running configuration. */
4652         do {
4653                 check_flag = 0;
4654                 state_update_pipeline_state(hdw);
4655                 /* Iterate over each bit of state */
4656                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4657                         if ((*eval_funcs[i])(hdw)) {
4658                                 check_flag = !0;
4659                                 state_updated = !0;
4660                                 state_update_pipeline_state(hdw);
4661                         }
4662                 }
4663         } while (check_flag && hdw->flag_ok);
4664         hdw->state_stale = 0;
4665         trace_stbit("state_stale",hdw->state_stale);
4666         return state_updated;
4667 }
4668
4669
4670 static unsigned int print_input_mask(unsigned int msk,
4671                                      char *buf,unsigned int acnt)
4672 {
4673         unsigned int idx,ccnt;
4674         unsigned int tcnt = 0;
4675         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4676                 if (!((1 << idx) & msk)) continue;
4677                 ccnt = scnprintf(buf+tcnt,
4678                                  acnt-tcnt,
4679                                  "%s%s",
4680                                  (tcnt ? ", " : ""),
4681                                  control_values_input[idx]);
4682                 tcnt += ccnt;
4683         }
4684         return tcnt;
4685 }
4686
4687
4688 static const char *pvr2_pathway_state_name(int id)
4689 {
4690         switch (id) {
4691         case PVR2_PATHWAY_ANALOG: return "analog";
4692         case PVR2_PATHWAY_DIGITAL: return "digital";
4693         default: return "unknown";
4694         }
4695 }
4696
4697
4698 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4699                                              char *buf,unsigned int acnt)
4700 {
4701         switch (which) {
4702         case 0:
4703                 return scnprintf(
4704                         buf,acnt,
4705                         "driver:%s%s%s%s%s <mode=%s>",
4706                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4707                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4708                         (hdw->flag_disconnected ? " <disconnected>" :
4709                          " <connected>"),
4710                         (hdw->flag_tripped ? " <tripped>" : ""),
4711                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4712                         pvr2_pathway_state_name(hdw->pathway_state));
4713
4714         case 1:
4715                 return scnprintf(
4716                         buf,acnt,
4717                         "pipeline:%s%s%s%s",
4718                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4719                         (hdw->state_pipeline_config ?
4720                          " <configok>" : " <stale>"),
4721                         (hdw->state_pipeline_req ? " <req>" : ""),
4722                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4723         case 2:
4724                 return scnprintf(
4725                         buf,acnt,
4726                         "worker:%s%s%s%s%s%s%s",
4727                         (hdw->state_decoder_run ?
4728                          (hdw->state_decoder_ready ?
4729                           "<decode:run>" : " <decode:start>") :
4730                          (hdw->state_decoder_quiescent ?
4731                           "" : " <decode:stop>")),
4732                         (hdw->state_decoder_quiescent ?
4733                          " <decode:quiescent>" : ""),
4734                         (hdw->state_encoder_ok ?
4735                          "" : " <encode:init>"),
4736                         (hdw->state_encoder_run ?
4737                          (hdw->state_encoder_runok ?
4738                           " <encode:run>" :
4739                           " <encode:firstrun>") :
4740                          (hdw->state_encoder_runok ?
4741                           " <encode:stop>" :
4742                           " <encode:virgin>")),
4743                         (hdw->state_encoder_config ?
4744                          " <encode:configok>" :
4745                          (hdw->state_encoder_waitok ?
4746                           "" : " <encode:waitok>")),
4747                         (hdw->state_usbstream_run ?
4748                          " <usb:run>" : " <usb:stop>"),
4749                         (hdw->state_pathway_ok ?
4750                          " <pathway:ok>" : ""));
4751         case 3:
4752                 return scnprintf(
4753                         buf,acnt,
4754                         "state: %s",
4755                         pvr2_get_state_name(hdw->master_state));
4756         case 4: {
4757                 unsigned int tcnt = 0;
4758                 unsigned int ccnt;
4759
4760                 ccnt = scnprintf(buf,
4761                                  acnt,
4762                                  "Hardware supported inputs: ");
4763                 tcnt += ccnt;
4764                 tcnt += print_input_mask(hdw->input_avail_mask,
4765                                          buf+tcnt,
4766                                          acnt-tcnt);
4767                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4768                         ccnt = scnprintf(buf+tcnt,
4769                                          acnt-tcnt,
4770                                          "; allowed inputs: ");
4771                         tcnt += ccnt;
4772                         tcnt += print_input_mask(hdw->input_allowed_mask,
4773                                                  buf+tcnt,
4774                                                  acnt-tcnt);
4775                 }
4776                 return tcnt;
4777         }
4778         case 5: {
4779                 struct pvr2_stream_stats stats;
4780                 if (!hdw->vid_stream) break;
4781                 pvr2_stream_get_stats(hdw->vid_stream,
4782                                       &stats,
4783                                       0);
4784                 return scnprintf(
4785                         buf,acnt,
4786                         "Bytes streamed=%u URBs: queued=%u idle=%u ready=%u processed=%u failed=%u",
4787                         stats.bytes_processed,
4788                         stats.buffers_in_queue,
4789                         stats.buffers_in_idle,
4790                         stats.buffers_in_ready,
4791                         stats.buffers_processed,
4792                         stats.buffers_failed);
4793         }
4794         case 6: {
4795                 unsigned int id = hdw->ir_scheme_active;
4796                 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4797                                  (id >= ARRAY_SIZE(ir_scheme_names) ?
4798                                   "?" : ir_scheme_names[id]));
4799         }
4800         default: break;
4801         }
4802         return 0;
4803 }
4804
4805
4806 /* Generate report containing info about attached sub-devices and attached
4807    i2c clients, including an indication of which attached i2c clients are
4808    actually sub-devices. */
4809 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4810                                             char *buf, unsigned int acnt)
4811 {
4812         struct v4l2_subdev *sd;
4813         unsigned int tcnt = 0;
4814         unsigned int ccnt;
4815         struct i2c_client *client;
4816         const char *p;
4817         unsigned int id;
4818
4819         ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
4820         tcnt += ccnt;
4821         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4822                 id = sd->grp_id;
4823                 p = NULL;
4824                 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4825                 if (p) {
4826                         ccnt = scnprintf(buf + tcnt, acnt - tcnt, "  %s:", p);
4827                         tcnt += ccnt;
4828                 } else {
4829                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4830                                          "  (unknown id=%u):", id);
4831                         tcnt += ccnt;
4832                 }
4833                 client = v4l2_get_subdevdata(sd);
4834                 if (client) {
4835                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4836                                          " %s @ %02x\n", client->name,
4837                                          client->addr);
4838                         tcnt += ccnt;
4839                 } else {
4840                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4841                                          " no i2c client\n");
4842                         tcnt += ccnt;
4843                 }
4844         }
4845         return tcnt;
4846 }
4847
4848
4849 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4850                                    char *buf,unsigned int acnt)
4851 {
4852         unsigned int bcnt,ccnt,idx;
4853         bcnt = 0;
4854         LOCK_TAKE(hdw->big_lock);
4855         for (idx = 0; ; idx++) {
4856                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4857                 if (!ccnt) break;
4858                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4859                 if (!acnt) break;
4860                 buf[0] = '\n'; ccnt = 1;
4861                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4862         }
4863         ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4864         bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4865         LOCK_GIVE(hdw->big_lock);
4866         return bcnt;
4867 }
4868
4869
4870 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4871 {
4872         char buf[256];
4873         unsigned int idx, ccnt;
4874         unsigned int lcnt, ucnt;
4875
4876         for (idx = 0; ; idx++) {
4877                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4878                 if (!ccnt) break;
4879                 pr_info("%s %.*s\n", hdw->name, ccnt, buf);
4880         }
4881         ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4882         if (ccnt >= sizeof(buf))
4883                 ccnt = sizeof(buf);
4884
4885         ucnt = 0;
4886         while (ucnt < ccnt) {
4887                 lcnt = 0;
4888                 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4889                         lcnt++;
4890                 }
4891                 pr_info("%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4892                 ucnt += lcnt + 1;
4893         }
4894 }
4895
4896
4897 /* Evaluate and update the driver's current state, taking various actions
4898    as appropriate for the update. */
4899 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4900 {
4901         unsigned int st;
4902         int state_updated = 0;
4903         int callback_flag = 0;
4904         int analog_mode;
4905
4906         pvr2_trace(PVR2_TRACE_STBITS,
4907                    "Drive state check START");
4908         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4909                 pvr2_hdw_state_log_state(hdw);
4910         }
4911
4912         /* Process all state and get back over disposition */
4913         state_updated = pvr2_hdw_state_update(hdw);
4914
4915         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4916
4917         /* Update master state based upon all other states. */
4918         if (!hdw->flag_ok) {
4919                 st = PVR2_STATE_DEAD;
4920         } else if (hdw->fw1_state != FW1_STATE_OK) {
4921                 st = PVR2_STATE_COLD;
4922         } else if ((analog_mode ||
4923                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4924                    !hdw->state_encoder_ok) {
4925                 st = PVR2_STATE_WARM;
4926         } else if (hdw->flag_tripped ||
4927                    (analog_mode && hdw->flag_decoder_missed)) {
4928                 st = PVR2_STATE_ERROR;
4929         } else if (hdw->state_usbstream_run &&
4930                    (!analog_mode ||
4931                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4932                 st = PVR2_STATE_RUN;
4933         } else {
4934                 st = PVR2_STATE_READY;
4935         }
4936         if (hdw->master_state != st) {
4937                 pvr2_trace(PVR2_TRACE_STATE,
4938                            "Device state change from %s to %s",
4939                            pvr2_get_state_name(hdw->master_state),
4940                            pvr2_get_state_name(st));
4941                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4942                 hdw->master_state = st;
4943                 state_updated = !0;
4944                 callback_flag = !0;
4945         }
4946         if (state_updated) {
4947                 /* Trigger anyone waiting on any state changes here. */
4948                 wake_up(&hdw->state_wait_data);
4949         }
4950
4951         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4952                 pvr2_hdw_state_log_state(hdw);
4953         }
4954         pvr2_trace(PVR2_TRACE_STBITS,
4955                    "Drive state check DONE callback=%d",callback_flag);
4956
4957         return callback_flag;
4958 }
4959
4960
4961 /* Cause kernel thread to check / update driver state */
4962 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4963 {
4964         if (hdw->state_stale) return;
4965         hdw->state_stale = !0;
4966         trace_stbit("state_stale",hdw->state_stale);
4967         schedule_work(&hdw->workpoll);
4968 }
4969
4970
4971 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4972 {
4973         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4974 }
4975
4976
4977 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4978 {
4979         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4980 }
4981
4982
4983 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4984 {
4985         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4986 }
4987
4988
4989 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4990 {
4991         u32 cval,nval;
4992         int ret;
4993         if (~msk) {
4994                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4995                 if (ret) return ret;
4996                 nval = (cval & ~msk) | (val & msk);
4997                 pvr2_trace(PVR2_TRACE_GPIO,
4998                            "GPIO direction changing 0x%x:0x%x from 0x%x to 0x%x",
4999                            msk,val,cval,nval);
5000         } else {
5001                 nval = val;
5002                 pvr2_trace(PVR2_TRACE_GPIO,
5003                            "GPIO direction changing to 0x%x",nval);
5004         }
5005         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5006 }
5007
5008
5009 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5010 {
5011         u32 cval,nval;
5012         int ret;
5013         if (~msk) {
5014                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5015                 if (ret) return ret;
5016                 nval = (cval & ~msk) | (val & msk);
5017                 pvr2_trace(PVR2_TRACE_GPIO,
5018                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5019                            msk,val,cval,nval);
5020         } else {
5021                 nval = val;
5022                 pvr2_trace(PVR2_TRACE_GPIO,
5023                            "GPIO output changing to 0x%x",nval);
5024         }
5025         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5026 }
5027
5028
5029 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5030 {
5031         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5032         memset(vtp, 0, sizeof(*vtp));
5033         vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
5034                 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
5035         hdw->tuner_signal_stale = 0;
5036         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5037            using v4l2-subdev - therefore we can't support that AT ALL right
5038            now.  (Of course, no sub-drivers seem to implement it either.
5039            But now it's a a chicken and egg problem...) */
5040         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
5041         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll type=%u strength=%u audio=0x%x cap=0x%x low=%u hi=%u",
5042                    vtp->type,
5043                    vtp->signal, vtp->rxsubchans, vtp->capability,
5044                    vtp->rangelow, vtp->rangehigh);
5045
5046         /* We have to do this to avoid getting into constant polling if
5047            there's nobody to answer a poll of cropcap info. */
5048         hdw->cropcap_stale = 0;
5049 }
5050
5051
5052 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5053 {
5054         return hdw->input_avail_mask;
5055 }
5056
5057
5058 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5059 {
5060         return hdw->input_allowed_mask;
5061 }
5062
5063
5064 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5065 {
5066         if (hdw->input_val != v) {
5067                 hdw->input_val = v;
5068                 hdw->input_dirty = !0;
5069         }
5070
5071         /* Handle side effects - if we switch to a mode that needs the RF
5072            tuner, then select the right frequency choice as well and mark
5073            it dirty. */
5074         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5075                 hdw->freqSelector = 0;
5076                 hdw->freqDirty = !0;
5077         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5078                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5079                 hdw->freqSelector = 1;
5080                 hdw->freqDirty = !0;
5081         }
5082         return 0;
5083 }
5084
5085
5086 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5087                                unsigned int change_mask,
5088                                unsigned int change_val)
5089 {
5090         int ret = 0;
5091         unsigned int nv,m,idx;
5092         LOCK_TAKE(hdw->big_lock);
5093         do {
5094                 nv = hdw->input_allowed_mask & ~change_mask;
5095                 nv |= (change_val & change_mask);
5096                 nv &= hdw->input_avail_mask;
5097                 if (!nv) {
5098                         /* No legal modes left; return error instead. */
5099                         ret = -EPERM;
5100                         break;
5101                 }
5102                 hdw->input_allowed_mask = nv;
5103                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5104                         /* Current mode is still in the allowed mask, so
5105                            we're done. */
5106                         break;
5107                 }
5108                 /* Select and switch to a mode that is still in the allowed
5109                    mask */
5110                 if (!hdw->input_allowed_mask) {
5111                         /* Nothing legal; give up */
5112                         break;
5113                 }
5114                 m = hdw->input_allowed_mask;
5115                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5116                         if (!((1 << idx) & m)) continue;
5117                         pvr2_hdw_set_input(hdw,idx);
5118                         break;
5119                 }
5120         } while (0);
5121         LOCK_GIVE(hdw->big_lock);
5122         return ret;
5123 }
5124
5125
5126 /* Find I2C address of eeprom */
5127 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5128 {
5129         int result;
5130         LOCK_TAKE(hdw->ctl_lock); do {
5131                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5132                 result = pvr2_send_request(hdw,
5133                                            hdw->cmd_buffer,1,
5134                                            hdw->cmd_buffer,1);
5135                 if (result < 0) break;
5136                 result = hdw->cmd_buffer[0];
5137         } while(0); LOCK_GIVE(hdw->ctl_lock);
5138         return result;
5139 }