drivers/media/platform/exynos4-is/fimc-core.c

   1 /*
   2  * Samsung S5P/EXYNOS4 SoC series FIMC (CAMIF) driver
   3  *
   4  * Copyright (C) 2010-2012 Samsung Electronics Co., Ltd.
   5  * Sylwester Nawrocki <s.nawrocki@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published
   9  * by the Free Software Foundation, either version 2 of the License,
  10  * or (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 #include <linux/errno.h>
  17 #include <linux/bug.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/list.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/io.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/slab.h>
  28 #include <linux/clk.h>
  29 #include <media/v4l2-ioctl.h>
  30 #include <media/videobuf2-core.h>
  31 #include <media/videobuf2-dma-contig.h>
  32
  33 #include "fimc-core.h"
  34 #include "fimc-reg.h"
  35 #include "media-dev.h"
  36
  37 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
  38         "sclk_fimc", "fimc"
  39 };
  40
  41 static struct fimc_fmt fimc_formats[] = {
  42         {
  43                 .name           = "RGB565",
  44                 .fourcc         = V4L2_PIX_FMT_RGB565,
  45                 .depth          = { 16 },
  46                 .color          = FIMC_FMT_RGB565,
  47                 .memplanes      = 1,
  48                 .colplanes      = 1,
  49                 .flags          = FMT_FLAGS_M2M,
  50         }, {
  51                 .name           = "BGR666",
  52                 .fourcc         = V4L2_PIX_FMT_BGR666,
  53                 .depth          = { 32 },
  54                 .color          = FIMC_FMT_RGB666,
  55                 .memplanes      = 1,
  56                 .colplanes      = 1,
  57                 .flags          = FMT_FLAGS_M2M,
  58         }, {
  59                 .name           = "ARGB8888, 32 bpp",
  60                 .fourcc         = V4L2_PIX_FMT_RGB32,
  61                 .depth          = { 32 },
  62                 .color          = FIMC_FMT_RGB888,
  63                 .memplanes      = 1,
  64                 .colplanes      = 1,
  65                 .flags          = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
  66         }, {
  67                 .name           = "ARGB1555",
  68                 .fourcc         = V4L2_PIX_FMT_RGB555,
  69                 .depth          = { 16 },
  70                 .color          = FIMC_FMT_RGB555,
  71                 .memplanes      = 1,
  72                 .colplanes      = 1,
  73                 .flags          = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
  74         }, {
  75                 .name           = "ARGB4444",
  76                 .fourcc         = V4L2_PIX_FMT_RGB444,
  77                 .depth          = { 16 },
  78                 .color          = FIMC_FMT_RGB444,
  79                 .memplanes      = 1,
  80                 .colplanes      = 1,
  81                 .flags          = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
  82         }, {
  83                 .name           = "YUV 4:4:4",
  84                 .mbus_code      = V4L2_MBUS_FMT_YUV10_1X30,
  85                 .flags          = FMT_FLAGS_WRITEBACK,
  86         }, {
  87                 .name           = "YUV 4:2:2 packed, YCbYCr",
  88                 .fourcc         = V4L2_PIX_FMT_YUYV,
  89                 .depth          = { 16 },
  90                 .color          = FIMC_FMT_YCBYCR422,
  91                 .memplanes      = 1,
  92                 .colplanes      = 1,
  93                 .mbus_code      = V4L2_MBUS_FMT_YUYV8_2X8,
  94                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  95         }, {
  96                 .name           = "YUV 4:2:2 packed, CbYCrY",
  97                 .fourcc         = V4L2_PIX_FMT_UYVY,
  98                 .depth          = { 16 },
  99                 .color          = FIMC_FMT_CBYCRY422,
 100                 .memplanes      = 1,
 101                 .colplanes      = 1,
 102                 .mbus_code      = V4L2_MBUS_FMT_UYVY8_2X8,
 103                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 104         }, {
 105                 .name           = "YUV 4:2:2 packed, CrYCbY",
 106                 .fourcc         = V4L2_PIX_FMT_VYUY,
 107                 .depth          = { 16 },
 108                 .color          = FIMC_FMT_CRYCBY422,
 109                 .memplanes      = 1,
 110                 .colplanes      = 1,
 111                 .mbus_code      = V4L2_MBUS_FMT_VYUY8_2X8,
 112                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 113         }, {
 114                 .name           = "YUV 4:2:2 packed, YCrYCb",
 115                 .fourcc         = V4L2_PIX_FMT_YVYU,
 116                 .depth          = { 16 },
 117                 .color          = FIMC_FMT_YCRYCB422,
 118                 .memplanes      = 1,
 119                 .colplanes      = 1,
 120                 .mbus_code      = V4L2_MBUS_FMT_YVYU8_2X8,
 121                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 122         }, {
 123                 .name           = "YUV 4:2:2 planar, Y/Cb/Cr",
 124                 .fourcc         = V4L2_PIX_FMT_YUV422P,
 125                 .depth          = { 12 },
 126                 .color          = FIMC_FMT_YCBYCR422,
 127                 .memplanes      = 1,
 128                 .colplanes      = 3,
 129                 .flags          = FMT_FLAGS_M2M,
 130         }, {
 131                 .name           = "YUV 4:2:2 planar, Y/CbCr",
 132                 .fourcc         = V4L2_PIX_FMT_NV16,
 133                 .depth          = { 16 },
 134                 .color          = FIMC_FMT_YCBYCR422,
 135                 .memplanes      = 1,
 136                 .colplanes      = 2,
 137                 .flags          = FMT_FLAGS_M2M,
 138         }, {
 139                 .name           = "YUV 4:2:2 planar, Y/CrCb",
 140                 .fourcc         = V4L2_PIX_FMT_NV61,
 141                 .depth          = { 16 },
 142                 .color          = FIMC_FMT_YCRYCB422,
 143                 .memplanes      = 1,
 144                 .colplanes      = 2,
 145                 .flags          = FMT_FLAGS_M2M,
 146         }, {
 147                 .name           = "YUV 4:2:0 planar, YCbCr",
 148                 .fourcc         = V4L2_PIX_FMT_YUV420,
 149                 .depth          = { 12 },
 150                 .color          = FIMC_FMT_YCBCR420,
 151                 .memplanes      = 1,
 152                 .colplanes      = 3,
 153                 .flags          = FMT_FLAGS_M2M,
 154         }, {
 155                 .name           = "YUV 4:2:0 planar, Y/CbCr",
 156                 .fourcc         = V4L2_PIX_FMT_NV12,
 157                 .depth          = { 12 },
 158                 .color          = FIMC_FMT_YCBCR420,
 159                 .memplanes      = 1,
 160                 .colplanes      = 2,
 161                 .flags          = FMT_FLAGS_M2M,
 162         }, {
 163                 .name           = "YUV 4:2:0 non-contig. 2p, Y/CbCr",
 164                 .fourcc         = V4L2_PIX_FMT_NV12M,
 165                 .color          = FIMC_FMT_YCBCR420,
 166                 .depth          = { 8, 4 },
 167                 .memplanes      = 2,
 168                 .colplanes      = 2,
 169                 .flags          = FMT_FLAGS_M2M,
 170         }, {
 171                 .name           = "YUV 4:2:0 non-contig. 3p, Y/Cb/Cr",
 172                 .fourcc         = V4L2_PIX_FMT_YUV420M,
 173                 .color          = FIMC_FMT_YCBCR420,
 174                 .depth          = { 8, 2, 2 },
 175                 .memplanes      = 3,
 176                 .colplanes      = 3,
 177                 .flags          = FMT_FLAGS_M2M,
 178         }, {
 179                 .name           = "YUV 4:2:0 non-contig. 2p, tiled",
 180                 .fourcc         = V4L2_PIX_FMT_NV12MT,
 181                 .color          = FIMC_FMT_YCBCR420,
 182                 .depth          = { 8, 4 },
 183                 .memplanes      = 2,
 184                 .colplanes      = 2,
 185                 .flags          = FMT_FLAGS_M2M,
 186         }, {
 187                 .name           = "JPEG encoded data",
 188                 .fourcc         = V4L2_PIX_FMT_JPEG,
 189                 .color          = FIMC_FMT_JPEG,
 190                 .depth          = { 8 },
 191                 .memplanes      = 1,
 192                 .colplanes      = 1,
 193                 .mbus_code      = V4L2_MBUS_FMT_JPEG_1X8,
 194                 .flags          = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED,
 195         }, {
 196                 .name           = "S5C73MX interleaved UYVY/JPEG",
 197                 .fourcc         = V4L2_PIX_FMT_S5C_UYVY_JPG,
 198                 .color          = FIMC_FMT_YUYV_JPEG,
 199                 .depth          = { 8 },
 200                 .memplanes      = 2,
 201                 .colplanes      = 1,
 202                 .mdataplanes    = 0x2, /* plane 1 holds frame meta data */
 203                 .mbus_code      = V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8,
 204                 .flags          = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED,
 205         },
 206 };
 207
 208 struct fimc_fmt *fimc_get_format(unsigned int index)
 209 {
 210         if (index >= ARRAY_SIZE(fimc_formats))
 211                 return NULL;
 212
 213         return &fimc_formats[index];
 214 }
 215
 216 void __fimc_vidioc_querycap(struct device *dev, struct v4l2_capability *cap,
 217                                                 unsigned int caps)
 218 {
 219         strlcpy(cap->driver, dev->driver->name, sizeof(cap->driver));
 220         strlcpy(cap->card, dev->driver->name, sizeof(cap->card));
 221         snprintf(cap->bus_info, sizeof(cap->bus_info),
 222                                 "platform:%s", dev_name(dev));
 223         cap->device_caps = caps;
 224         cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
 225 }
 226
 227 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
 228                             int dw, int dh, int rotation)
 229 {
 230         if (rotation == 90 || rotation == 270)
 231                 swap(dw, dh);
 232
 233         if (!ctx->scaler.enabled)
 234                 return (sw == dw && sh == dh) ? 0 : -EINVAL;
 235
 236         if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh))
 237                 return -EINVAL;
 238
 239         return 0;
 240 }
 241
 242 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
 243 {
 244         u32 sh = 6;
 245
 246         if (src >= 64 * tar)
 247                 return -EINVAL;
 248
 249         while (sh--) {
 250                 u32 tmp = 1 << sh;
 251                 if (src >= tar * tmp) {
 252                         *shift = sh, *ratio = tmp;
 253                         return 0;
 254                 }
 255         }
 256         *shift = 0, *ratio = 1;
 257         return 0;
 258 }
 259
 260 int fimc_set_scaler_info(struct fimc_ctx *ctx)
 261 {
 262         const struct fimc_variant *variant = ctx->fimc_dev->variant;
 263         struct device *dev = &ctx->fimc_dev->pdev->dev;
 264         struct fimc_scaler *sc = &ctx->scaler;
 265         struct fimc_frame *s_frame = &ctx->s_frame;
 266         struct fimc_frame *d_frame = &ctx->d_frame;
 267         int tx, ty, sx, sy;
 268         int ret;
 269
 270         if (ctx->rotation == 90 || ctx->rotation == 270) {
 271                 ty = d_frame->width;
 272                 tx = d_frame->height;
 273         } else {
 274                 tx = d_frame->width;
 275                 ty = d_frame->height;
 276         }
 277         if (tx <= 0 || ty <= 0) {
 278                 dev_err(dev, "Invalid target size: %dx%d\n", tx, ty);
 279                 return -EINVAL;
 280         }
 281
 282         sx = s_frame->width;
 283         sy = s_frame->height;
 284         if (sx <= 0 || sy <= 0) {
 285                 dev_err(dev, "Invalid source size: %dx%d\n", sx, sy);
 286                 return -EINVAL;
 287         }
 288         sc->real_width = sx;
 289         sc->real_height = sy;
 290
 291         ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
 292         if (ret)
 293                 return ret;
 294
 295         ret = fimc_get_scaler_factor(sy, ty,  &sc->pre_vratio, &sc->vfactor);
 296         if (ret)
 297                 return ret;
 298
 299         sc->pre_dst_width = sx / sc->pre_hratio;
 300         sc->pre_dst_height = sy / sc->pre_vratio;
 301
 302         if (variant->has_mainscaler_ext) {
 303                 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
 304                 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
 305         } else {
 306                 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
 307                 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
 308
 309         }
 310
 311         sc->scaleup_h = (tx >= sx) ? 1 : 0;
 312         sc->scaleup_v = (ty >= sy) ? 1 : 0;
 313
 314         /* check to see if input and output size/format differ */
 315         if (s_frame->fmt->color == d_frame->fmt->color
 316                 && s_frame->width == d_frame->width
 317                 && s_frame->height == d_frame->height)
 318                 sc->copy_mode = 1;
 319         else
 320                 sc->copy_mode = 0;
 321
 322         return 0;
 323 }
 324
 325 static irqreturn_t fimc_irq_handler(int irq, void *priv)
 326 {
 327         struct fimc_dev *fimc = priv;
 328         struct fimc_ctx *ctx;
 329
 330         fimc_hw_clear_irq(fimc);
 331
 332         spin_lock(&fimc->slock);
 333
 334         if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
 335                 if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) {
 336                         set_bit(ST_M2M_SUSPENDED, &fimc->state);
 337                         wake_up(&fimc->irq_queue);
 338                         goto out;
 339                 }
 340                 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
 341                 if (ctx != NULL) {
 342                         spin_unlock(&fimc->slock);
 343                         fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
 344
 345                         if (ctx->state & FIMC_CTX_SHUT) {
 346                                 ctx->state &= ~FIMC_CTX_SHUT;
 347                                 wake_up(&fimc->irq_queue);
 348                         }
 349                         return IRQ_HANDLED;
 350                 }
 351         } else if (test_bit(ST_CAPT_PEND, &fimc->state)) {
 352                 int last_buf = test_bit(ST_CAPT_JPEG, &fimc->state) &&
 353                                 fimc->vid_cap.reqbufs_count == 1;
 354                 fimc_capture_irq_handler(fimc, !last_buf);
 355         }
 356 out:
 357         spin_unlock(&fimc->slock);
 358         return IRQ_HANDLED;
 359 }
 360
 361 /* The color format (colplanes, memplanes) must be already configured. */
 362 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 363                       struct fimc_frame *frame, struct fimc_addr *paddr)
 364 {
 365         int ret = 0;
 366         u32 pix_size;
 367
 368         if (vb == NULL || frame == NULL)
 369                 return -EINVAL;
 370
 371         pix_size = frame->width * frame->height;
 372
 373         dbg("memplanes= %d, colplanes= %d, pix_size= %d",
 374                 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
 375
 376         paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
 377
 378         if (frame->fmt->memplanes == 1) {
 379                 switch (frame->fmt->colplanes) {
 380                 case 1:
 381                         paddr->cb = 0;
 382                         paddr->cr = 0;
 383                         break;
 384                 case 2:
 385                         /* decompose Y into Y/Cb */
 386                         paddr->cb = (u32)(paddr->y + pix_size);
 387                         paddr->cr = 0;
 388                         break;
 389                 case 3:
 390                         paddr->cb = (u32)(paddr->y + pix_size);
 391                         /* decompose Y into Y/Cb/Cr */
 392                         if (FIMC_FMT_YCBCR420 == frame->fmt->color)
 393                                 paddr->cr = (u32)(paddr->cb
 394                                                 + (pix_size >> 2));
 395                         else /* 422 */
 396                                 paddr->cr = (u32)(paddr->cb
 397                                                 + (pix_size >> 1));
 398                         break;
 399                 default:
 400                         return -EINVAL;
 401                 }
 402         } else if (!frame->fmt->mdataplanes) {
 403                 if (frame->fmt->memplanes >= 2)
 404                         paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
 405
 406                 if (frame->fmt->memplanes == 3)
 407                         paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
 408         }
 409
 410         dbg("PHYS_ADDR: y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
 411             paddr->y, paddr->cb, paddr->cr, ret);
 412
 413         return ret;
 414 }
 415
 416 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
 417 void fimc_set_yuv_order(struct fimc_ctx *ctx)
 418 {
 419         /* The one only mode supported in SoC. */
 420         ctx->in_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB;
 421         ctx->out_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB;
 422
 423         /* Set order for 1 plane input formats. */
 424         switch (ctx->s_frame.fmt->color) {
 425         case FIMC_FMT_YCRYCB422:
 426                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCRYCB;
 427                 break;
 428         case FIMC_FMT_CBYCRY422:
 429                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CBYCRY;
 430                 break;
 431         case FIMC_FMT_CRYCBY422:
 432                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CRYCBY;
 433                 break;
 434         case FIMC_FMT_YCBYCR422:
 435         default:
 436                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCBYCR;
 437                 break;
 438         }
 439         dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
 440
 441         switch (ctx->d_frame.fmt->color) {
 442         case FIMC_FMT_YCRYCB422:
 443                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCRYCB;
 444                 break;
 445         case FIMC_FMT_CBYCRY422:
 446                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CBYCRY;
 447                 break;
 448         case FIMC_FMT_CRYCBY422:
 449                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CRYCBY;
 450                 break;
 451         case FIMC_FMT_YCBYCR422:
 452         default:
 453                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCBYCR;
 454                 break;
 455         }
 456         dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
 457 }
 458
 459 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
 460 {
 461         bool pix_hoff = ctx->fimc_dev->drv_data->dma_pix_hoff;
 462         u32 i, depth = 0;
 463
 464         for (i = 0; i < f->fmt->colplanes; i++)
 465                 depth += f->fmt->depth[i];
 466
 467         f->dma_offset.y_h = f->offs_h;
 468         if (!pix_hoff)
 469                 f->dma_offset.y_h *= (depth >> 3);
 470
 471         f->dma_offset.y_v = f->offs_v;
 472
 473         f->dma_offset.cb_h = f->offs_h;
 474         f->dma_offset.cb_v = f->offs_v;
 475
 476         f->dma_offset.cr_h = f->offs_h;
 477         f->dma_offset.cr_v = f->offs_v;
 478
 479         if (!pix_hoff) {
 480                 if (f->fmt->colplanes == 3) {
 481                         f->dma_offset.cb_h >>= 1;
 482                         f->dma_offset.cr_h >>= 1;
 483                 }
 484                 if (f->fmt->color == FIMC_FMT_YCBCR420) {
 485                         f->dma_offset.cb_v >>= 1;
 486                         f->dma_offset.cr_v >>= 1;
 487                 }
 488         }
 489
 490         dbg("in_offset: color= %d, y_h= %d, y_v= %d",
 491             f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
 492 }
 493
 494 static int fimc_set_color_effect(struct fimc_ctx *ctx, enum v4l2_colorfx colorfx)
 495 {
 496         struct fimc_effect *effect = &ctx->effect;
 497
 498         switch (colorfx) {
 499         case V4L2_COLORFX_NONE:
 500                 effect->type = FIMC_REG_CIIMGEFF_FIN_BYPASS;
 501                 break;
 502         case V4L2_COLORFX_BW:
 503                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY;
 504                 effect->pat_cb = 128;
 505                 effect->pat_cr = 128;
 506                 break;
 507         case V4L2_COLORFX_SEPIA:
 508                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY;
 509                 effect->pat_cb = 115;
 510                 effect->pat_cr = 145;
 511                 break;
 512         case V4L2_COLORFX_NEGATIVE:
 513                 effect->type = FIMC_REG_CIIMGEFF_FIN_NEGATIVE;
 514                 break;
 515         case V4L2_COLORFX_EMBOSS:
 516                 effect->type = FIMC_REG_CIIMGEFF_FIN_EMBOSSING;
 517                 break;
 518         case V4L2_COLORFX_ART_FREEZE:
 519                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARTFREEZE;
 520                 break;
 521         case V4L2_COLORFX_SILHOUETTE:
 522                 effect->type = FIMC_REG_CIIMGEFF_FIN_SILHOUETTE;
 523                 break;
 524         case V4L2_COLORFX_SET_CBCR:
 525                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY;
 526                 effect->pat_cb = ctx->ctrls.colorfx_cbcr->val >> 8;
 527                 effect->pat_cr = ctx->ctrls.colorfx_cbcr->val & 0xff;
 528                 break;
 529         default:
 530                 return -EINVAL;
 531         }
 532
 533         return 0;
 534 }
 535
 536 /*
 537  * V4L2 controls handling
 538  */
 539 #define ctrl_to_ctx(__ctrl) \
 540         container_of((__ctrl)->handler, struct fimc_ctx, ctrls.handler)
 541
 542 static int __fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_ctrl *ctrl)
 543 {
 544         struct fimc_dev *fimc = ctx->fimc_dev;
 545         const struct fimc_variant *variant = fimc->variant;
 546         int ret = 0;
 547
 548         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
 549                 return 0;
 550
 551         switch (ctrl->id) {
 552         case V4L2_CID_HFLIP:
 553                 ctx->hflip = ctrl->val;
 554                 break;
 555
 556         case V4L2_CID_VFLIP:
 557                 ctx->vflip = ctrl->val;
 558                 break;
 559
 560         case V4L2_CID_ROTATE:
 561                 if (fimc_capture_pending(fimc)) {
 562                         ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
 563                                         ctx->s_frame.height, ctx->d_frame.width,
 564                                         ctx->d_frame.height, ctrl->val);
 565                         if (ret)
 566                                 return -EINVAL;
 567                 }
 568                 if ((ctrl->val == 90 || ctrl->val == 270) &&
 569                     !variant->has_out_rot)
 570                         return -EINVAL;
 571
 572                 ctx->rotation = ctrl->val;
 573                 break;
 574
 575         case V4L2_CID_ALPHA_COMPONENT:
 576                 ctx->d_frame.alpha = ctrl->val;
 577                 break;
 578
 579         case V4L2_CID_COLORFX:
 580                 ret = fimc_set_color_effect(ctx, ctrl->val);
 581                 if (ret)
 582                         return ret;
 583                 break;
 584         }
 585
 586         ctx->state |= FIMC_PARAMS;
 587         set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
 588         return 0;
 589 }
 590
 591 static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
 592 {
 593         struct fimc_ctx *ctx = ctrl_to_ctx(ctrl);
 594         unsigned long flags;
 595         int ret;
 596
 597         spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
 598         ret = __fimc_s_ctrl(ctx, ctrl);
 599         spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
 600
 601         return ret;
 602 }
 603
 604 static const struct v4l2_ctrl_ops fimc_ctrl_ops = {
 605         .s_ctrl = fimc_s_ctrl,
 606 };
 607
 608 int fimc_ctrls_create(struct fimc_ctx *ctx)
 609 {
 610         unsigned int max_alpha = fimc_get_alpha_mask(ctx->d_frame.fmt);
 611         struct fimc_ctrls *ctrls = &ctx->ctrls;
 612         struct v4l2_ctrl_handler *handler = &ctrls->handler;
 613
 614         if (ctx->ctrls.ready)
 615                 return 0;
 616
 617         v4l2_ctrl_handler_init(handler, 6);
 618
 619         ctrls->rotate = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 620                                         V4L2_CID_ROTATE, 0, 270, 90, 0);
 621         ctrls->hflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 622                                         V4L2_CID_HFLIP, 0, 1, 1, 0);
 623         ctrls->vflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 624                                         V4L2_CID_VFLIP, 0, 1, 1, 0);
 625
 626         if (ctx->fimc_dev->drv_data->alpha_color)
 627                 ctrls->alpha = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 628                                         V4L2_CID_ALPHA_COMPONENT,
 629                                         0, max_alpha, 1, 0);
 630         else
 631                 ctrls->alpha = NULL;
 632
 633         ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, &fimc_ctrl_ops,
 634                                 V4L2_CID_COLORFX, V4L2_COLORFX_SET_CBCR,
 635                                 ~0x983f, V4L2_COLORFX_NONE);
 636
 637         ctrls->colorfx_cbcr = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 638                                 V4L2_CID_COLORFX_CBCR, 0, 0xffff, 1, 0);
 639
 640         ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS;
 641
 642         if (!handler->error) {
 643                 v4l2_ctrl_cluster(2, &ctrls->colorfx);
 644                 ctrls->ready = true;
 645         }
 646
 647         return handler->error;
 648 }
 649
 650 void fimc_ctrls_delete(struct fimc_ctx *ctx)
 651 {
 652         struct fimc_ctrls *ctrls = &ctx->ctrls;
 653
 654         if (ctrls->ready) {
 655                 v4l2_ctrl_handler_free(&ctrls->handler);
 656                 ctrls->ready = false;
 657                 ctrls->alpha = NULL;
 658         }
 659 }
 660
 661 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active)
 662 {
 663         unsigned int has_alpha = ctx->d_frame.fmt->flags & FMT_HAS_ALPHA;
 664         struct fimc_ctrls *ctrls = &ctx->ctrls;
 665
 666         if (!ctrls->ready)
 667                 return;
 668
 669         mutex_lock(ctrls->handler.lock);
 670         v4l2_ctrl_activate(ctrls->rotate, active);
 671         v4l2_ctrl_activate(ctrls->hflip, active);
 672         v4l2_ctrl_activate(ctrls->vflip, active);
 673         v4l2_ctrl_activate(ctrls->colorfx, active);
 674         if (ctrls->alpha)
 675                 v4l2_ctrl_activate(ctrls->alpha, active && has_alpha);
 676
 677         if (active) {
 678                 fimc_set_color_effect(ctx, ctrls->colorfx->cur.val);
 679                 ctx->rotation = ctrls->rotate->val;
 680                 ctx->hflip    = ctrls->hflip->val;
 681                 ctx->vflip    = ctrls->vflip->val;
 682         } else {
 683                 ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS;
 684                 ctx->rotation = 0;
 685                 ctx->hflip    = 0;
 686                 ctx->vflip    = 0;
 687         }
 688         mutex_unlock(ctrls->handler.lock);
 689 }
 690
 691 /* Update maximum value of the alpha color control */
 692 void fimc_alpha_ctrl_update(struct fimc_ctx *ctx)
 693 {
 694         struct fimc_dev *fimc = ctx->fimc_dev;
 695         struct v4l2_ctrl *ctrl = ctx->ctrls.alpha;
 696
 697         if (ctrl == NULL || !fimc->drv_data->alpha_color)
 698                 return;
 699
 700         v4l2_ctrl_lock(ctrl);
 701         ctrl->maximum = fimc_get_alpha_mask(ctx->d_frame.fmt);
 702
 703         if (ctrl->cur.val > ctrl->maximum)
 704                 ctrl->cur.val = ctrl->maximum;
 705
 706         v4l2_ctrl_unlock(ctrl);
 707 }
 708
 709 void __fimc_get_format(struct fimc_frame *frame, struct v4l2_format *f)
 710 {
 711         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
 712         int i;
 713
 714         pixm->width = frame->o_width;
 715         pixm->height = frame->o_height;
 716         pixm->field = V4L2_FIELD_NONE;
 717         pixm->pixelformat = frame->fmt->fourcc;
 718         pixm->colorspace = V4L2_COLORSPACE_JPEG;
 719         pixm->num_planes = frame->fmt->memplanes;
 720
 721         for (i = 0; i < pixm->num_planes; ++i) {
 722                 pixm->plane_fmt[i].bytesperline = frame->bytesperline[i];
 723                 pixm->plane_fmt[i].sizeimage = frame->payload[i];
 724         }
 725 }
 726
 727 /**
 728  * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane
 729  * @fmt: fimc pixel format description (input)
 730  * @width: requested pixel width
 731  * @height: requested pixel height
 732  * @pix: multi-plane format to adjust
 733  */
 734 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
 735                                struct v4l2_pix_format_mplane *pix)
 736 {
 737         u32 bytesperline = 0;
 738         int i;
 739
 740         pix->colorspace = V4L2_COLORSPACE_JPEG;
 741         pix->field = V4L2_FIELD_NONE;
 742         pix->num_planes = fmt->memplanes;
 743         pix->pixelformat = fmt->fourcc;
 744         pix->height = height;
 745         pix->width = width;
 746
 747         for (i = 0; i < pix->num_planes; ++i) {
 748                 struct v4l2_plane_pix_format *plane_fmt = &pix->plane_fmt[i];
 749                 u32 bpl = plane_fmt->bytesperline;
 750
 751                 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
 752                         bpl = pix->width; /* Planar */
 753
 754                 if (fmt->colplanes == 1 && /* Packed */
 755                     (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
 756                         bpl = (pix->width * fmt->depth[0]) / 8;
 757                 /*
 758                  * Currently bytesperline for each plane is same, except
 759                  * V4L2_PIX_FMT_YUV420M format. This calculation may need
 760                  * to be changed when other multi-planar formats are added
 761                  * to the fimc_formats[] array.
 762                  */
 763                 if (i == 0)
 764                         bytesperline = bpl;
 765                 else if (i == 1 && fmt->memplanes == 3)
 766                         bytesperline /= 2;
 767
 768                 plane_fmt->bytesperline = bytesperline;
 769                 plane_fmt->sizeimage = max((pix->width * pix->height *
 770                                    fmt->depth[i]) / 8, plane_fmt->sizeimage);
 771         }
 772 }
 773
 774 /**
 775  * fimc_find_format - lookup fimc color format by fourcc or media bus format
 776  * @pixelformat: fourcc to match, ignored if null
 777  * @mbus_code: media bus code to match, ignored if null
 778  * @mask: the color flags to match
 779  * @index: offset in the fimc_formats array, ignored if negative
 780  */
 781 struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
 782                                   unsigned int mask, int index)
 783 {
 784         struct fimc_fmt *fmt, *def_fmt = NULL;
 785         unsigned int i;
 786         int id = 0;
 787
 788         if (index >= (int)ARRAY_SIZE(fimc_formats))
 789                 return NULL;
 790
 791         for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
 792                 fmt = &fimc_formats[i];
 793                 if (!(fmt->flags & mask))
 794                         continue;
 795                 if (pixelformat && fmt->fourcc == *pixelformat)
 796                         return fmt;
 797                 if (mbus_code && fmt->mbus_code == *mbus_code)
 798                         return fmt;
 799                 if (index == id)
 800                         def_fmt = fmt;
 801                 id++;
 802         }
 803         return def_fmt;
 804 }
 805
 806 static void fimc_clk_put(struct fimc_dev *fimc)
 807 {
 808         int i;
 809         for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
 810                 if (IS_ERR(fimc->clock[i]))
 811                         continue;
 812                 clk_unprepare(fimc->clock[i]);
 813                 clk_put(fimc->clock[i]);
 814                 fimc->clock[i] = ERR_PTR(-EINVAL);
 815         }
 816 }
 817
 818 static int fimc_clk_get(struct fimc_dev *fimc)
 819 {
 820         int i, ret;
 821
 822         for (i = 0; i < MAX_FIMC_CLOCKS; i++)
 823                 fimc->clock[i] = ERR_PTR(-EINVAL);
 824
 825         for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
 826                 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
 827                 if (IS_ERR(fimc->clock[i])) {
 828                         ret = PTR_ERR(fimc->clock[i]);
 829                         goto err;
 830                 }
 831                 ret = clk_prepare(fimc->clock[i]);
 832                 if (ret < 0) {
 833                         clk_put(fimc->clock[i]);
 834                         fimc->clock[i] = ERR_PTR(-EINVAL);
 835                         goto err;
 836                 }
 837         }
 838         return 0;
 839 err:
 840         fimc_clk_put(fimc);
 841         dev_err(&fimc->pdev->dev, "failed to get clock: %s\n",
 842                 fimc_clocks[i]);
 843         return -ENXIO;
 844 }
 845
 846 static int fimc_m2m_suspend(struct fimc_dev *fimc)
 847 {
 848         unsigned long flags;
 849         int timeout;
 850
 851         spin_lock_irqsave(&fimc->slock, flags);
 852         if (!fimc_m2m_pending(fimc)) {
 853                 spin_unlock_irqrestore(&fimc->slock, flags);
 854                 return 0;
 855         }
 856         clear_bit(ST_M2M_SUSPENDED, &fimc->state);
 857         set_bit(ST_M2M_SUSPENDING, &fimc->state);
 858         spin_unlock_irqrestore(&fimc->slock, flags);
 859
 860         timeout = wait_event_timeout(fimc->irq_queue,
 861                              test_bit(ST_M2M_SUSPENDED, &fimc->state),
 862                              FIMC_SHUTDOWN_TIMEOUT);
 863
 864         clear_bit(ST_M2M_SUSPENDING, &fimc->state);
 865         return timeout == 0 ? -EAGAIN : 0;
 866 }
 867
 868 static int fimc_m2m_resume(struct fimc_dev *fimc)
 869 {
 870         struct fimc_ctx *ctx;
 871         unsigned long flags;
 872
 873         spin_lock_irqsave(&fimc->slock, flags);
 874         /* Clear for full H/W setup in first run after resume */
 875         ctx = fimc->m2m.ctx;
 876         fimc->m2m.ctx = NULL;
 877         spin_unlock_irqrestore(&fimc->slock, flags);
 878
 879         if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state))
 880                 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
 881
 882         return 0;
 883 }
 884
 885 static const struct of_device_id fimc_of_match[];
 886
 887 static int fimc_parse_dt(struct fimc_dev *fimc, u32 *clk_freq)
 888 {
 889         struct device *dev = &fimc->pdev->dev;
 890         struct device_node *node = dev->of_node;
 891         const struct of_device_id *of_id;
 892         struct fimc_variant *v;
 893         struct fimc_pix_limit *lim;
 894         u32 args[FIMC_PIX_LIMITS_MAX];
 895         int ret;
 896
 897         if (of_property_read_bool(node, "samsung,lcd-wb"))
 898                 return -ENODEV;
 899
 900         v = devm_kzalloc(dev, sizeof(*v) + sizeof(*lim), GFP_KERNEL);
 901         if (!v)
 902                 return -ENOMEM;
 903
 904         of_id = of_match_node(fimc_of_match, node);
 905         if (!of_id)
 906                 return -EINVAL;
 907         fimc->drv_data = of_id->data;
 908         ret = of_property_read_u32_array(node, "samsung,pix-limits",
 909                                          args, FIMC_PIX_LIMITS_MAX);
 910         if (ret < 0)
 911                 return ret;
 912
 913         lim = (struct fimc_pix_limit *)&v[1];
 914
 915         lim->scaler_en_w = args[0];
 916         lim->scaler_dis_w = args[1];
 917         lim->out_rot_en_w = args[2];
 918         lim->out_rot_dis_w = args[3];
 919         v->pix_limit = lim;
 920
 921         ret = of_property_read_u32_array(node, "samsung,min-pix-sizes",
 922                                                                 args, 2);
 923         v->min_inp_pixsize = ret ? FIMC_DEF_MIN_SIZE : args[0];
 924         v->min_out_pixsize = ret ? FIMC_DEF_MIN_SIZE : args[1];
 925         ret = of_property_read_u32_array(node, "samsung,min-pix-alignment",
 926                                                                 args, 2);
 927         v->min_vsize_align = ret ? FIMC_DEF_HEIGHT_ALIGN : args[0];
 928         v->hor_offs_align = ret ? FIMC_DEF_HOR_OFFS_ALIGN : args[1];
 929
 930         ret = of_property_read_u32(node, "samsung,rotators", &args[1]);
 931         v->has_inp_rot = ret ? 1 : args[1] & 0x01;
 932         v->has_out_rot = ret ? 1 : args[1] & 0x10;
 933         v->has_mainscaler_ext = of_property_read_bool(node,
 934                                         "samsung,mainscaler-ext");
 935
 936         v->has_isp_wb = of_property_read_bool(node, "samsung,isp-wb");
 937         v->has_cam_if = of_property_read_bool(node, "samsung,cam-if");
 938         of_property_read_u32(node, "clock-frequency", clk_freq);
 939         fimc->id = of_alias_get_id(node, "fimc");
 940
 941         fimc->variant = v;
 942         return 0;
 943 }
 944
 945 static int fimc_probe(struct platform_device *pdev)
 946 {
 947         struct device *dev = &pdev->dev;
 948         u32 lclk_freq = 0;
 949         struct fimc_dev *fimc;
 950         struct resource *res;
 951         int ret = 0;
 952
 953         fimc = devm_kzalloc(dev, sizeof(*fimc), GFP_KERNEL);
 954         if (!fimc)
 955                 return -ENOMEM;
 956
 957         fimc->pdev = pdev;
 958
 959         if (dev->of_node) {
 960                 ret = fimc_parse_dt(fimc, &lclk_freq);
 961                 if (ret < 0)
 962                         return ret;
 963         } else {
 964                 fimc->drv_data = fimc_get_drvdata(pdev);
 965                 fimc->id = pdev->id;
 966         }
 967         if (!fimc->drv_data || fimc->id >= fimc->drv_data->num_entities ||
 968             fimc->id < 0) {
 969                 dev_err(dev, "Invalid driver data or device id (%d)\n",
 970                         fimc->id);
 971                 return -EINVAL;
 972         }
 973         if (!dev->of_node)
 974                 fimc->variant = fimc->drv_data->variant[fimc->id];
 975
 976         init_waitqueue_head(&fimc->irq_queue);
 977         spin_lock_init(&fimc->slock);
 978         mutex_init(&fimc->lock);
 979
 980         fimc->sysreg = fimc_get_sysreg_regmap(dev->of_node);
 981         if (IS_ERR(fimc->sysreg))
 982                 return PTR_ERR(fimc->sysreg);
 983
 984         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 985         fimc->regs = devm_ioremap_resource(dev, res);
 986         if (IS_ERR(fimc->regs))
 987                 return PTR_ERR(fimc->regs);
 988
 989         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 990         if (res == NULL) {
 991                 dev_err(dev, "Failed to get IRQ resource\n");
 992                 return -ENXIO;
 993         }
 994
 995         ret = fimc_clk_get(fimc);
 996         if (ret)
 997                 return ret;
 998
 999         if (lclk_freq == 0)
1000                 lclk_freq = fimc->drv_data->lclk_frequency;
1001
1002         ret = clk_set_rate(fimc->clock[CLK_BUS], lclk_freq);
1003         if (ret < 0)
1004                 return ret;
1005
1006         ret = clk_enable(fimc->clock[CLK_BUS]);
1007         if (ret < 0)
1008                 return ret;
1009
1010         ret = devm_request_irq(dev, res->start, fimc_irq_handler,
1011                                0, dev_name(dev), fimc);
1012         if (ret) {
1013                 dev_err(dev, "failed to install irq (%d)\n", ret);
1014                 goto err_clk;
1015         }
1016
1017         ret = fimc_initialize_capture_subdev(fimc);
1018         if (ret)
1019                 goto err_clk;
1020
1021         platform_set_drvdata(pdev, fimc);
1022         pm_runtime_enable(dev);
1023         ret = pm_runtime_get_sync(dev);
1024         if (ret < 0)
1025                 goto err_sd;
1026         /* Initialize contiguous memory allocator */
1027         fimc->alloc_ctx = vb2_dma_contig_init_ctx(dev);
1028         if (IS_ERR(fimc->alloc_ctx)) {
1029                 ret = PTR_ERR(fimc->alloc_ctx);
1030                 goto err_pm;
1031         }
1032
1033         dev_dbg(dev, "FIMC.%d registered successfully\n", fimc->id);
1034
1035         pm_runtime_put(dev);
1036         return 0;
1037 err_pm:
1038         pm_runtime_put(dev);
1039 err_sd:
1040         fimc_unregister_capture_subdev(fimc);
1041 err_clk:
1042         clk_disable(fimc->clock[CLK_BUS]);
1043         fimc_clk_put(fimc);
1044         return ret;
1045 }
1046
1047 static int fimc_runtime_resume(struct device *dev)
1048 {
1049         struct fimc_dev *fimc = dev_get_drvdata(dev);
1050
1051         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1052
1053         /* Enable clocks and perform basic initalization */
1054         clk_enable(fimc->clock[CLK_GATE]);
1055         fimc_hw_reset(fimc);
1056
1057         /* Resume the capture or mem-to-mem device */
1058         if (fimc_capture_busy(fimc))
1059                 return fimc_capture_resume(fimc);
1060
1061         return fimc_m2m_resume(fimc);
1062 }
1063
1064 static int fimc_runtime_suspend(struct device *dev)
1065 {
1066         struct fimc_dev *fimc = dev_get_drvdata(dev);
1067         int ret = 0;
1068
1069         if (fimc_capture_busy(fimc))
1070                 ret = fimc_capture_suspend(fimc);
1071         else
1072                 ret = fimc_m2m_suspend(fimc);
1073         if (!ret)
1074                 clk_disable(fimc->clock[CLK_GATE]);
1075
1076         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1077         return ret;
1078 }
1079
1080 #ifdef CONFIG_PM_SLEEP
1081 static int fimc_resume(struct device *dev)
1082 {
1083         struct fimc_dev *fimc = dev_get_drvdata(dev);
1084         unsigned long flags;
1085
1086         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1087
1088         /* Do not resume if the device was idle before system suspend */
1089         spin_lock_irqsave(&fimc->slock, flags);
1090         if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1091             (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) {
1092                 spin_unlock_irqrestore(&fimc->slock, flags);
1093                 return 0;
1094         }
1095         fimc_hw_reset(fimc);
1096         spin_unlock_irqrestore(&fimc->slock, flags);
1097
1098         if (fimc_capture_busy(fimc))
1099                 return fimc_capture_resume(fimc);
1100
1101         return fimc_m2m_resume(fimc);
1102 }
1103
1104 static int fimc_suspend(struct device *dev)
1105 {
1106         struct fimc_dev *fimc = dev_get_drvdata(dev);
1107
1108         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1109
1110         if (test_and_set_bit(ST_LPM, &fimc->state))
1111                 return 0;
1112         if (fimc_capture_busy(fimc))
1113                 return fimc_capture_suspend(fimc);
1114
1115         return fimc_m2m_suspend(fimc);
1116 }
1117 #endif /* CONFIG_PM_SLEEP */
1118
1119 static int fimc_remove(struct platform_device *pdev)
1120 {
1121         struct fimc_dev *fimc = platform_get_drvdata(pdev);
1122
1123         pm_runtime_disable(&pdev->dev);
1124         pm_runtime_set_suspended(&pdev->dev);
1125
1126         fimc_unregister_capture_subdev(fimc);
1127         vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1128
1129         clk_disable(fimc->clock[CLK_BUS]);
1130         fimc_clk_put(fimc);
1131
1132         dev_info(&pdev->dev, "driver unloaded\n");
1133         return 0;
1134 }
1135
1136 /* Image pixel limits, similar across several FIMC HW revisions. */
1137 static const struct fimc_pix_limit s5p_pix_limit[4] = {
1138         [0] = {
1139                 .scaler_en_w    = 3264,
1140                 .scaler_dis_w   = 8192,
1141                 .out_rot_en_w   = 1920,
1142                 .out_rot_dis_w  = 4224,
1143         },
1144         [1] = {
1145                 .scaler_en_w    = 4224,
1146                 .scaler_dis_w   = 8192,
1147                 .out_rot_en_w   = 1920,
1148                 .out_rot_dis_w  = 4224,
1149         },
1150         [2] = {
1151                 .scaler_en_w    = 1920,
1152                 .scaler_dis_w   = 8192,
1153                 .out_rot_en_w   = 1280,
1154                 .out_rot_dis_w  = 1920,
1155         },
1156 };
1157
1158 static const struct fimc_variant fimc0_variant_s5p = {
1159         .has_inp_rot     = 1,
1160         .has_out_rot     = 1,
1161         .has_cam_if      = 1,
1162         .min_inp_pixsize = 16,
1163         .min_out_pixsize = 16,
1164         .hor_offs_align  = 8,
1165         .min_vsize_align = 16,
1166         .pix_limit       = &s5p_pix_limit[0],
1167 };
1168
1169 static const struct fimc_variant fimc2_variant_s5p = {
1170         .has_cam_if      = 1,
1171         .min_inp_pixsize = 16,
1172         .min_out_pixsize = 16,
1173         .hor_offs_align  = 8,
1174         .min_vsize_align = 16,
1175         .pix_limit       = &s5p_pix_limit[1],
1176 };
1177
1178 static const struct fimc_variant fimc0_variant_s5pv210 = {
1179         .has_inp_rot     = 1,
1180         .has_out_rot     = 1,
1181         .has_cam_if      = 1,
1182         .min_inp_pixsize = 16,
1183         .min_out_pixsize = 16,
1184         .hor_offs_align  = 8,
1185         .min_vsize_align = 16,
1186         .pix_limit       = &s5p_pix_limit[1],
1187 };
1188
1189 static const struct fimc_variant fimc1_variant_s5pv210 = {
1190         .has_inp_rot     = 1,
1191         .has_out_rot     = 1,
1192         .has_cam_if      = 1,
1193         .has_mainscaler_ext = 1,
1194         .min_inp_pixsize = 16,
1195         .min_out_pixsize = 16,
1196         .hor_offs_align  = 1,
1197         .min_vsize_align = 1,
1198         .pix_limit       = &s5p_pix_limit[2],
1199 };
1200
1201 static const struct fimc_variant fimc2_variant_s5pv210 = {
1202         .has_cam_if      = 1,
1203         .min_inp_pixsize = 16,
1204         .min_out_pixsize = 16,
1205         .hor_offs_align  = 8,
1206         .min_vsize_align = 16,
1207         .pix_limit       = &s5p_pix_limit[2],
1208 };
1209
1210 /* S5PC100 */
1211 static const struct fimc_drvdata fimc_drvdata_s5p = {
1212         .variant = {
1213                 [0] = &fimc0_variant_s5p,
1214                 [1] = &fimc0_variant_s5p,
1215                 [2] = &fimc2_variant_s5p,
1216         },
1217         .num_entities   = 3,
1218         .lclk_frequency = 133000000UL,
1219         .out_buf_count  = 4,
1220 };
1221
1222 /* S5PV210, S5PC110 */
1223 static const struct fimc_drvdata fimc_drvdata_s5pv210 = {
1224         .variant = {
1225                 [0] = &fimc0_variant_s5pv210,
1226                 [1] = &fimc1_variant_s5pv210,
1227                 [2] = &fimc2_variant_s5pv210,
1228         },
1229         .num_entities   = 3,
1230         .lclk_frequency = 166000000UL,
1231         .out_buf_count  = 4,
1232         .dma_pix_hoff   = 1,
1233 };
1234
1235 /* EXYNOS4210, S5PV310, S5PC210 */
1236 static const struct fimc_drvdata fimc_drvdata_exynos4210 = {
1237         .num_entities   = 4,
1238         .lclk_frequency = 166000000UL,
1239         .dma_pix_hoff   = 1,
1240         .cistatus2      = 1,
1241         .alpha_color    = 1,
1242         .out_buf_count  = 32,
1243 };
1244
1245 /* EXYNOS4212, EXYNOS4412 */
1246 static const struct fimc_drvdata fimc_drvdata_exynos4x12 = {
1247         .num_entities   = 4,
1248         .lclk_frequency = 166000000UL,
1249         .dma_pix_hoff   = 1,
1250         .cistatus2      = 1,
1251         .alpha_color    = 1,
1252         .out_buf_count  = 32,
1253 };
1254
1255 static const struct platform_device_id fimc_driver_ids[] = {
1256         {
1257                 .name           = "s5p-fimc",
1258                 .driver_data    = (unsigned long)&fimc_drvdata_s5p,
1259         }, {
1260                 .name           = "s5pv210-fimc",
1261                 .driver_data    = (unsigned long)&fimc_drvdata_s5pv210,
1262         }, {
1263                 .name           = "exynos4-fimc",
1264                 .driver_data    = (unsigned long)&fimc_drvdata_exynos4210,
1265         }, {
1266                 .name           = "exynos4x12-fimc",
1267                 .driver_data    = (unsigned long)&fimc_drvdata_exynos4x12,
1268         },
1269         { },
1270 };
1271
1272 static const struct of_device_id fimc_of_match[] = {
1273         {
1274                 .compatible = "samsung,s5pv210-fimc",
1275                 .data = &fimc_drvdata_s5pv210,
1276         }, {
1277                 .compatible = "samsung,exynos4210-fimc",
1278                 .data = &fimc_drvdata_exynos4210,
1279         }, {
1280                 .compatible = "samsung,exynos4212-fimc",
1281                 .data = &fimc_drvdata_exynos4x12,
1282         },
1283         { /* sentinel */ },
1284 };
1285
1286 static const struct dev_pm_ops fimc_pm_ops = {
1287         SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1288         SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1289 };
1290
1291 static struct platform_driver fimc_driver = {
1292         .probe          = fimc_probe,
1293         .remove         = fimc_remove,
1294         .id_table       = fimc_driver_ids,
1295         .driver = {
1296                 .of_match_table = fimc_of_match,
1297                 .name           = FIMC_DRIVER_NAME,
1298                 .owner          = THIS_MODULE,
1299                 .pm             = &fimc_pm_ops,
1300         }
1301 };
1302
1303 int __init fimc_register_driver(void)
1304 {
1305         return platform_driver_register(&fimc_driver);
1306 }
1307
1308 void __exit fimc_unregister_driver(void)
1309 {
1310         platform_driver_unregister(&fimc_driver);
1311 }