drivers/media/i2c/ov6650.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * V4L2 subdevice driver for OmniVision OV6650 Camera Sensor
   4  *
   5  * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
   6  *
   7  * Based on OmniVision OV96xx Camera Driver
   8  * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
   9  *
  10  * Based on ov772x camera driver:
  11  * Copyright (C) 2008 Renesas Solutions Corp.
  12  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  13  *
  14  * Based on ov7670 and soc_camera_platform driver,
  15  * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
  16  * Copyright (C) 2008 Magnus Damm
  17  * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  18  *
  19  * Hardware specific bits initially based on former work by Matt Callow
  20  * drivers/media/video/omap/sensor_ov6650.c
  21  * Copyright (C) 2006 Matt Callow
  22  */
  23
  24 #include <linux/bitops.h>
  25 #include <linux/delay.h>
  26 #include <linux/i2c.h>
  27 #include <linux/slab.h>
  28 #include <linux/v4l2-mediabus.h>
  29 #include <linux/module.h>
  30
  31 #include <media/v4l2-clk.h>
  32 #include <media/v4l2-ctrls.h>
  33 #include <media/v4l2-device.h>
  34
  35 /* Register definitions */
  36 #define REG_GAIN                0x00    /* range 00 - 3F */
  37 #define REG_BLUE                0x01
  38 #define REG_RED                 0x02
  39 #define REG_SAT                 0x03    /* [7:4] saturation [0:3] reserved */
  40 #define REG_HUE                 0x04    /* [7:6] rsrvd [5] hue en [4:0] hue */
  41
  42 #define REG_BRT                 0x06
  43
  44 #define REG_PIDH                0x0a
  45 #define REG_PIDL                0x0b
  46
  47 #define REG_AECH                0x10
  48 #define REG_CLKRC               0x11    /* Data Format and Internal Clock */
  49                                         /* [7:6] Input system clock (MHz)*/
  50                                         /*   00=8, 01=12, 10=16, 11=24 */
  51                                         /* [5:0]: Internal Clock Pre-Scaler */
  52 #define REG_COMA                0x12    /* [7] Reset */
  53 #define REG_COMB                0x13
  54 #define REG_COMC                0x14
  55 #define REG_COMD                0x15
  56 #define REG_COML                0x16
  57 #define REG_HSTRT               0x17
  58 #define REG_HSTOP               0x18
  59 #define REG_VSTRT               0x19
  60 #define REG_VSTOP               0x1a
  61 #define REG_PSHFT               0x1b
  62 #define REG_MIDH                0x1c
  63 #define REG_MIDL                0x1d
  64 #define REG_HSYNS               0x1e
  65 #define REG_HSYNE               0x1f
  66 #define REG_COME                0x20
  67 #define REG_YOFF                0x21
  68 #define REG_UOFF                0x22
  69 #define REG_VOFF                0x23
  70 #define REG_AEW                 0x24
  71 #define REG_AEB                 0x25
  72 #define REG_COMF                0x26
  73 #define REG_COMG                0x27
  74 #define REG_COMH                0x28
  75 #define REG_COMI                0x29
  76
  77 #define REG_FRARL               0x2b
  78 #define REG_COMJ                0x2c
  79 #define REG_COMK                0x2d
  80 #define REG_AVGY                0x2e
  81 #define REG_REF0                0x2f
  82 #define REG_REF1                0x30
  83 #define REG_REF2                0x31
  84 #define REG_FRAJH               0x32
  85 #define REG_FRAJL               0x33
  86 #define REG_FACT                0x34
  87 #define REG_L1AEC               0x35
  88 #define REG_AVGU                0x36
  89 #define REG_AVGV                0x37
  90
  91 #define REG_SPCB                0x60
  92 #define REG_SPCC                0x61
  93 #define REG_GAM1                0x62
  94 #define REG_GAM2                0x63
  95 #define REG_GAM3                0x64
  96 #define REG_SPCD                0x65
  97
  98 #define REG_SPCE                0x68
  99 #define REG_ADCL                0x69
 100
 101 #define REG_RMCO                0x6c
 102 #define REG_GMCO                0x6d
 103 #define REG_BMCO                0x6e
 104
 105
 106 /* Register bits, values, etc. */
 107 #define OV6650_PIDH             0x66    /* high byte of product ID number */
 108 #define OV6650_PIDL             0x50    /* low byte of product ID number */
 109 #define OV6650_MIDH             0x7F    /* high byte of mfg ID */
 110 #define OV6650_MIDL             0xA2    /* low byte of mfg ID */
 111
 112 #define DEF_GAIN                0x00
 113 #define DEF_BLUE                0x80
 114 #define DEF_RED                 0x80
 115
 116 #define SAT_SHIFT               4
 117 #define SAT_MASK                (0xf << SAT_SHIFT)
 118 #define SET_SAT(x)              (((x) << SAT_SHIFT) & SAT_MASK)
 119
 120 #define HUE_EN                  BIT(5)
 121 #define HUE_MASK                0x1f
 122 #define DEF_HUE                 0x10
 123 #define SET_HUE(x)              (HUE_EN | ((x) & HUE_MASK))
 124
 125 #define DEF_AECH                0x4D
 126
 127 #define CLKRC_8MHz              0x00
 128 #define CLKRC_12MHz             0x40
 129 #define CLKRC_16MHz             0x80
 130 #define CLKRC_24MHz             0xc0
 131 #define CLKRC_DIV_MASK          0x3f
 132 #define GET_CLKRC_DIV(x)        (((x) & CLKRC_DIV_MASK) + 1)
 133 #define DEF_CLKRC               0x00
 134
 135 #define COMA_RESET              BIT(7)
 136 #define COMA_QCIF               BIT(5)
 137 #define COMA_RAW_RGB            BIT(4)
 138 #define COMA_RGB                BIT(3)
 139 #define COMA_BW                 BIT(2)
 140 #define COMA_WORD_SWAP          BIT(1)
 141 #define COMA_BYTE_SWAP          BIT(0)
 142 #define DEF_COMA                0x00
 143
 144 #define COMB_FLIP_V             BIT(7)
 145 #define COMB_FLIP_H             BIT(5)
 146 #define COMB_BAND_FILTER        BIT(4)
 147 #define COMB_AWB                BIT(2)
 148 #define COMB_AGC                BIT(1)
 149 #define COMB_AEC                BIT(0)
 150 #define DEF_COMB                0x5f
 151
 152 #define COML_ONE_CHANNEL        BIT(7)
 153
 154 #define DEF_HSTRT               0x24
 155 #define DEF_HSTOP               0xd4
 156 #define DEF_VSTRT               0x04
 157 #define DEF_VSTOP               0x94
 158
 159 #define COMF_HREF_LOW           BIT(4)
 160
 161 #define COMJ_PCLK_RISING        BIT(4)
 162 #define COMJ_VSYNC_HIGH         BIT(0)
 163
 164 /* supported resolutions */
 165 #define W_QCIF                  (DEF_HSTOP - DEF_HSTRT)
 166 #define W_CIF                   (W_QCIF << 1)
 167 #define H_QCIF                  (DEF_VSTOP - DEF_VSTRT)
 168 #define H_CIF                   (H_QCIF << 1)
 169
 170 #define FRAME_RATE_MAX          30
 171
 172
 173 struct ov6650_reg {
 174         u8      reg;
 175         u8      val;
 176 };
 177
 178 struct ov6650 {
 179         struct v4l2_subdev      subdev;
 180         struct v4l2_ctrl_handler hdl;
 181         struct {
 182                 /* exposure/autoexposure cluster */
 183                 struct v4l2_ctrl *autoexposure;
 184                 struct v4l2_ctrl *exposure;
 185         };
 186         struct {
 187                 /* gain/autogain cluster */
 188                 struct v4l2_ctrl *autogain;
 189                 struct v4l2_ctrl *gain;
 190         };
 191         struct {
 192                 /* blue/red/autowhitebalance cluster */
 193                 struct v4l2_ctrl *autowb;
 194                 struct v4l2_ctrl *blue;
 195                 struct v4l2_ctrl *red;
 196         };
 197         struct v4l2_clk         *clk;
 198         bool                    half_scale;     /* scale down output by 2 */
 199         struct v4l2_rect        rect;           /* sensor cropping window */
 200         struct v4l2_fract       tpf;            /* as requested with s_frame_interval */
 201         u32 code;
 202 };
 203
 204 struct ov6650_xclk {
 205         unsigned long   rate;
 206         u8              clkrc;
 207 };
 208
 209 static const struct ov6650_xclk ov6650_xclk[] = {
 210 {
 211         .rate   = 8000000,
 212         .clkrc  = CLKRC_8MHz,
 213 },
 214 {
 215         .rate   = 12000000,
 216         .clkrc  = CLKRC_12MHz,
 217 },
 218 {
 219         .rate   = 16000000,
 220         .clkrc  = CLKRC_16MHz,
 221 },
 222 {
 223         .rate   = 24000000,
 224         .clkrc  = CLKRC_24MHz,
 225 },
 226 };
 227
 228 static u32 ov6650_codes[] = {
 229         MEDIA_BUS_FMT_YUYV8_2X8,
 230         MEDIA_BUS_FMT_UYVY8_2X8,
 231         MEDIA_BUS_FMT_YVYU8_2X8,
 232         MEDIA_BUS_FMT_VYUY8_2X8,
 233         MEDIA_BUS_FMT_SBGGR8_1X8,
 234         MEDIA_BUS_FMT_Y8_1X8,
 235 };
 236
 237 static const struct v4l2_mbus_framefmt ov6650_def_fmt = {
 238         .width          = W_CIF,
 239         .height         = H_CIF,
 240         .code           = MEDIA_BUS_FMT_SBGGR8_1X8,
 241         .colorspace     = V4L2_COLORSPACE_SRGB,
 242         .field          = V4L2_FIELD_NONE,
 243         .ycbcr_enc      = V4L2_YCBCR_ENC_DEFAULT,
 244         .quantization   = V4L2_QUANTIZATION_DEFAULT,
 245         .xfer_func      = V4L2_XFER_FUNC_DEFAULT,
 246 };
 247
 248 /* read a register */
 249 static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
 250 {
 251         int ret;
 252         u8 data = reg;
 253         struct i2c_msg msg = {
 254                 .addr   = client->addr,
 255                 .flags  = 0,
 256                 .len    = 1,
 257                 .buf    = &data,
 258         };
 259
 260         ret = i2c_transfer(client->adapter, &msg, 1);
 261         if (ret < 0)
 262                 goto err;
 263
 264         msg.flags = I2C_M_RD;
 265         ret = i2c_transfer(client->adapter, &msg, 1);
 266         if (ret < 0)
 267                 goto err;
 268
 269         *val = data;
 270         return 0;
 271
 272 err:
 273         dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
 274         return ret;
 275 }
 276
 277 /* write a register */
 278 static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
 279 {
 280         int ret;
 281         unsigned char data[2] = { reg, val };
 282         struct i2c_msg msg = {
 283                 .addr   = client->addr,
 284                 .flags  = 0,
 285                 .len    = 2,
 286                 .buf    = data,
 287         };
 288
 289         ret = i2c_transfer(client->adapter, &msg, 1);
 290         udelay(100);
 291
 292         if (ret < 0) {
 293                 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
 294                 return ret;
 295         }
 296         return 0;
 297 }
 298
 299
 300 /* Read a register, alter its bits, write it back */
 301 static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
 302 {
 303         u8 val;
 304         int ret;
 305
 306         ret = ov6650_reg_read(client, reg, &val);
 307         if (ret) {
 308                 dev_err(&client->dev,
 309                         "[Read]-Modify-Write of register 0x%02x failed!\n",
 310                         reg);
 311                 return ret;
 312         }
 313
 314         val &= ~mask;
 315         val |= set;
 316
 317         ret = ov6650_reg_write(client, reg, val);
 318         if (ret)
 319                 dev_err(&client->dev,
 320                         "Read-Modify-[Write] of register 0x%02x failed!\n",
 321                         reg);
 322
 323         return ret;
 324 }
 325
 326 static struct ov6650 *to_ov6650(const struct i2c_client *client)
 327 {
 328         return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
 329 }
 330
 331 /* Start/Stop streaming from the device */
 332 static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
 333 {
 334         return 0;
 335 }
 336
 337 /* Get status of additional camera capabilities */
 338 static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
 339 {
 340         struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
 341         struct v4l2_subdev *sd = &priv->subdev;
 342         struct i2c_client *client = v4l2_get_subdevdata(sd);
 343         uint8_t reg, reg2;
 344         int ret;
 345
 346         switch (ctrl->id) {
 347         case V4L2_CID_AUTOGAIN:
 348                 ret = ov6650_reg_read(client, REG_GAIN, &reg);
 349                 if (!ret)
 350                         priv->gain->val = reg;
 351                 return ret;
 352         case V4L2_CID_AUTO_WHITE_BALANCE:
 353                 ret = ov6650_reg_read(client, REG_BLUE, &reg);
 354                 if (!ret)
 355                         ret = ov6650_reg_read(client, REG_RED, &reg2);
 356                 if (!ret) {
 357                         priv->blue->val = reg;
 358                         priv->red->val = reg2;
 359                 }
 360                 return ret;
 361         case V4L2_CID_EXPOSURE_AUTO:
 362                 ret = ov6650_reg_read(client, REG_AECH, &reg);
 363                 if (!ret)
 364                         priv->exposure->val = reg;
 365                 return ret;
 366         }
 367         return -EINVAL;
 368 }
 369
 370 /* Set status of additional camera capabilities */
 371 static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
 372 {
 373         struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
 374         struct v4l2_subdev *sd = &priv->subdev;
 375         struct i2c_client *client = v4l2_get_subdevdata(sd);
 376         int ret;
 377
 378         switch (ctrl->id) {
 379         case V4L2_CID_AUTOGAIN:
 380                 ret = ov6650_reg_rmw(client, REG_COMB,
 381                                 ctrl->val ? COMB_AGC : 0, COMB_AGC);
 382                 if (!ret && !ctrl->val)
 383                         ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
 384                 return ret;
 385         case V4L2_CID_AUTO_WHITE_BALANCE:
 386                 ret = ov6650_reg_rmw(client, REG_COMB,
 387                                 ctrl->val ? COMB_AWB : 0, COMB_AWB);
 388                 if (!ret && !ctrl->val) {
 389                         ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
 390                         if (!ret)
 391                                 ret = ov6650_reg_write(client, REG_RED,
 392                                                         priv->red->val);
 393                 }
 394                 return ret;
 395         case V4L2_CID_SATURATION:
 396                 return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
 397                                 SAT_MASK);
 398         case V4L2_CID_HUE:
 399                 return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
 400                                 HUE_MASK);
 401         case V4L2_CID_BRIGHTNESS:
 402                 return ov6650_reg_write(client, REG_BRT, ctrl->val);
 403         case V4L2_CID_EXPOSURE_AUTO:
 404                 ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val ==
 405                                 V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC);
 406                 if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
 407                         ret = ov6650_reg_write(client, REG_AECH,
 408                                                 priv->exposure->val);
 409                 return ret;
 410         case V4L2_CID_GAMMA:
 411                 return ov6650_reg_write(client, REG_GAM1, ctrl->val);
 412         case V4L2_CID_VFLIP:
 413                 return ov6650_reg_rmw(client, REG_COMB,
 414                                 ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
 415         case V4L2_CID_HFLIP:
 416                 return ov6650_reg_rmw(client, REG_COMB,
 417                                 ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
 418         }
 419
 420         return -EINVAL;
 421 }
 422
 423 #ifdef CONFIG_VIDEO_ADV_DEBUG
 424 static int ov6650_get_register(struct v4l2_subdev *sd,
 425                                 struct v4l2_dbg_register *reg)
 426 {
 427         struct i2c_client *client = v4l2_get_subdevdata(sd);
 428         int ret;
 429         u8 val;
 430
 431         if (reg->reg & ~0xff)
 432                 return -EINVAL;
 433
 434         reg->size = 1;
 435
 436         ret = ov6650_reg_read(client, reg->reg, &val);
 437         if (!ret)
 438                 reg->val = (__u64)val;
 439
 440         return ret;
 441 }
 442
 443 static int ov6650_set_register(struct v4l2_subdev *sd,
 444                                 const struct v4l2_dbg_register *reg)
 445 {
 446         struct i2c_client *client = v4l2_get_subdevdata(sd);
 447
 448         if (reg->reg & ~0xff || reg->val & ~0xff)
 449                 return -EINVAL;
 450
 451         return ov6650_reg_write(client, reg->reg, reg->val);
 452 }
 453 #endif
 454
 455 static int ov6650_s_power(struct v4l2_subdev *sd, int on)
 456 {
 457         struct i2c_client *client = v4l2_get_subdevdata(sd);
 458         struct ov6650 *priv = to_ov6650(client);
 459         int ret = 0;
 460
 461         if (on)
 462                 ret = v4l2_clk_enable(priv->clk);
 463         else
 464                 v4l2_clk_disable(priv->clk);
 465
 466         return ret;
 467 }
 468
 469 static int ov6650_get_selection(struct v4l2_subdev *sd,
 470                 struct v4l2_subdev_pad_config *cfg,
 471                 struct v4l2_subdev_selection *sel)
 472 {
 473         struct i2c_client *client = v4l2_get_subdevdata(sd);
 474         struct ov6650 *priv = to_ov6650(client);
 475
 476         if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
 477                 return -EINVAL;
 478
 479         switch (sel->target) {
 480         case V4L2_SEL_TGT_CROP_BOUNDS:
 481                 sel->r.left = DEF_HSTRT << 1;
 482                 sel->r.top = DEF_VSTRT << 1;
 483                 sel->r.width = W_CIF;
 484                 sel->r.height = H_CIF;
 485                 return 0;
 486         case V4L2_SEL_TGT_CROP:
 487                 sel->r = priv->rect;
 488                 return 0;
 489         default:
 490                 return -EINVAL;
 491         }
 492 }
 493
 494 static int ov6650_set_selection(struct v4l2_subdev *sd,
 495                 struct v4l2_subdev_pad_config *cfg,
 496                 struct v4l2_subdev_selection *sel)
 497 {
 498         struct i2c_client *client = v4l2_get_subdevdata(sd);
 499         struct ov6650 *priv = to_ov6650(client);
 500         int ret;
 501
 502         if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
 503             sel->target != V4L2_SEL_TGT_CROP)
 504                 return -EINVAL;
 505
 506         v4l_bound_align_image(&sel->r.width, 2, W_CIF, 1,
 507                               &sel->r.height, 2, H_CIF, 1, 0);
 508         v4l_bound_align_image(&sel->r.left, DEF_HSTRT << 1,
 509                               (DEF_HSTRT << 1) + W_CIF - (__s32)sel->r.width, 1,
 510                               &sel->r.top, DEF_VSTRT << 1,
 511                               (DEF_VSTRT << 1) + H_CIF - (__s32)sel->r.height,
 512                               1, 0);
 513
 514         ret = ov6650_reg_write(client, REG_HSTRT, sel->r.left >> 1);
 515         if (!ret) {
 516                 priv->rect.width += priv->rect.left - sel->r.left;
 517                 priv->rect.left = sel->r.left;
 518                 ret = ov6650_reg_write(client, REG_HSTOP,
 519                                        (sel->r.left + sel->r.width) >> 1);
 520         }
 521         if (!ret) {
 522                 priv->rect.width = sel->r.width;
 523                 ret = ov6650_reg_write(client, REG_VSTRT, sel->r.top >> 1);
 524         }
 525         if (!ret) {
 526                 priv->rect.height += priv->rect.top - sel->r.top;
 527                 priv->rect.top = sel->r.top;
 528                 ret = ov6650_reg_write(client, REG_VSTOP,
 529                                        (sel->r.top + sel->r.height) >> 1);
 530         }
 531         if (!ret)
 532                 priv->rect.height = sel->r.height;
 533
 534         return ret;
 535 }
 536
 537 static int ov6650_get_fmt(struct v4l2_subdev *sd,
 538                 struct v4l2_subdev_pad_config *cfg,
 539                 struct v4l2_subdev_format *format)
 540 {
 541         struct v4l2_mbus_framefmt *mf = &format->format;
 542         struct i2c_client *client = v4l2_get_subdevdata(sd);
 543         struct ov6650 *priv = to_ov6650(client);
 544
 545         if (format->pad)
 546                 return -EINVAL;
 547
 548         /* initialize response with default media bus frame format */
 549         *mf = ov6650_def_fmt;
 550
 551         /* update media bus format code and frame size */
 552         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
 553                 mf->width = cfg->try_fmt.width;
 554                 mf->height = cfg->try_fmt.height;
 555                 mf->code = cfg->try_fmt.code;
 556
 557         } else {
 558                 mf->width = priv->rect.width >> priv->half_scale;
 559                 mf->height = priv->rect.height >> priv->half_scale;
 560                 mf->code = priv->code;
 561         }
 562         return 0;
 563 }
 564
 565 static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
 566 {
 567         return width > rect->width >> 1 || height > rect->height >> 1;
 568 }
 569
 570 #define to_clkrc(div)   ((div) - 1)
 571
 572 /* set the format we will capture in */
 573 static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
 574 {
 575         struct i2c_client *client = v4l2_get_subdevdata(sd);
 576         struct ov6650 *priv = to_ov6650(client);
 577         bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect);
 578         struct v4l2_subdev_selection sel = {
 579                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
 580                 .target = V4L2_SEL_TGT_CROP,
 581                 .r.left = priv->rect.left + (priv->rect.width >> 1) -
 582                         (mf->width >> (1 - half_scale)),
 583                 .r.top = priv->rect.top + (priv->rect.height >> 1) -
 584                         (mf->height >> (1 - half_scale)),
 585                 .r.width = mf->width << half_scale,
 586                 .r.height = mf->height << half_scale,
 587         };
 588         u32 code = mf->code;
 589         u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask;
 590         int ret;
 591
 592         /* select color matrix configuration for given color encoding */
 593         switch (code) {
 594         case MEDIA_BUS_FMT_Y8_1X8:
 595                 dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
 596                 coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
 597                 coma_set |= COMA_BW;
 598                 break;
 599         case MEDIA_BUS_FMT_YUYV8_2X8:
 600                 dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
 601                 coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
 602                 coma_set |= COMA_WORD_SWAP;
 603                 break;
 604         case MEDIA_BUS_FMT_YVYU8_2X8:
 605                 dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
 606                 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
 607                                 COMA_BYTE_SWAP;
 608                 break;
 609         case MEDIA_BUS_FMT_UYVY8_2X8:
 610                 dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
 611                 if (half_scale) {
 612                         coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
 613                         coma_set |= COMA_BYTE_SWAP;
 614                 } else {
 615                         coma_mask |= COMA_RGB | COMA_BW;
 616                         coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
 617                 }
 618                 break;
 619         case MEDIA_BUS_FMT_VYUY8_2X8:
 620                 dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
 621                 if (half_scale) {
 622                         coma_mask |= COMA_RGB | COMA_BW;
 623                         coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
 624                 } else {
 625                         coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
 626                         coma_set |= COMA_BYTE_SWAP;
 627                 }
 628                 break;
 629         case MEDIA_BUS_FMT_SBGGR8_1X8:
 630                 dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
 631                 coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
 632                 coma_set |= COMA_RAW_RGB | COMA_RGB;
 633                 break;
 634         default:
 635                 dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
 636                 return -EINVAL;
 637         }
 638
 639         if (code == MEDIA_BUS_FMT_Y8_1X8 ||
 640                         code == MEDIA_BUS_FMT_SBGGR8_1X8) {
 641                 coml_mask = COML_ONE_CHANNEL;
 642                 coml_set = 0;
 643         } else {
 644                 coml_mask = 0;
 645                 coml_set = COML_ONE_CHANNEL;
 646         }
 647
 648         if (half_scale) {
 649                 dev_dbg(&client->dev, "max resolution: QCIF\n");
 650                 coma_set |= COMA_QCIF;
 651         } else {
 652                 dev_dbg(&client->dev, "max resolution: CIF\n");
 653                 coma_mask |= COMA_QCIF;
 654         }
 655
 656         ret = ov6650_set_selection(sd, NULL, &sel);
 657         if (!ret)
 658                 ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
 659         if (!ret) {
 660                 priv->half_scale = half_scale;
 661
 662                 ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
 663         }
 664         if (!ret)
 665                 priv->code = code;
 666
 667         return ret;
 668 }
 669
 670 static int ov6650_set_fmt(struct v4l2_subdev *sd,
 671                 struct v4l2_subdev_pad_config *cfg,
 672                 struct v4l2_subdev_format *format)
 673 {
 674         struct v4l2_mbus_framefmt *mf = &format->format;
 675         struct i2c_client *client = v4l2_get_subdevdata(sd);
 676         struct ov6650 *priv = to_ov6650(client);
 677
 678         if (format->pad)
 679                 return -EINVAL;
 680
 681         if (is_unscaled_ok(mf->width, mf->height, &priv->rect))
 682                 v4l_bound_align_image(&mf->width, 2, W_CIF, 1,
 683                                 &mf->height, 2, H_CIF, 1, 0);
 684
 685         switch (mf->code) {
 686         case MEDIA_BUS_FMT_Y10_1X10:
 687                 mf->code = MEDIA_BUS_FMT_Y8_1X8;
 688                 /* fall through */
 689         case MEDIA_BUS_FMT_Y8_1X8:
 690         case MEDIA_BUS_FMT_YVYU8_2X8:
 691         case MEDIA_BUS_FMT_YUYV8_2X8:
 692         case MEDIA_BUS_FMT_VYUY8_2X8:
 693         case MEDIA_BUS_FMT_UYVY8_2X8:
 694                 break;
 695         default:
 696                 mf->code = MEDIA_BUS_FMT_SBGGR8_1X8;
 697                 /* fall through */
 698         case MEDIA_BUS_FMT_SBGGR8_1X8:
 699                 break;
 700         }
 701
 702         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
 703                 /* store media bus format code and frame size in pad config */
 704                 cfg->try_fmt.width = mf->width;
 705                 cfg->try_fmt.height = mf->height;
 706                 cfg->try_fmt.code = mf->code;
 707
 708                 /* return default mbus frame format updated with pad config */
 709                 *mf = ov6650_def_fmt;
 710                 mf->width = cfg->try_fmt.width;
 711                 mf->height = cfg->try_fmt.height;
 712                 mf->code = cfg->try_fmt.code;
 713
 714         } else {
 715                 /* apply new media bus format code and frame size */
 716                 int ret = ov6650_s_fmt(sd, mf);
 717
 718                 if (ret)
 719                         return ret;
 720
 721                 /* return default format updated with active size and code */
 722                 *mf = ov6650_def_fmt;
 723                 mf->width = priv->rect.width >> priv->half_scale;
 724                 mf->height = priv->rect.height >> priv->half_scale;
 725                 mf->code = priv->code;
 726         }
 727         return 0;
 728 }
 729
 730 static int ov6650_enum_mbus_code(struct v4l2_subdev *sd,
 731                 struct v4l2_subdev_pad_config *cfg,
 732                 struct v4l2_subdev_mbus_code_enum *code)
 733 {
 734         if (code->pad || code->index >= ARRAY_SIZE(ov6650_codes))
 735                 return -EINVAL;
 736
 737         code->code = ov6650_codes[code->index];
 738         return 0;
 739 }
 740
 741 static int ov6650_g_frame_interval(struct v4l2_subdev *sd,
 742                                    struct v4l2_subdev_frame_interval *ival)
 743 {
 744         struct i2c_client *client = v4l2_get_subdevdata(sd);
 745         struct ov6650 *priv = to_ov6650(client);
 746
 747         ival->interval = priv->tpf;
 748
 749         dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
 750                 ival->interval.numerator, ival->interval.denominator);
 751
 752         return 0;
 753 }
 754
 755 static int ov6650_s_frame_interval(struct v4l2_subdev *sd,
 756                                    struct v4l2_subdev_frame_interval *ival)
 757 {
 758         struct i2c_client *client = v4l2_get_subdevdata(sd);
 759         struct ov6650 *priv = to_ov6650(client);
 760         struct v4l2_fract *tpf = &ival->interval;
 761         int div, ret;
 762
 763         if (tpf->numerator == 0 || tpf->denominator == 0)
 764                 div = 1;  /* Reset to full rate */
 765         else
 766                 div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
 767
 768         if (div == 0)
 769                 div = 1;
 770         else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
 771                 div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
 772
 773         ret = ov6650_reg_rmw(client, REG_CLKRC, to_clkrc(div), CLKRC_DIV_MASK);
 774         if (!ret) {
 775                 priv->tpf.numerator = div;
 776                 priv->tpf.denominator = FRAME_RATE_MAX;
 777
 778                 *tpf = priv->tpf;
 779         }
 780
 781         return ret;
 782 }
 783
 784 /* Soft reset the camera. This has nothing to do with the RESET pin! */
 785 static int ov6650_reset(struct i2c_client *client)
 786 {
 787         int ret;
 788
 789         dev_dbg(&client->dev, "reset\n");
 790
 791         ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
 792         if (ret)
 793                 dev_err(&client->dev,
 794                         "An error occurred while entering soft reset!\n");
 795
 796         return ret;
 797 }
 798
 799 /* program default register values */
 800 static int ov6650_prog_dflt(struct i2c_client *client, u8 clkrc)
 801 {
 802         int ret;
 803
 804         dev_dbg(&client->dev, "initializing\n");
 805
 806         ret = ov6650_reg_write(client, REG_COMA, 0);    /* ~COMA_RESET */
 807         if (!ret)
 808                 ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
 809         if (!ret)
 810                 ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
 811
 812         return ret;
 813 }
 814
 815 static int ov6650_video_probe(struct v4l2_subdev *sd)
 816 {
 817         struct i2c_client *client = v4l2_get_subdevdata(sd);
 818         struct ov6650 *priv = to_ov6650(client);
 819         const struct ov6650_xclk *xclk = NULL;
 820         unsigned long rate;
 821         u8 pidh, pidl, midh, midl;
 822         int i, ret = 0;
 823
 824         priv->clk = v4l2_clk_get(&client->dev, NULL);
 825         if (IS_ERR(priv->clk)) {
 826                 ret = PTR_ERR(priv->clk);
 827                 dev_err(&client->dev, "v4l2_clk request err: %d\n", ret);
 828                 return ret;
 829         }
 830
 831         rate = v4l2_clk_get_rate(priv->clk);
 832         for (i = 0; rate && i < ARRAY_SIZE(ov6650_xclk); i++) {
 833                 if (rate != ov6650_xclk[i].rate)
 834                         continue;
 835
 836                 xclk = &ov6650_xclk[i];
 837                 dev_info(&client->dev, "using host default clock rate %lukHz\n",
 838                          rate / 1000);
 839                 break;
 840         }
 841         for (i = 0; !xclk && i < ARRAY_SIZE(ov6650_xclk); i++) {
 842                 ret = v4l2_clk_set_rate(priv->clk, ov6650_xclk[i].rate);
 843                 if (ret || v4l2_clk_get_rate(priv->clk) != ov6650_xclk[i].rate)
 844                         continue;
 845
 846                 xclk = &ov6650_xclk[i];
 847                 dev_info(&client->dev, "using negotiated clock rate %lukHz\n",
 848                          xclk->rate / 1000);
 849                 break;
 850         }
 851         if (!xclk) {
 852                 dev_err(&client->dev, "unable to get supported clock rate\n");
 853                 if (!ret)
 854                         ret = -EINVAL;
 855                 goto eclkput;
 856         }
 857
 858         ret = ov6650_s_power(sd, 1);
 859         if (ret < 0)
 860                 goto eclkput;
 861
 862         msleep(20);
 863
 864         /*
 865          * check and show product ID and manufacturer ID
 866          */
 867         ret = ov6650_reg_read(client, REG_PIDH, &pidh);
 868         if (!ret)
 869                 ret = ov6650_reg_read(client, REG_PIDL, &pidl);
 870         if (!ret)
 871                 ret = ov6650_reg_read(client, REG_MIDH, &midh);
 872         if (!ret)
 873                 ret = ov6650_reg_read(client, REG_MIDL, &midl);
 874
 875         if (ret)
 876                 goto done;
 877
 878         if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
 879                 dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
 880                                 pidh, pidl);
 881                 ret = -ENODEV;
 882                 goto done;
 883         }
 884
 885         dev_info(&client->dev,
 886                 "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
 887                 pidh, pidl, midh, midl);
 888
 889         ret = ov6650_reset(client);
 890         if (!ret)
 891                 ret = ov6650_prog_dflt(client, xclk->clkrc);
 892         if (!ret) {
 893                 struct v4l2_mbus_framefmt mf = ov6650_def_fmt;
 894
 895                 ret = ov6650_s_fmt(sd, &mf);
 896         }
 897         if (!ret)
 898                 ret = v4l2_ctrl_handler_setup(&priv->hdl);
 899
 900 done:
 901         ov6650_s_power(sd, 0);
 902         if (!ret)
 903                 return 0;
 904 eclkput:
 905         v4l2_clk_put(priv->clk);
 906
 907         return ret;
 908 }
 909
 910 static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
 911         .g_volatile_ctrl = ov6550_g_volatile_ctrl,
 912         .s_ctrl = ov6550_s_ctrl,
 913 };
 914
 915 static const struct v4l2_subdev_core_ops ov6650_core_ops = {
 916 #ifdef CONFIG_VIDEO_ADV_DEBUG
 917         .g_register             = ov6650_get_register,
 918         .s_register             = ov6650_set_register,
 919 #endif
 920         .s_power                = ov6650_s_power,
 921 };
 922
 923 /* Request bus settings on camera side */
 924 static int ov6650_g_mbus_config(struct v4l2_subdev *sd,
 925                                 struct v4l2_mbus_config *cfg)
 926 {
 927
 928         cfg->flags = V4L2_MBUS_MASTER |
 929                 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
 930                 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
 931                 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
 932                 V4L2_MBUS_DATA_ACTIVE_HIGH;
 933         cfg->type = V4L2_MBUS_PARALLEL;
 934
 935         return 0;
 936 }
 937
 938 /* Alter bus settings on camera side */
 939 static int ov6650_s_mbus_config(struct v4l2_subdev *sd,
 940                                 const struct v4l2_mbus_config *cfg)
 941 {
 942         struct i2c_client *client = v4l2_get_subdevdata(sd);
 943         int ret;
 944
 945         if (cfg->flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
 946                 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0);
 947         else
 948                 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING);
 949         if (ret)
 950                 return ret;
 951
 952         if (cfg->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
 953                 ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0);
 954         else
 955                 ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW);
 956         if (ret)
 957                 return ret;
 958
 959         if (cfg->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
 960                 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0);
 961         else
 962                 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH);
 963
 964         return ret;
 965 }
 966
 967 static const struct v4l2_subdev_video_ops ov6650_video_ops = {
 968         .s_stream       = ov6650_s_stream,
 969         .g_frame_interval = ov6650_g_frame_interval,
 970         .s_frame_interval = ov6650_s_frame_interval,
 971         .g_mbus_config  = ov6650_g_mbus_config,
 972         .s_mbus_config  = ov6650_s_mbus_config,
 973 };
 974
 975 static const struct v4l2_subdev_pad_ops ov6650_pad_ops = {
 976         .enum_mbus_code = ov6650_enum_mbus_code,
 977         .get_selection  = ov6650_get_selection,
 978         .set_selection  = ov6650_set_selection,
 979         .get_fmt        = ov6650_get_fmt,
 980         .set_fmt        = ov6650_set_fmt,
 981 };
 982
 983 static const struct v4l2_subdev_ops ov6650_subdev_ops = {
 984         .core   = &ov6650_core_ops,
 985         .video  = &ov6650_video_ops,
 986         .pad    = &ov6650_pad_ops,
 987 };
 988
 989 static const struct v4l2_subdev_internal_ops ov6650_internal_ops = {
 990         .registered = ov6650_video_probe,
 991 };
 992
 993 /*
 994  * i2c_driver function
 995  */
 996 static int ov6650_probe(struct i2c_client *client,
 997                         const struct i2c_device_id *did)
 998 {
 999         struct ov6650 *priv;
1000         int ret;
1001
1002         priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1003         if (!priv)
1004                 return -ENOMEM;
1005
1006         v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
1007         v4l2_ctrl_handler_init(&priv->hdl, 13);
1008         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1009                         V4L2_CID_VFLIP, 0, 1, 1, 0);
1010         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1011                         V4L2_CID_HFLIP, 0, 1, 1, 0);
1012         priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1013                         V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1014         priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1015                         V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
1016         priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1017                         V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1018         priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1019                         V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
1020         priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1021                         V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
1022         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1023                         V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
1024         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1025                         V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
1026         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1027                         V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
1028         priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
1029                         &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
1030                         V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
1031         priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1032                         V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
1033         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1034                         V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
1035
1036         priv->subdev.ctrl_handler = &priv->hdl;
1037         if (priv->hdl.error) {
1038                 ret = priv->hdl.error;
1039                 goto ectlhdlfree;
1040         }
1041
1042         v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
1043         v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
1044         v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
1045                                 V4L2_EXPOSURE_MANUAL, true);
1046
1047         priv->rect.left   = DEF_HSTRT << 1;
1048         priv->rect.top    = DEF_VSTRT << 1;
1049         priv->rect.width  = W_CIF;
1050         priv->rect.height = H_CIF;
1051
1052         /* Hardware default frame interval */
1053         priv->tpf.numerator   = GET_CLKRC_DIV(DEF_CLKRC);
1054         priv->tpf.denominator = FRAME_RATE_MAX;
1055
1056         priv->subdev.internal_ops = &ov6650_internal_ops;
1057
1058         ret = v4l2_async_register_subdev(&priv->subdev);
1059         if (!ret)
1060                 return 0;
1061 ectlhdlfree:
1062         v4l2_ctrl_handler_free(&priv->hdl);
1063
1064         return ret;
1065 }
1066
1067 static int ov6650_remove(struct i2c_client *client)
1068 {
1069         struct ov6650 *priv = to_ov6650(client);
1070
1071         v4l2_clk_put(priv->clk);
1072         v4l2_async_unregister_subdev(&priv->subdev);
1073         v4l2_ctrl_handler_free(&priv->hdl);
1074         return 0;
1075 }
1076
1077 static const struct i2c_device_id ov6650_id[] = {
1078         { "ov6650", 0 },
1079         { }
1080 };
1081 MODULE_DEVICE_TABLE(i2c, ov6650_id);
1082
1083 static struct i2c_driver ov6650_i2c_driver = {
1084         .driver = {
1085                 .name = "ov6650",
1086         },
1087         .probe    = ov6650_probe,
1088         .remove   = ov6650_remove,
1089         .id_table = ov6650_id,
1090 };
1091
1092 module_i2c_driver(ov6650_i2c_driver);
1093
1094 MODULE_DESCRIPTION("V4L2 subdevice driver for OmniVision OV6650 camera sensor");
1095 MODULE_AUTHOR("Janusz Krzysztofik <jmkrzyszt@gmail.com");
1096 MODULE_LICENSE("GPL v2");