2 * Sony CXD2820R demodulator driver
4 * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "cxd2820r_priv.h"
24 int cxd2820r_set_frontend_t2(struct dvb_frontend *fe)
26 struct cxd2820r_priv *priv = fe->demodulator_priv;
27 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
32 u8 bw_params1[][5] = {
33 { 0x1c, 0xb3, 0x33, 0x33, 0x33 }, /* 5 MHz */
34 { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
35 { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
36 { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
38 struct reg_val_mask tab[] = {
39 { 0x00080, 0x02, 0xff },
40 { 0x00081, 0x20, 0xff },
41 { 0x00085, 0x07, 0xff },
42 { 0x00088, 0x01, 0xff },
43 { 0x02069, 0x01, 0xff },
45 { 0x0207f, 0x2a, 0xff },
46 { 0x02082, 0x0a, 0xff },
47 { 0x02083, 0x0a, 0xff },
48 { 0x020cb, priv->cfg.if_agc_polarity << 6, 0x40 },
49 { 0x02070, priv->cfg.ts_mode, 0xff },
50 { 0x020b5, priv->cfg.spec_inv << 4, 0x10 },
51 { 0x02567, 0x07, 0x0f },
52 { 0x02569, 0x03, 0x03 },
53 { 0x02595, 0x1a, 0xff },
54 { 0x02596, 0x50, 0xff },
55 { 0x02a8c, 0x00, 0xff },
56 { 0x02a8d, 0x34, 0xff },
57 { 0x02a45, 0x06, 0x07 },
58 { 0x03f10, 0x0d, 0xff },
59 { 0x03f11, 0x02, 0xff },
60 { 0x03f12, 0x01, 0xff },
61 { 0x03f23, 0x2c, 0xff },
62 { 0x03f51, 0x13, 0xff },
63 { 0x03f52, 0x01, 0xff },
64 { 0x03f53, 0x00, 0xff },
65 { 0x027e6, 0x14, 0xff },
66 { 0x02786, 0x02, 0x07 },
67 { 0x02787, 0x40, 0xe0 },
68 { 0x027ef, 0x10, 0x18 },
71 dev_dbg(&priv->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n", __func__,
72 c->frequency, c->bandwidth_hz);
74 switch (c->bandwidth_hz) {
96 if (fe->ops.tuner_ops.set_params)
97 fe->ops.tuner_ops.set_params(fe);
99 if (priv->delivery_system != SYS_DVBT2) {
100 for (i = 0; i < ARRAY_SIZE(tab); i++) {
101 ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
102 tab[i].val, tab[i].mask);
108 priv->delivery_system = SYS_DVBT2;
110 /* program IF frequency */
111 if (fe->ops.tuner_ops.get_if_frequency) {
112 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
118 dev_dbg(&priv->i2c->dev, "%s: if_freq=%d\n", __func__, if_freq);
120 num = if_freq / 1000; /* Hz => kHz */
122 if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
123 buf[0] = ((if_ctl >> 16) & 0xff);
124 buf[1] = ((if_ctl >> 8) & 0xff);
125 buf[2] = ((if_ctl >> 0) & 0xff);
128 if (c->stream_id > 255) {
129 dev_dbg(&priv->i2c->dev, "%s: Disable PLP filtering\n", __func__);
130 ret = cxd2820r_wr_reg(priv, 0x023ad , 0);
134 dev_dbg(&priv->i2c->dev, "%s: Enable PLP filtering = %d\n", __func__,
136 ret = cxd2820r_wr_reg(priv, 0x023af , c->stream_id & 0xFF);
139 ret = cxd2820r_wr_reg(priv, 0x023ad , 1);
144 ret = cxd2820r_wr_regs(priv, 0x020b6, buf, 3);
148 ret = cxd2820r_wr_regs(priv, 0x0209f, bw_params1[bw_i], 5);
152 ret = cxd2820r_wr_reg_mask(priv, 0x020d7, bw_param << 6, 0xc0);
156 ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
160 ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
166 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
171 int cxd2820r_get_frontend_t2(struct dvb_frontend *fe)
173 struct cxd2820r_priv *priv = fe->demodulator_priv;
174 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
178 ret = cxd2820r_rd_regs(priv, 0x0205c, buf, 2);
182 switch ((buf[0] >> 0) & 0x07) {
184 c->transmission_mode = TRANSMISSION_MODE_2K;
187 c->transmission_mode = TRANSMISSION_MODE_8K;
190 c->transmission_mode = TRANSMISSION_MODE_4K;
193 c->transmission_mode = TRANSMISSION_MODE_1K;
196 c->transmission_mode = TRANSMISSION_MODE_16K;
199 c->transmission_mode = TRANSMISSION_MODE_32K;
203 switch ((buf[1] >> 4) & 0x07) {
205 c->guard_interval = GUARD_INTERVAL_1_32;
208 c->guard_interval = GUARD_INTERVAL_1_16;
211 c->guard_interval = GUARD_INTERVAL_1_8;
214 c->guard_interval = GUARD_INTERVAL_1_4;
217 c->guard_interval = GUARD_INTERVAL_1_128;
220 c->guard_interval = GUARD_INTERVAL_19_128;
223 c->guard_interval = GUARD_INTERVAL_19_256;
227 ret = cxd2820r_rd_regs(priv, 0x0225b, buf, 2);
231 switch ((buf[0] >> 0) & 0x07) {
233 c->fec_inner = FEC_1_2;
236 c->fec_inner = FEC_3_5;
239 c->fec_inner = FEC_2_3;
242 c->fec_inner = FEC_3_4;
245 c->fec_inner = FEC_4_5;
248 c->fec_inner = FEC_5_6;
252 switch ((buf[1] >> 0) & 0x07) {
254 c->modulation = QPSK;
257 c->modulation = QAM_16;
260 c->modulation = QAM_64;
263 c->modulation = QAM_256;
267 ret = cxd2820r_rd_reg(priv, 0x020b5, &buf[0]);
271 switch ((buf[0] >> 4) & 0x01) {
273 c->inversion = INVERSION_OFF;
276 c->inversion = INVERSION_ON;
282 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
286 int cxd2820r_read_status_t2(struct dvb_frontend *fe, fe_status_t *status)
288 struct cxd2820r_priv *priv = fe->demodulator_priv;
293 ret = cxd2820r_rd_reg(priv, 0x02010 , &buf[0]);
297 if ((buf[0] & 0x07) == 6) {
298 if (((buf[0] >> 5) & 0x01) == 1) {
299 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
300 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
302 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
303 FE_HAS_VITERBI | FE_HAS_SYNC;
307 dev_dbg(&priv->i2c->dev, "%s: lock=%02x\n", __func__, buf[0]);
311 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
315 int cxd2820r_read_ber_t2(struct dvb_frontend *fe, u32 *ber)
317 struct cxd2820r_priv *priv = fe->demodulator_priv;
320 unsigned int errbits;
322 /* FIXME: correct calculation */
324 ret = cxd2820r_rd_regs(priv, 0x02039, buf, sizeof(buf));
328 if ((buf[0] >> 4) & 0x01) {
329 errbits = (buf[0] & 0x0f) << 24 | buf[1] << 16 |
330 buf[2] << 8 | buf[3];
333 *ber = errbits * 64 / 16588800;
338 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
342 int cxd2820r_read_signal_strength_t2(struct dvb_frontend *fe,
345 struct cxd2820r_priv *priv = fe->demodulator_priv;
350 ret = cxd2820r_rd_regs(priv, 0x02026, buf, sizeof(buf));
354 tmp = (buf[0] & 0x0f) << 8 | buf[1];
357 /* scale value to 0x0000-0xffff from 0x0000-0x0fff */
358 *strength = tmp * 0xffff / 0x0fff;
362 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
366 int cxd2820r_read_snr_t2(struct dvb_frontend *fe, u16 *snr)
368 struct cxd2820r_priv *priv = fe->demodulator_priv;
372 /* report SNR in dB * 10 */
374 ret = cxd2820r_rd_regs(priv, 0x02028, buf, sizeof(buf));
378 tmp = (buf[0] & 0x0f) << 8 | buf[1];
379 #define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
381 *snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24)
386 dev_dbg(&priv->i2c->dev, "%s: dBx10=%d val=%04x\n", __func__, *snr,
391 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
395 int cxd2820r_read_ucblocks_t2(struct dvb_frontend *fe, u32 *ucblocks)
398 /* no way to read ? */
402 int cxd2820r_sleep_t2(struct dvb_frontend *fe)
404 struct cxd2820r_priv *priv = fe->demodulator_priv;
406 struct reg_val_mask tab[] = {
407 { 0x000ff, 0x1f, 0xff },
408 { 0x00085, 0x00, 0xff },
409 { 0x00088, 0x01, 0xff },
410 { 0x02069, 0x00, 0xff },
411 { 0x00081, 0x00, 0xff },
412 { 0x00080, 0x00, 0xff },
415 dev_dbg(&priv->i2c->dev, "%s\n", __func__);
417 for (i = 0; i < ARRAY_SIZE(tab); i++) {
418 ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
424 priv->delivery_system = SYS_UNDEFINED;
428 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
432 int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe,
433 struct dvb_frontend_tune_settings *s)
435 s->min_delay_ms = 1500;
436 s->step_size = fe->ops.info.frequency_stepsize * 2;
437 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;