1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
10 #include <mailbox-uclass.h>
13 #include <dm/device_compat.h>
14 #include <linux/bitops.h>
17 * IPCC has one set of registers per CPU
18 * IPCC_PROC_OFFST allows to define cpu registers set base address
19 * according to the assigned proc_id.
22 #define IPCC_PROC_OFFST 0x010
24 #define IPCC_XSCR 0x008
25 #define IPCC_XTOYSR 0x00c
27 #define IPCC_HWCFGR 0x3f0
28 #define IPCFGR_CHAN_MASK GENMASK(7, 0)
30 #define RX_BIT_CHAN(chan) BIT(chan)
31 #define TX_BIT_SHIFT 16
32 #define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan))
34 #define STM32_MAX_PROCS 2
37 void __iomem *reg_base;
38 void __iomem *reg_proc;
43 static int stm32_ipcc_request(struct mbox_chan *chan)
45 struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
47 debug("%s(chan=%p)\n", __func__, chan);
49 if (chan->id >= ipcc->n_chans) {
50 debug("%s failed to request channel: %ld\n",
58 static int stm32_ipcc_free(struct mbox_chan *chan)
60 debug("%s(chan=%p)\n", __func__, chan);
65 static int stm32_ipcc_send(struct mbox_chan *chan, const void *data)
67 struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
69 debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
71 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id))
74 /* set channel n occupied */
75 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id));
80 static int stm32_ipcc_recv(struct mbox_chan *chan, void *data)
82 struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
86 debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
88 /* read 'channel occupied' status from other proc */
89 proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
90 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
92 if (!(val & BIT(chan->id)))
95 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id));
100 static int stm32_ipcc_probe(struct udevice *dev)
102 struct stm32_ipcc *ipcc = dev_get_priv(dev);
108 debug("%s(dev=%p)\n", __func__, dev);
110 addr = dev_read_addr(dev);
111 if (addr == FDT_ADDR_T_NONE)
114 ipcc->reg_base = (void __iomem *)addr;
117 cell = dev_read_prop(dev, "st,proc_id", &len);
118 if (len < sizeof(fdt32_t)) {
119 dev_dbg(dev, "Missing st,proc_id\n");
123 ipcc->proc_id = fdtdec_get_number(cell, 1);
125 if (ipcc->proc_id >= STM32_MAX_PROCS) {
126 dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
130 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
132 ret = clk_get_by_index(dev, 0, &clk);
136 ret = clk_enable(&clk);
140 /* get channel number */
141 ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR);
142 ipcc->n_chans &= IPCFGR_CHAN_MASK;
152 static const struct udevice_id stm32_ipcc_ids[] = {
153 { .compatible = "st,stm32mp1-ipcc" },
157 struct mbox_ops stm32_ipcc_mbox_ops = {
158 .request = stm32_ipcc_request,
159 .rfree = stm32_ipcc_free,
160 .send = stm32_ipcc_send,
161 .recv = stm32_ipcc_recv,
164 U_BOOT_DRIVER(stm32_ipcc) = {
165 .name = "stm32_ipcc",
166 .id = UCLASS_MAILBOX,
167 .of_match = stm32_ipcc_ids,
168 .probe = stm32_ipcc_probe,
169 .priv_auto_alloc_size = sizeof(struct stm32_ipcc),
170 .ops = &stm32_ipcc_mbox_ops,