1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
9 #include <mailbox-uclass.h>
12 #include <dm/device_compat.h>
15 * IPCC has one set of registers per CPU
16 * IPCC_PROC_OFFST allows to define cpu registers set base address
17 * according to the assigned proc_id.
20 #define IPCC_PROC_OFFST 0x010
22 #define IPCC_XSCR 0x008
23 #define IPCC_XTOYSR 0x00c
25 #define IPCC_HWCFGR 0x3f0
26 #define IPCFGR_CHAN_MASK GENMASK(7, 0)
28 #define RX_BIT_CHAN(chan) BIT(chan)
29 #define TX_BIT_SHIFT 16
30 #define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan))
32 #define STM32_MAX_PROCS 2
35 void __iomem *reg_base;
36 void __iomem *reg_proc;
41 static int stm32_ipcc_request(struct mbox_chan *chan)
43 struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
45 debug("%s(chan=%p)\n", __func__, chan);
47 if (chan->id >= ipcc->n_chans) {
48 debug("%s failed to request channel: %ld\n",
56 static int stm32_ipcc_free(struct mbox_chan *chan)
58 debug("%s(chan=%p)\n", __func__, chan);
63 static int stm32_ipcc_send(struct mbox_chan *chan, const void *data)
65 struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
67 debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
69 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id))
72 /* set channel n occupied */
73 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id));
78 static int stm32_ipcc_recv(struct mbox_chan *chan, void *data)
80 struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
84 debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
86 /* read 'channel occupied' status from other proc */
87 proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
88 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
90 if (!(val & BIT(chan->id)))
93 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id));
98 static int stm32_ipcc_probe(struct udevice *dev)
100 struct stm32_ipcc *ipcc = dev_get_priv(dev);
106 debug("%s(dev=%p)\n", __func__, dev);
108 addr = dev_read_addr(dev);
109 if (addr == FDT_ADDR_T_NONE)
112 ipcc->reg_base = (void __iomem *)addr;
115 cell = dev_read_prop(dev, "st,proc_id", &len);
116 if (len < sizeof(fdt32_t)) {
117 dev_dbg(dev, "Missing st,proc_id\n");
121 ipcc->proc_id = fdtdec_get_number(cell, 1);
123 if (ipcc->proc_id >= STM32_MAX_PROCS) {
124 dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
128 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
130 ret = clk_get_by_index(dev, 0, &clk);
134 ret = clk_enable(&clk);
138 /* get channel number */
139 ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR);
140 ipcc->n_chans &= IPCFGR_CHAN_MASK;
150 static const struct udevice_id stm32_ipcc_ids[] = {
151 { .compatible = "st,stm32mp1-ipcc" },
155 struct mbox_ops stm32_ipcc_mbox_ops = {
156 .request = stm32_ipcc_request,
157 .rfree = stm32_ipcc_free,
158 .send = stm32_ipcc_send,
159 .recv = stm32_ipcc_recv,
162 U_BOOT_DRIVER(stm32_ipcc) = {
163 .name = "stm32_ipcc",
164 .id = UCLASS_MAILBOX,
165 .of_match = stm32_ipcc_ids,
166 .probe = stm32_ipcc_probe,
167 .priv_auto_alloc_size = sizeof(struct stm32_ipcc),
168 .ops = &stm32_ipcc_mbox_ops,