2 * Copyright (C) 2005-2006 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #if defined(CONFIG_MACB) \
21 && (defined(CONFIG_CMD_NET) || defined(CONFIG_CMD_MII))
24 * The u-boot networking stack is a little weird. It seems like the
25 * networking core allocates receive buffers up front without any
26 * regard to the hardware that's supposed to actually receive those
29 * The MACB receives packets into 128-byte receive buffers, so the
30 * buffers allocated by the core isn't very practical to use. We'll
31 * allocate our own, but we need one such buffer in case a packet
32 * wraps around the DMA ring so that we have to copy it.
34 * Therefore, define CFG_RX_ETH_BUFFER to 1 in the board-specific
35 * configuration header. This way, the core allocates one RX buffer
36 * and one TX buffer, each of which can hold a ethernet packet of
39 * For some reason, the networking core unconditionally specifies a
40 * 32-byte packet "alignment" (which really should be called
41 * "padding"). MACB shouldn't need that, but we'll refrain from any
42 * core modifications here...
48 #include <linux/mii.h>
50 #include <asm/dma-mapping.h>
51 #include <asm/arch/clk.h>
55 #define CFG_MACB_RX_BUFFER_SIZE 4096
56 #define CFG_MACB_RX_RING_SIZE (CFG_MACB_RX_BUFFER_SIZE / 128)
57 #define CFG_MACB_TX_RING_SIZE 16
58 #define CFG_MACB_TX_TIMEOUT 1000
59 #define CFG_MACB_AUTONEG_TIMEOUT 5000000
61 struct macb_dma_desc {
66 #define RXADDR_USED 0x00000001
67 #define RXADDR_WRAP 0x00000002
69 #define RXBUF_FRMLEN_MASK 0x00000fff
70 #define RXBUF_FRAME_START 0x00004000
71 #define RXBUF_FRAME_END 0x00008000
72 #define RXBUF_TYPEID_MATCH 0x00400000
73 #define RXBUF_ADDR4_MATCH 0x00800000
74 #define RXBUF_ADDR3_MATCH 0x01000000
75 #define RXBUF_ADDR2_MATCH 0x02000000
76 #define RXBUF_ADDR1_MATCH 0x04000000
77 #define RXBUF_BROADCAST 0x80000000
79 #define TXBUF_FRMLEN_MASK 0x000007ff
80 #define TXBUF_FRAME_END 0x00008000
81 #define TXBUF_NOCRC 0x00010000
82 #define TXBUF_EXHAUSTED 0x08000000
83 #define TXBUF_UNDERRUN 0x10000000
84 #define TXBUF_MAXRETRY 0x20000000
85 #define TXBUF_WRAP 0x40000000
86 #define TXBUF_USED 0x80000000
97 struct macb_dma_desc *rx_ring;
98 struct macb_dma_desc *tx_ring;
100 unsigned long rx_buffer_dma;
101 unsigned long rx_ring_dma;
102 unsigned long tx_ring_dma;
104 const struct device *dev;
105 struct eth_device netdev;
106 unsigned short phy_addr;
108 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
110 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
112 unsigned long netctl;
113 unsigned long netstat;
116 netctl = macb_readl(macb, NCR);
117 netctl |= MACB_BIT(MPE);
118 macb_writel(macb, NCR, netctl);
120 frame = (MACB_BF(SOF, 1)
122 | MACB_BF(PHYA, macb->phy_addr)
125 | MACB_BF(DATA, value));
126 macb_writel(macb, MAN, frame);
129 netstat = macb_readl(macb, NSR);
130 } while (!(netstat & MACB_BIT(IDLE)));
132 netctl = macb_readl(macb, NCR);
133 netctl &= ~MACB_BIT(MPE);
134 macb_writel(macb, NCR, netctl);
137 static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
139 unsigned long netctl;
140 unsigned long netstat;
143 netctl = macb_readl(macb, NCR);
144 netctl |= MACB_BIT(MPE);
145 macb_writel(macb, NCR, netctl);
147 frame = (MACB_BF(SOF, 1)
149 | MACB_BF(PHYA, macb->phy_addr)
152 macb_writel(macb, MAN, frame);
155 netstat = macb_readl(macb, NSR);
156 } while (!(netstat & MACB_BIT(IDLE)));
158 frame = macb_readl(macb, MAN);
160 netctl = macb_readl(macb, NCR);
161 netctl &= ~MACB_BIT(MPE);
162 macb_writel(macb, NCR, netctl);
164 return MACB_BFEXT(DATA, frame);
167 #if defined(CONFIG_CMD_NET)
169 static int macb_send(struct eth_device *netdev, volatile void *packet,
172 struct macb_device *macb = to_macb(netdev);
173 unsigned long paddr, ctrl;
174 unsigned int tx_head = macb->tx_head;
177 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
179 ctrl = length & TXBUF_FRMLEN_MASK;
180 ctrl |= TXBUF_FRAME_END;
181 if (tx_head == (CFG_MACB_TX_RING_SIZE - 1)) {
187 macb->tx_ring[tx_head].ctrl = ctrl;
188 macb->tx_ring[tx_head].addr = paddr;
189 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
192 * I guess this is necessary because the networking core may
193 * re-use the transmit buffer as soon as we return...
196 while (!(macb->tx_ring[tx_head].ctrl & TXBUF_USED)) {
197 if (i > CFG_MACB_TX_TIMEOUT) {
198 printf("%s: TX timeout\n", netdev->name);
205 dma_unmap_single(packet, length, paddr);
207 if (i <= CFG_MACB_TX_TIMEOUT) {
208 ctrl = macb->tx_ring[tx_head].ctrl;
209 if (ctrl & TXBUF_UNDERRUN)
210 printf("%s: TX underrun\n", netdev->name);
211 if (ctrl & TXBUF_EXHAUSTED)
212 printf("%s: TX buffers exhausted in mid frame\n",
216 /* No one cares anyway */
220 static void reclaim_rx_buffers(struct macb_device *macb,
221 unsigned int new_tail)
226 while (i > new_tail) {
227 macb->rx_ring[i].addr &= ~RXADDR_USED;
229 if (i > CFG_MACB_RX_RING_SIZE)
233 while (i < new_tail) {
234 macb->rx_ring[i].addr &= ~RXADDR_USED;
238 macb->rx_tail = new_tail;
241 static int macb_recv(struct eth_device *netdev)
243 struct macb_device *macb = to_macb(netdev);
244 unsigned int rx_tail = macb->rx_tail;
251 if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
254 status = macb->rx_ring[rx_tail].ctrl;
255 if (status & RXBUF_FRAME_START) {
256 if (rx_tail != macb->rx_tail)
257 reclaim_rx_buffers(macb, rx_tail);
261 if (status & RXBUF_FRAME_END) {
262 buffer = macb->rx_buffer + 128 * macb->rx_tail;
263 length = status & RXBUF_FRMLEN_MASK;
265 unsigned int headlen, taillen;
267 headlen = 128 * (CFG_MACB_RX_RING_SIZE
269 taillen = length - headlen;
270 memcpy((void *)NetRxPackets[0],
272 memcpy((void *)NetRxPackets[0] + headlen,
273 macb->rx_buffer, taillen);
274 buffer = (void *)NetRxPackets[0];
277 NetReceive(buffer, length);
278 if (++rx_tail >= CFG_MACB_RX_RING_SIZE)
280 reclaim_rx_buffers(macb, rx_tail);
282 if (++rx_tail >= CFG_MACB_RX_RING_SIZE) {
292 static int macb_phy_init(struct macb_device *macb)
294 struct eth_device *netdev = &macb->netdev;
296 u16 phy_id, status, adv, lpa;
297 int media, speed, duplex;
300 /* Check if the PHY is up to snuff... */
301 phy_id = macb_mdio_read(macb, MII_PHYSID1);
302 if (phy_id == 0xffff) {
303 printf("%s: No PHY present\n", netdev->name);
307 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
308 macb_mdio_write(macb, MII_ADVERTISE, adv);
309 printf("%s: Starting autonegotiation...\n", netdev->name);
310 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
314 for (i = 0; i < 9; i++)
315 printf("mii%d: 0x%04x\n", i, macb_mdio_read(macb, i));
318 for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) {
319 status = macb_mdio_read(macb, MII_BMSR);
320 if (status & BMSR_ANEGCOMPLETE)
325 if (status & BMSR_ANEGCOMPLETE)
326 printf("%s: Autonegotiation complete\n", netdev->name);
328 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
329 netdev->name, status);
331 if (!(status & BMSR_LSTATUS)) {
332 for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) {
334 status = macb_mdio_read(macb, MII_BMSR);
335 if (status & BMSR_LSTATUS)
340 if (!(status & BMSR_LSTATUS)) {
341 printf("%s: link down (status: 0x%04x)\n",
342 netdev->name, status);
345 lpa = macb_mdio_read(macb, MII_LPA);
346 media = mii_nway_result(lpa & adv);
347 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
349 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
350 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
352 speed ? "100" : "10",
353 duplex ? "full" : "half",
356 ncfgr = macb_readl(macb, NCFGR);
357 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
359 ncfgr |= MACB_BIT(SPD);
361 ncfgr |= MACB_BIT(FD);
362 macb_writel(macb, NCFGR, ncfgr);
367 static int macb_init(struct eth_device *netdev, bd_t *bd)
369 struct macb_device *macb = to_macb(netdev);
376 * macb_halt should have been called at some point before now,
377 * so we'll assume the controller is idle.
380 /* initialize DMA descriptors */
381 paddr = macb->rx_buffer_dma;
382 for (i = 0; i < CFG_MACB_RX_RING_SIZE; i++) {
383 if (i == (CFG_MACB_RX_RING_SIZE - 1))
384 paddr |= RXADDR_WRAP;
385 macb->rx_ring[i].addr = paddr;
386 macb->rx_ring[i].ctrl = 0;
389 for (i = 0; i < CFG_MACB_TX_RING_SIZE; i++) {
390 macb->tx_ring[i].addr = 0;
391 if (i == (CFG_MACB_TX_RING_SIZE - 1))
392 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
394 macb->tx_ring[i].ctrl = TXBUF_USED;
396 macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
398 macb_writel(macb, RBQP, macb->rx_ring_dma);
399 macb_writel(macb, TBQP, macb->tx_ring_dma);
401 /* set hardware address */
402 hwaddr_bottom = cpu_to_le32(*((u32 *)netdev->enetaddr));
403 macb_writel(macb, SA1B, hwaddr_bottom);
404 hwaddr_top = cpu_to_le16(*((u16 *)(netdev->enetaddr + 4)));
405 macb_writel(macb, SA1T, hwaddr_top);
407 /* choose RMII or MII mode. This depends on the board */
409 macb_writel(macb, USRIO, 0);
411 macb_writel(macb, USRIO, MACB_BIT(MII));
414 if (!macb_phy_init(macb))
417 /* Enable TX and RX */
418 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
423 static void macb_halt(struct eth_device *netdev)
425 struct macb_device *macb = to_macb(netdev);
428 /* Halt the controller and wait for any ongoing transmission to end. */
429 ncr = macb_readl(macb, NCR);
430 ncr |= MACB_BIT(THALT);
431 macb_writel(macb, NCR, ncr);
434 tsr = macb_readl(macb, TSR);
435 } while (tsr & MACB_BIT(TGO));
437 /* Disable TX and RX, and clear statistics */
438 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
441 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
443 struct macb_device *macb;
444 struct eth_device *netdev;
445 unsigned long macb_hz;
448 macb = malloc(sizeof(struct macb_device));
450 printf("Error: Failed to allocate memory for MACB%d\n", id);
453 memset(macb, 0, sizeof(struct macb_device));
455 netdev = &macb->netdev;
457 macb->rx_buffer = dma_alloc_coherent(CFG_MACB_RX_BUFFER_SIZE,
458 &macb->rx_buffer_dma);
459 macb->rx_ring = dma_alloc_coherent(CFG_MACB_RX_RING_SIZE
460 * sizeof(struct macb_dma_desc),
462 macb->tx_ring = dma_alloc_coherent(CFG_MACB_TX_RING_SIZE
463 * sizeof(struct macb_dma_desc),
467 macb->phy_addr = phy_addr;
469 sprintf(netdev->name, "macb%d", id);
470 netdev->init = macb_init;
471 netdev->halt = macb_halt;
472 netdev->send = macb_send;
473 netdev->recv = macb_recv;
476 * Do some basic initialization so that we at least can talk
479 macb_hz = get_macb_pclk_rate(id);
480 if (macb_hz < 20000000)
481 ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
482 else if (macb_hz < 40000000)
483 ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
484 else if (macb_hz < 80000000)
485 ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
487 ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
489 macb_writel(macb, NCFGR, ncfgr);
491 eth_register(netdev);
498 #if defined(CONFIG_CMD_MII)
500 int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
502 unsigned long netctl;
503 unsigned long netstat;
507 iflag = disable_interrupts();
508 netctl = macb_readl(&macb, EMACB_NCR);
509 netctl |= MACB_BIT(MPE);
510 macb_writel(&macb, EMACB_NCR, netctl);
514 frame = (MACB_BF(SOF, 1)
516 | MACB_BF(PHYA, addr)
519 macb_writel(&macb, EMACB_MAN, frame);
522 netstat = macb_readl(&macb, EMACB_NSR);
523 } while (!(netstat & MACB_BIT(IDLE)));
525 frame = macb_readl(&macb, EMACB_MAN);
526 *value = MACB_BFEXT(DATA, frame);
528 iflag = disable_interrupts();
529 netctl = macb_readl(&macb, EMACB_NCR);
530 netctl &= ~MACB_BIT(MPE);
531 macb_writel(&macb, EMACB_NCR, netctl);
538 int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
540 unsigned long netctl;
541 unsigned long netstat;
545 iflag = disable_interrupts();
546 netctl = macb_readl(&macb, EMACB_NCR);
547 netctl |= MACB_BIT(MPE);
548 macb_writel(&macb, EMACB_NCR, netctl);
552 frame = (MACB_BF(SOF, 1)
554 | MACB_BF(PHYA, addr)
557 | MACB_BF(DATA, value));
558 macb_writel(&macb, EMACB_MAN, frame);
561 netstat = macb_readl(&macb, EMACB_NSR);
562 } while (!(netstat & MACB_BIT(IDLE)));
564 iflag = disable_interrupts();
565 netctl = macb_readl(&macb, EMACB_NCR);
566 netctl &= ~MACB_BIT(MPE);
567 macb_writel(&macb, EMACB_NCR, netctl);
576 #endif /* CONFIG_MACB */