2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/kref.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_user_verbs.h>
36 #include <rdma/ib_cache.h>
40 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe)
42 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
44 ibcq->comp_handler(ibcq, ibcq->cq_context);
47 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
49 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
50 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
51 struct ib_cq *ibcq = &cq->ibcq;
52 struct ib_event event;
54 if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
55 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
60 if (ibcq->event_handler) {
61 event.device = &dev->ib_dev;
62 event.event = IB_EVENT_CQ_ERR;
63 event.element.cq = ibcq;
64 ibcq->event_handler(&event, ibcq->cq_context);
68 static void *get_cqe(struct mlx5_ib_cq *cq, int n)
70 return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n);
73 static u8 sw_ownership_bit(int n, int nent)
75 return (n & nent) ? 1 : 0;
78 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
80 void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
81 struct mlx5_cqe64 *cqe64;
83 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
85 if (likely(get_cqe_opcode(cqe64) != MLX5_CQE_INVALID) &&
86 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
93 static void *next_cqe_sw(struct mlx5_ib_cq *cq)
95 return get_sw_cqe(cq, cq->mcq.cons_index);
98 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
100 switch (wq->wr_data[idx]) {
104 case IB_WR_LOCAL_INV:
105 return IB_WC_LOCAL_INV;
111 pr_warn("unknown completion status\n");
116 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
117 struct mlx5_ib_wq *wq, int idx)
120 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
121 case MLX5_OPCODE_RDMA_WRITE_IMM:
122 wc->wc_flags |= IB_WC_WITH_IMM;
124 case MLX5_OPCODE_RDMA_WRITE:
125 wc->opcode = IB_WC_RDMA_WRITE;
127 case MLX5_OPCODE_SEND_IMM:
128 wc->wc_flags |= IB_WC_WITH_IMM;
130 case MLX5_OPCODE_SEND:
131 case MLX5_OPCODE_SEND_INVAL:
132 wc->opcode = IB_WC_SEND;
134 case MLX5_OPCODE_RDMA_READ:
135 wc->opcode = IB_WC_RDMA_READ;
136 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
138 case MLX5_OPCODE_ATOMIC_CS:
139 wc->opcode = IB_WC_COMP_SWAP;
142 case MLX5_OPCODE_ATOMIC_FA:
143 wc->opcode = IB_WC_FETCH_ADD;
146 case MLX5_OPCODE_ATOMIC_MASKED_CS:
147 wc->opcode = IB_WC_MASKED_COMP_SWAP;
150 case MLX5_OPCODE_ATOMIC_MASKED_FA:
151 wc->opcode = IB_WC_MASKED_FETCH_ADD;
154 case MLX5_OPCODE_UMR:
155 wc->opcode = get_umr_comp(wq, idx);
161 MLX5_GRH_IN_BUFFER = 1,
165 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
166 struct mlx5_ib_qp *qp)
168 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
169 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
170 struct mlx5_ib_srq *srq;
171 struct mlx5_ib_wq *wq;
177 if (qp->ibqp.srq || qp->ibqp.xrcd) {
178 struct mlx5_core_srq *msrq = NULL;
181 msrq = mlx5_cmd_get_srq(dev, be32_to_cpu(cqe->srqn));
182 srq = to_mibsrq(msrq);
184 srq = to_msrq(qp->ibqp.srq);
187 wqe_ctr = be16_to_cpu(cqe->wqe_counter);
188 wc->wr_id = srq->wrid[wqe_ctr];
189 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
191 mlx5_core_res_put(&msrq->common);
195 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
198 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
200 switch (get_cqe_opcode(cqe)) {
201 case MLX5_CQE_RESP_WR_IMM:
202 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
203 wc->wc_flags = IB_WC_WITH_IMM;
204 wc->ex.imm_data = cqe->imm_inval_pkey;
206 case MLX5_CQE_RESP_SEND:
207 wc->opcode = IB_WC_RECV;
208 wc->wc_flags = IB_WC_IP_CSUM_OK;
209 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
210 (cqe->hds_ip_ext & CQE_L4_OK))))
213 case MLX5_CQE_RESP_SEND_IMM:
214 wc->opcode = IB_WC_RECV;
215 wc->wc_flags = IB_WC_WITH_IMM;
216 wc->ex.imm_data = cqe->imm_inval_pkey;
218 case MLX5_CQE_RESP_SEND_INV:
219 wc->opcode = IB_WC_RECV;
220 wc->wc_flags = IB_WC_WITH_INVALIDATE;
221 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
224 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
225 wc->dlid_path_bits = cqe->ml_path;
226 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
227 wc->wc_flags |= g ? IB_WC_GRH : 0;
228 if (unlikely(is_qp1(qp->ibqp.qp_type))) {
229 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
231 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
237 if (ll != IB_LINK_LAYER_ETHERNET) {
238 wc->slid = be16_to_cpu(cqe->slid);
239 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
244 vlan_present = cqe->l4_l3_hdr_type & 0x1;
245 roce_packet_type = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3;
247 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff;
248 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7;
249 wc->wc_flags |= IB_WC_WITH_VLAN;
254 switch (roce_packet_type) {
255 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
256 wc->network_hdr_type = RDMA_NETWORK_IB;
258 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
259 wc->network_hdr_type = RDMA_NETWORK_IPV6;
261 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
262 wc->network_hdr_type = RDMA_NETWORK_IPV4;
265 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
268 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
270 mlx5_ib_warn(dev, "dump error cqe\n");
271 mlx5_dump_err_cqe(dev->mdev, cqe);
274 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
275 struct mlx5_err_cqe *cqe,
280 switch (cqe->syndrome) {
281 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
282 wc->status = IB_WC_LOC_LEN_ERR;
284 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
285 wc->status = IB_WC_LOC_QP_OP_ERR;
287 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
288 wc->status = IB_WC_LOC_PROT_ERR;
290 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
292 wc->status = IB_WC_WR_FLUSH_ERR;
294 case MLX5_CQE_SYNDROME_MW_BIND_ERR:
295 wc->status = IB_WC_MW_BIND_ERR;
297 case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
298 wc->status = IB_WC_BAD_RESP_ERR;
300 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
301 wc->status = IB_WC_LOC_ACCESS_ERR;
303 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
304 wc->status = IB_WC_REM_INV_REQ_ERR;
306 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
307 wc->status = IB_WC_REM_ACCESS_ERR;
309 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
310 wc->status = IB_WC_REM_OP_ERR;
312 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
313 wc->status = IB_WC_RETRY_EXC_ERR;
316 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
317 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
320 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
321 wc->status = IB_WC_REM_ABORT_ERR;
324 wc->status = IB_WC_GENERAL_ERR;
328 wc->vendor_err = cqe->vendor_err_synd;
333 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
335 mlx5_frag_buf_free(dev->mdev, &buf->frag_buf);
338 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
339 struct ib_sig_err *item)
341 u16 syndrome = be16_to_cpu(cqe->syndrome);
343 #define GUARD_ERR (1 << 13)
344 #define APPTAG_ERR (1 << 12)
345 #define REFTAG_ERR (1 << 11)
347 if (syndrome & GUARD_ERR) {
348 item->err_type = IB_SIG_BAD_GUARD;
349 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
350 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
352 if (syndrome & REFTAG_ERR) {
353 item->err_type = IB_SIG_BAD_REFTAG;
354 item->expected = be32_to_cpu(cqe->expected_reftag);
355 item->actual = be32_to_cpu(cqe->actual_reftag);
357 if (syndrome & APPTAG_ERR) {
358 item->err_type = IB_SIG_BAD_APPTAG;
359 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
360 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
362 pr_err("Got signature completion error with bad syndrome %04x\n",
366 item->sig_err_offset = be64_to_cpu(cqe->err_offset);
367 item->key = be32_to_cpu(cqe->mkey);
370 static void sw_comp(struct mlx5_ib_qp *qp, int num_entries, struct ib_wc *wc,
371 int *npolled, int is_send)
373 struct mlx5_ib_wq *wq;
378 wq = (is_send) ? &qp->sq : &qp->rq;
379 cur = wq->head - wq->tail;
385 for (i = 0; i < cur && np < num_entries; i++) {
386 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
387 wc->status = IB_WC_WR_FLUSH_ERR;
388 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
397 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries,
398 struct ib_wc *wc, int *npolled)
400 struct mlx5_ib_qp *qp;
403 /* Find uncompleted WQEs belonging to that cq and return mmics ones */
404 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) {
405 sw_comp(qp, num_entries, wc + *npolled, npolled, true);
406 if (*npolled >= num_entries)
410 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) {
411 sw_comp(qp, num_entries, wc + *npolled, npolled, false);
412 if (*npolled >= num_entries)
417 static int mlx5_poll_one(struct mlx5_ib_cq *cq,
418 struct mlx5_ib_qp **cur_qp,
421 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
422 struct mlx5_err_cqe *err_cqe;
423 struct mlx5_cqe64 *cqe64;
424 struct mlx5_core_qp *mqp;
425 struct mlx5_ib_wq *wq;
426 struct mlx5_sig_err_cqe *sig_err_cqe;
427 struct mlx5_core_mkey *mmkey;
428 struct mlx5_ib_mr *mr;
436 cqe = next_cqe_sw(cq);
440 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
442 ++cq->mcq.cons_index;
444 /* Make sure we read CQ entry contents after we've checked the
449 opcode = get_cqe_opcode(cqe64);
450 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
451 if (likely(cq->resize_buf)) {
452 free_cq_buf(dev, &cq->buf);
453 cq->buf = *cq->resize_buf;
454 kfree(cq->resize_buf);
455 cq->resize_buf = NULL;
458 mlx5_ib_warn(dev, "unexpected resize cqe\n");
462 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
463 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
464 /* We do not have to take the QP table lock here,
465 * because CQs will be locked while QPs are removed
468 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
469 *cur_qp = to_mibqp(mqp);
472 wc->qp = &(*cur_qp)->ibqp;
476 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
477 idx = wqe_ctr & (wq->wqe_cnt - 1);
478 handle_good_req(wc, cqe64, wq, idx);
479 wc->wr_id = wq->wrid[idx];
480 wq->tail = wq->wqe_head[idx] + 1;
481 wc->status = IB_WC_SUCCESS;
483 case MLX5_CQE_RESP_WR_IMM:
484 case MLX5_CQE_RESP_SEND:
485 case MLX5_CQE_RESP_SEND_IMM:
486 case MLX5_CQE_RESP_SEND_INV:
487 handle_responder(wc, cqe64, *cur_qp);
488 wc->status = IB_WC_SUCCESS;
490 case MLX5_CQE_RESIZE_CQ:
492 case MLX5_CQE_REQ_ERR:
493 case MLX5_CQE_RESP_ERR:
494 err_cqe = (struct mlx5_err_cqe *)cqe64;
495 mlx5_handle_error_cqe(dev, err_cqe, wc);
496 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
497 opcode == MLX5_CQE_REQ_ERR ?
498 "Requestor" : "Responder", cq->mcq.cqn);
499 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
500 err_cqe->syndrome, err_cqe->vendor_err_synd);
501 if (opcode == MLX5_CQE_REQ_ERR) {
503 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
504 idx = wqe_ctr & (wq->wqe_cnt - 1);
505 wc->wr_id = wq->wrid[idx];
506 wq->tail = wq->wqe_head[idx] + 1;
508 struct mlx5_ib_srq *srq;
510 if ((*cur_qp)->ibqp.srq) {
511 srq = to_msrq((*cur_qp)->ibqp.srq);
512 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
513 wc->wr_id = srq->wrid[wqe_ctr];
514 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
517 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
522 case MLX5_CQE_SIG_ERR:
523 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64;
525 xa_lock(&dev->mdev->priv.mkey_table);
526 mmkey = xa_load(&dev->mdev->priv.mkey_table,
527 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
528 mr = to_mibmr(mmkey);
529 get_sig_err_item(sig_err_cqe, &mr->sig->err_item);
530 mr->sig->sig_err_exists = true;
531 mr->sig->sigerr_count++;
533 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
534 cq->mcq.cqn, mr->sig->err_item.key,
535 mr->sig->err_item.err_type,
536 mr->sig->err_item.sig_err_offset,
537 mr->sig->err_item.expected,
538 mr->sig->err_item.actual);
540 xa_unlock(&dev->mdev->priv.mkey_table);
547 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
548 struct ib_wc *wc, bool is_fatal_err)
550 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
551 struct mlx5_ib_wc *soft_wc, *next;
554 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) {
555 if (npolled >= num_entries)
558 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
561 if (unlikely(is_fatal_err)) {
562 soft_wc->wc.status = IB_WC_WR_FLUSH_ERR;
563 soft_wc->wc.vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
565 wc[npolled++] = soft_wc->wc;
566 list_del(&soft_wc->list);
573 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
575 struct mlx5_ib_cq *cq = to_mcq(ibcq);
576 struct mlx5_ib_qp *cur_qp = NULL;
577 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
578 struct mlx5_core_dev *mdev = dev->mdev;
583 spin_lock_irqsave(&cq->lock, flags);
584 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
585 /* make sure no soft wqe's are waiting */
586 if (unlikely(!list_empty(&cq->wc_list)))
587 soft_polled = poll_soft_wc(cq, num_entries, wc, true);
589 mlx5_ib_poll_sw_comp(cq, num_entries - soft_polled,
590 wc + soft_polled, &npolled);
594 if (unlikely(!list_empty(&cq->wc_list)))
595 soft_polled = poll_soft_wc(cq, num_entries, wc, false);
597 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
598 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled))
603 mlx5_cq_set_ci(&cq->mcq);
605 spin_unlock_irqrestore(&cq->lock, flags);
607 return soft_polled + npolled;
610 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
612 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
613 struct mlx5_ib_cq *cq = to_mcq(ibcq);
614 void __iomem *uar_page = mdev->priv.uar->map;
615 unsigned long irq_flags;
618 spin_lock_irqsave(&cq->lock, irq_flags);
619 if (cq->notify_flags != IB_CQ_NEXT_COMP)
620 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK;
622 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list))
624 spin_unlock_irqrestore(&cq->lock, irq_flags);
626 mlx5_cq_arm(&cq->mcq,
627 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
628 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
629 uar_page, to_mcq(ibcq)->mcq.cons_index);
634 static int alloc_cq_frag_buf(struct mlx5_ib_dev *dev,
635 struct mlx5_ib_cq_buf *buf,
639 struct mlx5_frag_buf *frag_buf = &buf->frag_buf;
640 u8 log_wq_stride = 6 + (cqe_size == 128 ? 1 : 0);
641 u8 log_wq_sz = ilog2(cqe_size);
644 err = mlx5_frag_buf_alloc_node(dev->mdev,
647 dev->mdev->priv.numa_node);
651 mlx5_init_fbc(frag_buf->frags, log_wq_stride, log_wq_sz, &buf->fbc);
653 buf->cqe_size = cqe_size;
660 MLX5_CQE_RES_FORMAT_HASH = 0,
661 MLX5_CQE_RES_FORMAT_CSUM = 1,
662 MLX5_CQE_RES_FORMAT_CSUM_STRIDX = 3,
665 static int mini_cqe_res_format_to_hw(struct mlx5_ib_dev *dev, u8 format)
668 case MLX5_IB_CQE_RES_FORMAT_HASH:
669 return MLX5_CQE_RES_FORMAT_HASH;
670 case MLX5_IB_CQE_RES_FORMAT_CSUM:
671 return MLX5_CQE_RES_FORMAT_CSUM;
672 case MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX:
673 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
674 return MLX5_CQE_RES_FORMAT_CSUM_STRIDX;
681 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
682 struct mlx5_ib_cq *cq, int entries, u32 **cqb,
683 int *cqe_size, int *index, int *inlen)
685 struct mlx5_ib_create_cq ucmd = {};
693 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
694 udata, struct mlx5_ib_ucontext, ibucontext);
696 ucmdlen = udata->inlen < sizeof(ucmd) ?
697 (sizeof(ucmd) - sizeof(ucmd.flags)) : sizeof(ucmd);
699 if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
702 if (ucmdlen == sizeof(ucmd) &&
703 (ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD)))
706 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
709 *cqe_size = ucmd.cqe_size;
712 ib_umem_get(udata, ucmd.buf_addr, entries * ucmd.cqe_size,
713 IB_ACCESS_LOCAL_WRITE, 1);
714 if (IS_ERR(cq->buf.umem)) {
715 err = PTR_ERR(cq->buf.umem);
719 err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &cq->db);
723 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift,
725 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
726 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
728 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
729 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont;
730 *cqb = kvzalloc(*inlen, GFP_KERNEL);
736 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
737 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0);
739 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
740 MLX5_SET(cqc, cqc, log_page_size,
741 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
743 *index = context->bfregi.sys_pages[0];
745 if (ucmd.cqe_comp_en == 1) {
748 if (!((*cqe_size == 128 &&
749 MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) ||
751 MLX5_CAP_GEN(dev->mdev, cqe_compression)))) {
753 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n",
759 mini_cqe_res_format_to_hw(dev,
760 ucmd.cqe_comp_res_format);
761 if (mini_cqe_format < 0) {
762 err = mini_cqe_format;
763 mlx5_ib_dbg(dev, "CQE compression res format %d error: %d\n",
764 ucmd.cqe_comp_res_format, err);
768 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
769 MLX5_SET(cqc, cqc, mini_cqe_res_format, mini_cqe_format);
772 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) {
773 if (*cqe_size != 128 ||
774 !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) {
777 "CQE padding is not supported for CQE size of %dB!\n",
782 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD;
785 MLX5_SET(create_cq_in, *cqb, uid, context->devx_uid);
792 mlx5_ib_db_unmap_user(context, &cq->db);
795 ib_umem_release(cq->buf.umem);
799 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_udata *udata)
801 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
802 udata, struct mlx5_ib_ucontext, ibucontext);
804 mlx5_ib_db_unmap_user(context, &cq->db);
805 ib_umem_release(cq->buf.umem);
808 static void init_cq_frag_buf(struct mlx5_ib_cq *cq,
809 struct mlx5_ib_cq_buf *buf)
813 struct mlx5_cqe64 *cqe64;
815 for (i = 0; i < buf->nent; i++) {
816 cqe = get_cqe(cq, i);
817 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
818 cqe64->op_own = MLX5_CQE_INVALID << 4;
822 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
823 int entries, int cqe_size,
824 u32 **cqb, int *index, int *inlen)
830 err = mlx5_db_alloc(dev->mdev, &cq->db);
834 cq->mcq.set_ci_db = cq->db.db;
835 cq->mcq.arm_db = cq->db.db + 1;
836 cq->mcq.cqe_sz = cqe_size;
838 err = alloc_cq_frag_buf(dev, &cq->buf, entries, cqe_size);
842 init_cq_frag_buf(cq, &cq->buf);
844 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
845 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) *
846 cq->buf.frag_buf.npages;
847 *cqb = kvzalloc(*inlen, GFP_KERNEL);
853 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
854 mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas);
856 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
857 MLX5_SET(cqc, cqc, log_page_size,
858 cq->buf.frag_buf.page_shift -
859 MLX5_ADAPTER_PAGE_SHIFT);
861 *index = dev->mdev->priv.uar->index;
866 free_cq_buf(dev, &cq->buf);
869 mlx5_db_free(dev->mdev, &cq->db);
873 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
875 free_cq_buf(dev, &cq->buf);
876 mlx5_db_free(dev->mdev, &cq->db);
879 static void notify_soft_wc_handler(struct work_struct *work)
881 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq,
884 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
887 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
888 struct ib_udata *udata)
890 struct ib_device *ibdev = ibcq->device;
891 int entries = attr->cqe;
892 int vector = attr->comp_vector;
893 struct mlx5_ib_dev *dev = to_mdev(ibdev);
894 struct mlx5_ib_cq *cq = to_mcq(ibcq);
895 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
896 int uninitialized_var(index);
897 int uninitialized_var(inlen);
906 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))))
909 if (check_cq_create_flags(attr->flags))
912 entries = roundup_pow_of_two(entries + 1);
913 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
916 cq->ibcq.cqe = entries - 1;
917 mutex_init(&cq->resize_mutex);
918 spin_lock_init(&cq->lock);
919 cq->resize_buf = NULL;
920 cq->resize_umem = NULL;
921 cq->create_flags = attr->flags;
922 INIT_LIST_HEAD(&cq->list_send_qp);
923 INIT_LIST_HEAD(&cq->list_recv_qp);
926 err = create_cq_user(dev, udata, cq, entries, &cqb, &cqe_size,
931 cqe_size = cache_line_size() == 128 ? 128 : 64;
932 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
937 INIT_WORK(&cq->notify_work, notify_soft_wc_handler);
940 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
944 cq->cqe_size = cqe_size;
946 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context);
947 MLX5_SET(cqc, cqc, cqe_sz,
948 cqe_sz_to_mlx_sz(cqe_size,
950 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
951 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
952 MLX5_SET(cqc, cqc, uar_page, index);
953 MLX5_SET(cqc, cqc, c_eqn, eqn);
954 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma);
955 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN)
956 MLX5_SET(cqc, cqc, oi, 1);
958 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen, out, sizeof(out));
962 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
965 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp;
967 cq->mcq.comp = mlx5_ib_cq_comp;
968 cq->mcq.event = mlx5_ib_cq_event;
970 INIT_LIST_HEAD(&cq->wc_list);
973 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
983 mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
988 destroy_cq_user(cq, udata);
990 destroy_cq_kernel(dev, cq);
994 void mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata)
996 struct mlx5_ib_dev *dev = to_mdev(cq->device);
997 struct mlx5_ib_cq *mcq = to_mcq(cq);
999 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
1001 destroy_cq_user(mcq, udata);
1003 destroy_cq_kernel(dev, mcq);
1006 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
1008 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
1011 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
1013 struct mlx5_cqe64 *cqe64, *dest64;
1022 /* First we need to find the current producer index, so we
1023 * know where to start cleaning from. It doesn't matter if HW
1024 * adds new entries after this loop -- the QP we're worried
1025 * about is already in RESET, so the new entries won't come
1026 * from our QP and therefore don't need to be checked.
1028 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
1029 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
1032 /* Now sweep backwards through the CQ, removing CQ entries
1033 * that match our QP by copying older entries on top of them.
1035 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
1036 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
1037 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
1038 if (is_equal_rsn(cqe64, rsn)) {
1039 if (srq && (ntohl(cqe64->srqn) & 0xffffff))
1040 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
1042 } else if (nfreed) {
1043 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
1044 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
1045 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
1046 memcpy(dest, cqe, cq->mcq.cqe_sz);
1047 dest64->op_own = owner_bit |
1048 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
1053 cq->mcq.cons_index += nfreed;
1054 /* Make sure update of buffer contents is done before
1055 * updating consumer index.
1058 mlx5_cq_set_ci(&cq->mcq);
1062 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
1067 spin_lock_irq(&cq->lock);
1068 __mlx5_ib_cq_clean(cq, qpn, srq);
1069 spin_unlock_irq(&cq->lock);
1072 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1074 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1075 struct mlx5_ib_cq *mcq = to_mcq(cq);
1078 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
1081 if (cq_period > MLX5_MAX_CQ_PERIOD)
1084 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq,
1085 cq_period, cq_count);
1087 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
1092 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1093 int entries, struct ib_udata *udata, int *npas,
1094 int *page_shift, int *cqe_size)
1096 struct mlx5_ib_resize_cq ucmd;
1097 struct ib_umem *umem;
1101 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
1105 if (ucmd.reserved0 || ucmd.reserved1)
1108 /* check multiplication overflow */
1109 if (ucmd.cqe_size && SIZE_MAX / ucmd.cqe_size <= entries - 1)
1112 umem = ib_umem_get(udata, ucmd.buf_addr,
1113 (size_t)ucmd.cqe_size * entries,
1114 IB_ACCESS_LOCAL_WRITE, 1);
1116 err = PTR_ERR(umem);
1120 mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift,
1123 cq->resize_umem = umem;
1124 *cqe_size = ucmd.cqe_size;
1129 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1130 int entries, int cqe_size)
1134 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1135 if (!cq->resize_buf)
1138 err = alloc_cq_frag_buf(dev, cq->resize_buf, entries, cqe_size);
1142 init_cq_frag_buf(cq, cq->resize_buf);
1147 kfree(cq->resize_buf);
1151 static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1153 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1154 struct mlx5_cqe64 *scqe64;
1155 struct mlx5_cqe64 *dcqe64;
1164 ssize = cq->buf.cqe_size;
1165 dsize = cq->resize_buf->cqe_size;
1166 if (ssize != dsize) {
1167 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1171 i = cq->mcq.cons_index;
1172 scqe = get_sw_cqe(cq, i);
1173 scqe64 = ssize == 64 ? scqe : scqe + 64;
1176 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1180 while (get_cqe_opcode(scqe64) != MLX5_CQE_RESIZE_CQ) {
1181 dcqe = mlx5_frag_buf_get_wqe(&cq->resize_buf->fbc,
1182 (i + 1) & cq->resize_buf->nent);
1183 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1184 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1185 memcpy(dcqe, scqe, dsize);
1186 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1189 scqe = get_sw_cqe(cq, i);
1190 scqe64 = ssize == 64 ? scqe : scqe + 64;
1192 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1196 if (scqe == start_cqe) {
1197 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1202 ++cq->mcq.cons_index;
1206 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1208 struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1209 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1217 int uninitialized_var(cqe_size);
1218 unsigned long flags;
1220 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
1221 pr_info("Firmware does not support resize CQ\n");
1226 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) {
1227 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n",
1229 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz));
1233 entries = roundup_pow_of_two(entries + 1);
1234 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
1237 if (entries == ibcq->cqe + 1)
1240 mutex_lock(&cq->resize_mutex);
1242 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1246 err = resize_kernel(dev, cq, entries, cqe_size);
1248 struct mlx5_frag_buf *frag_buf = &cq->resize_buf->frag_buf;
1250 npas = frag_buf->npages;
1251 page_shift = frag_buf->page_shift;
1258 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) +
1259 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas;
1261 in = kvzalloc(inlen, GFP_KERNEL);
1267 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas);
1269 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
1272 mlx5_fill_page_frag_array(&cq->resize_buf->frag_buf, pas);
1274 MLX5_SET(modify_cq_in, in,
1275 modify_field_select_resize_field_select.resize_field_select.resize_field_select,
1276 MLX5_MODIFY_CQ_MASK_LOG_SIZE |
1277 MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1278 MLX5_MODIFY_CQ_MASK_PG_SIZE);
1280 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
1282 MLX5_SET(cqc, cqc, log_page_size,
1283 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1284 MLX5_SET(cqc, cqc, cqe_sz,
1285 cqe_sz_to_mlx_sz(cqe_size,
1287 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
1288 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1290 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE);
1291 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn);
1293 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
1298 cq->ibcq.cqe = entries - 1;
1299 ib_umem_release(cq->buf.umem);
1300 cq->buf.umem = cq->resize_umem;
1301 cq->resize_umem = NULL;
1303 struct mlx5_ib_cq_buf tbuf;
1306 spin_lock_irqsave(&cq->lock, flags);
1307 if (cq->resize_buf) {
1308 err = copy_resize_cqes(cq);
1311 cq->buf = *cq->resize_buf;
1312 kfree(cq->resize_buf);
1313 cq->resize_buf = NULL;
1317 cq->ibcq.cqe = entries - 1;
1318 spin_unlock_irqrestore(&cq->lock, flags);
1320 free_cq_buf(dev, &tbuf);
1322 mutex_unlock(&cq->resize_mutex);
1331 ib_umem_release(cq->resize_umem);
1333 free_cq_buf(dev, cq->resize_buf);
1334 cq->resize_buf = NULL;
1337 mutex_unlock(&cq->resize_mutex);
1341 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq)
1343 struct mlx5_ib_cq *cq;
1349 return cq->cqe_size;
1352 /* Called from atomic context */
1353 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc)
1355 struct mlx5_ib_wc *soft_wc;
1356 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1357 unsigned long flags;
1359 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC);
1364 spin_lock_irqsave(&cq->lock, flags);
1365 list_add_tail(&soft_wc->list, &cq->wc_list);
1366 if (cq->notify_flags == IB_CQ_NEXT_COMP ||
1367 wc->status != IB_WC_SUCCESS) {
1368 cq->notify_flags = 0;
1369 schedule_work(&cq->notify_work);
1371 spin_unlock_irqrestore(&cq->lock, flags);