drivers/infiniband/hw/hns/hns_roce_device.h

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _HNS_ROCE_DEVICE_H
  34 #define _HNS_ROCE_DEVICE_H
  35
  36 #include <rdma/ib_verbs.h>
  37
  38 #define DRV_NAME "hns_roce"
  39
  40 /* hip08 is a pci device, it includes two version according pci version id */
  41 #define PCI_REVISION_ID_HIP08_A                 0x20
  42 #define PCI_REVISION_ID_HIP08_B                 0x21
  43
  44 #define HNS_ROCE_HW_VER1        ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
  45
  46 #define HNS_ROCE_MAX_MSG_LEN                    0x80000000
  47
  48 #define HNS_ROCE_ALOGN_UP(a, b) ((((a) + (b) - 1) / (b)) * (b))
  49
  50 #define HNS_ROCE_IB_MIN_SQ_STRIDE               6
  51
  52 #define HNS_ROCE_BA_SIZE                        (32 * 4096)
  53
  54 #define BA_BYTE_LEN                             8
  55
  56 #define BITS_PER_BYTE                           8
  57
  58 /* Hardware specification only for v1 engine */
  59 #define HNS_ROCE_MIN_CQE_NUM                    0x40
  60 #define HNS_ROCE_MIN_WQE_NUM                    0x20
  61
  62 /* Hardware specification only for v1 engine */
  63 #define HNS_ROCE_MAX_INNER_MTPT_NUM             0x7
  64 #define HNS_ROCE_MAX_MTPT_PBL_NUM               0x100000
  65 #define HNS_ROCE_MAX_SGE_NUM                    2
  66
  67 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS        20
  68 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT   \
  69         (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
  70 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT             0x2
  71 #define HNS_ROCE_MIN_CQE_CNT                    16
  72
  73 #define HNS_ROCE_MAX_IRQ_NUM                    128
  74
  75 #define HNS_ROCE_SGE_IN_WQE                     2
  76 #define HNS_ROCE_SGE_SHIFT                      4
  77
  78 #define EQ_ENABLE                               1
  79 #define EQ_DISABLE                              0
  80
  81 #define HNS_ROCE_CEQ                            0
  82 #define HNS_ROCE_AEQ                            1
  83
  84 #define HNS_ROCE_CEQ_ENTRY_SIZE                 0x4
  85 #define HNS_ROCE_AEQ_ENTRY_SIZE                 0x10
  86
  87 /* 4G/4K = 1M */
  88 #define HNS_ROCE_SL_SHIFT                       28
  89 #define HNS_ROCE_TCLASS_SHIFT                   20
  90 #define HNS_ROCE_FLOW_LABEL_MASK                0xfffff
  91
  92 #define HNS_ROCE_MAX_PORTS                      6
  93 #define HNS_ROCE_MAX_GID_NUM                    16
  94 #define HNS_ROCE_GID_SIZE                       16
  95 #define HNS_ROCE_SGE_SIZE                       16
  96
  97 #define HNS_ROCE_HOP_NUM_0                      0xff
  98
  99 #define BITMAP_NO_RR                            0
 100 #define BITMAP_RR                               1
 101
 102 #define MR_TYPE_MR                              0x00
 103 #define MR_TYPE_FRMR                            0x01
 104 #define MR_TYPE_DMA                             0x03
 105
 106 #define HNS_ROCE_FRMR_MAX_PA                    512
 107
 108 #define PKEY_ID                                 0xffff
 109 #define GUID_LEN                                8
 110 #define NODE_DESC_SIZE                          64
 111 #define DB_REG_OFFSET                           0x1000
 112
 113 #define SERV_TYPE_RC                            0
 114 #define SERV_TYPE_RD                            1
 115 #define SERV_TYPE_UC                            2
 116 #define SERV_TYPE_UD                            3
 117
 118 /* Configure to HW for PAGE_SIZE larger than 4KB */
 119 #define PG_SHIFT_OFFSET                         (PAGE_SHIFT - 12)
 120
 121 #define PAGES_SHIFT_8                           8
 122 #define PAGES_SHIFT_16                          16
 123 #define PAGES_SHIFT_24                          24
 124 #define PAGES_SHIFT_32                          32
 125
 126 #define HNS_ROCE_PCI_BAR_NUM                    2
 127
 128 #define HNS_ROCE_IDX_QUE_ENTRY_SZ               4
 129 #define SRQ_DB_REG                              0x230
 130
 131 enum {
 132         HNS_ROCE_SUPPORT_RQ_RECORD_DB = 1 << 0,
 133         HNS_ROCE_SUPPORT_SQ_RECORD_DB = 1 << 1,
 134 };
 135
 136 enum {
 137         HNS_ROCE_SUPPORT_CQ_RECORD_DB = 1 << 0,
 138 };
 139
 140 enum hns_roce_qp_state {
 141         HNS_ROCE_QP_STATE_RST,
 142         HNS_ROCE_QP_STATE_INIT,
 143         HNS_ROCE_QP_STATE_RTR,
 144         HNS_ROCE_QP_STATE_RTS,
 145         HNS_ROCE_QP_STATE_SQD,
 146         HNS_ROCE_QP_STATE_ERR,
 147         HNS_ROCE_QP_NUM_STATE,
 148 };
 149
 150 enum hns_roce_event {
 151         HNS_ROCE_EVENT_TYPE_PATH_MIG                  = 0x01,
 152         HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED           = 0x02,
 153         HNS_ROCE_EVENT_TYPE_COMM_EST                  = 0x03,
 154         HNS_ROCE_EVENT_TYPE_SQ_DRAINED                = 0x04,
 155         HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR            = 0x05,
 156         HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR    = 0x06,
 157         HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR     = 0x07,
 158         HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH           = 0x08,
 159         HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH        = 0x09,
 160         HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR           = 0x0a,
 161         HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR           = 0x0b,
 162         HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW               = 0x0c,
 163         HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID             = 0x0d,
 164         HNS_ROCE_EVENT_TYPE_PORT_CHANGE               = 0x0f,
 165         /* 0x10 and 0x11 is unused in currently application case */
 166         HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,
 167         HNS_ROCE_EVENT_TYPE_MB                        = 0x13,
 168         HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW              = 0x14,
 169         HNS_ROCE_EVENT_TYPE_FLR                       = 0x15,
 170 };
 171
 172 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
 173 enum {
 174         HNS_ROCE_LWQCE_QPC_ERROR                = 1,
 175         HNS_ROCE_LWQCE_MTU_ERROR                = 2,
 176         HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR        = 3,
 177         HNS_ROCE_LWQCE_WQE_ADDR_ERROR           = 4,
 178         HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR       = 5,
 179         HNS_ROCE_LWQCE_SL_ERROR                 = 6,
 180         HNS_ROCE_LWQCE_PORT_ERROR               = 7,
 181 };
 182
 183 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */
 184 enum {
 185         HNS_ROCE_LAVWQE_R_KEY_VIOLATION         = 1,
 186         HNS_ROCE_LAVWQE_LENGTH_ERROR            = 2,
 187         HNS_ROCE_LAVWQE_VA_ERROR                = 3,
 188         HNS_ROCE_LAVWQE_PD_ERROR                = 4,
 189         HNS_ROCE_LAVWQE_RW_ACC_ERROR            = 5,
 190         HNS_ROCE_LAVWQE_KEY_STATE_ERROR         = 6,
 191         HNS_ROCE_LAVWQE_MR_OPERATION_ERROR      = 7,
 192 };
 193
 194 /* DOORBELL overflow subtype */
 195 enum {
 196         HNS_ROCE_DB_SUBTYPE_SDB_OVF             = 1,
 197         HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF         = 2,
 198         HNS_ROCE_DB_SUBTYPE_ODB_OVF             = 3,
 199         HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF         = 4,
 200         HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP         = 5,
 201         HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP         = 6,
 202 };
 203
 204 enum {
 205         /* RQ&SRQ related operations */
 206         HNS_ROCE_OPCODE_SEND_DATA_RECEIVE       = 0x06,
 207         HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE   = 0x07,
 208 };
 209
 210 enum {
 211         HNS_ROCE_CAP_FLAG_REREG_MR              = BIT(0),
 212         HNS_ROCE_CAP_FLAG_ROCE_V1_V2            = BIT(1),
 213         HNS_ROCE_CAP_FLAG_RQ_INLINE             = BIT(2),
 214         HNS_ROCE_CAP_FLAG_RECORD_DB             = BIT(3),
 215         HNS_ROCE_CAP_FLAG_SQ_RECORD_DB          = BIT(4),
 216         HNS_ROCE_CAP_FLAG_SRQ                   = BIT(5),
 217         HNS_ROCE_CAP_FLAG_MW                    = BIT(7),
 218         HNS_ROCE_CAP_FLAG_FRMR                  = BIT(8),
 219         HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL          = BIT(9),
 220         HNS_ROCE_CAP_FLAG_ATOMIC                = BIT(10),
 221 };
 222
 223 enum hns_roce_mtt_type {
 224         MTT_TYPE_WQE,
 225         MTT_TYPE_CQE,
 226         MTT_TYPE_SRQWQE,
 227         MTT_TYPE_IDX
 228 };
 229
 230 #define HNS_ROCE_DB_TYPE_COUNT                  2
 231 #define HNS_ROCE_DB_UNIT_SIZE                   4
 232
 233 enum {
 234         HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
 235 };
 236
 237 enum hns_roce_reset_stage {
 238         HNS_ROCE_STATE_NON_RST,
 239         HNS_ROCE_STATE_RST_BEF_DOWN,
 240         HNS_ROCE_STATE_RST_DOWN,
 241         HNS_ROCE_STATE_RST_UNINIT,
 242         HNS_ROCE_STATE_RST_INIT,
 243         HNS_ROCE_STATE_RST_INITED,
 244 };
 245
 246 enum hns_roce_instance_state {
 247         HNS_ROCE_STATE_NON_INIT,
 248         HNS_ROCE_STATE_INIT,
 249         HNS_ROCE_STATE_INITED,
 250         HNS_ROCE_STATE_UNINIT,
 251 };
 252
 253 enum {
 254         HNS_ROCE_RST_DIRECT_RETURN              = 0,
 255 };
 256
 257 enum {
 258         CMD_RST_PRC_OTHERS,
 259         CMD_RST_PRC_SUCCESS,
 260         CMD_RST_PRC_EBUSY,
 261 };
 262
 263 #define HNS_ROCE_CMD_SUCCESS                    1
 264
 265 #define HNS_ROCE_PORT_DOWN                      0
 266 #define HNS_ROCE_PORT_UP                        1
 267
 268 #define HNS_ROCE_MTT_ENTRY_PER_SEG              8
 269
 270 #define PAGE_ADDR_SHIFT                         12
 271
 272 struct hns_roce_uar {
 273         u64             pfn;
 274         unsigned long   index;
 275         unsigned long   logic_idx;
 276 };
 277
 278 struct hns_roce_ucontext {
 279         struct ib_ucontext      ibucontext;
 280         struct hns_roce_uar     uar;
 281         struct list_head        page_list;
 282         struct mutex            page_mutex;
 283 };
 284
 285 struct hns_roce_pd {
 286         struct ib_pd            ibpd;
 287         unsigned long           pdn;
 288 };
 289
 290 struct hns_roce_bitmap {
 291         /* Bitmap Traversal last a bit which is 1 */
 292         unsigned long           last;
 293         unsigned long           top;
 294         unsigned long           max;
 295         unsigned long           reserved_top;
 296         unsigned long           mask;
 297         spinlock_t              lock;
 298         unsigned long           *table;
 299 };
 300
 301 /* Order bitmap length -- bit num compute formula: 1 << (max_order - order) */
 302 /* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */
 303 /* Every bit repesent to a partner free/used status in bitmap */
 304 /*
 305  * Initial, bits of other bitmap are all 0 except that a bit of max_order is 1
 306  * Bit = 1 represent to idle and available; bit = 0: not available
 307  */
 308 struct hns_roce_buddy {
 309         /* Members point to every order level bitmap */
 310         unsigned long **bits;
 311         /* Represent to avail bits of the order level bitmap */
 312         u32            *num_free;
 313         int             max_order;
 314         spinlock_t      lock;
 315 };
 316
 317 /* For Hardware Entry Memory */
 318 struct hns_roce_hem_table {
 319         /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
 320         u32             type;
 321         /* HEM array elment num */
 322         unsigned long   num_hem;
 323         /* HEM entry record obj total num */
 324         unsigned long   num_obj;
 325         /*Single obj size */
 326         unsigned long   obj_size;
 327         unsigned long   table_chunk_size;
 328         int             lowmem;
 329         struct mutex    mutex;
 330         struct hns_roce_hem **hem;
 331         u64             **bt_l1;
 332         dma_addr_t      *bt_l1_dma_addr;
 333         u64             **bt_l0;
 334         dma_addr_t      *bt_l0_dma_addr;
 335 };
 336
 337 struct hns_roce_mtt {
 338         unsigned long           first_seg;
 339         int                     order;
 340         int                     page_shift;
 341         enum hns_roce_mtt_type  mtt_type;
 342 };
 343
 344 struct hns_roce_buf_region {
 345         int offset; /* page offset */
 346         u32 count; /* page count*/
 347         int hopnum; /* addressing hop num */
 348 };
 349
 350 #define HNS_ROCE_MAX_BT_REGION  3
 351 #define HNS_ROCE_MAX_BT_LEVEL   3
 352 struct hns_roce_hem_list {
 353         struct list_head root_bt;
 354         /* link all bt dma mem by hop config */
 355         struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
 356         struct list_head btm_bt; /* link all bottom bt in @mid_bt */
 357         dma_addr_t root_ba; /* pointer to the root ba table */
 358         int bt_pg_shift;
 359 };
 360
 361 /* memory translate region */
 362 struct hns_roce_mtr {
 363         struct hns_roce_hem_list hem_list;
 364         int buf_pg_shift;
 365 };
 366
 367 struct hns_roce_mw {
 368         struct ib_mw            ibmw;
 369         u32                     pdn;
 370         u32                     rkey;
 371         int                     enabled; /* MW's active status */
 372         u32                     pbl_hop_num;
 373         u32                     pbl_ba_pg_sz;
 374         u32                     pbl_buf_pg_sz;
 375 };
 376
 377 /* Only support 4K page size for mr register */
 378 #define MR_SIZE_4K 0
 379
 380 struct hns_roce_mr {
 381         struct ib_mr            ibmr;
 382         struct ib_umem          *umem;
 383         u64                     iova; /* MR's virtual orignal addr */
 384         u64                     size; /* Address range of MR */
 385         u32                     key; /* Key of MR */
 386         u32                     pd;   /* PD num of MR */
 387         u32                     access;/* Access permission of MR */
 388         u32                     npages;
 389         int                     enabled; /* MR's active status */
 390         int                     type;   /* MR's register type */
 391         u64                     *pbl_buf;/* MR's PBL space */
 392         dma_addr_t              pbl_dma_addr;   /* MR's PBL space PA */
 393         u32                     pbl_size;/* PA number in the PBL */
 394         u64                     pbl_ba;/* page table address */
 395         u32                     l0_chunk_last_num;/* L0 last number */
 396         u32                     l1_chunk_last_num;/* L1 last number */
 397         u64                     **pbl_bt_l2;/* PBL BT L2 */
 398         u64                     **pbl_bt_l1;/* PBL BT L1 */
 399         u64                     *pbl_bt_l0;/* PBL BT L0 */
 400         dma_addr_t              *pbl_l2_dma_addr;/* PBL BT L2 dma addr */
 401         dma_addr_t              *pbl_l1_dma_addr;/* PBL BT L1 dma addr */
 402         dma_addr_t              pbl_l0_dma_addr;/* PBL BT L0 dma addr */
 403         u32                     pbl_ba_pg_sz;/* BT chunk page size */
 404         u32                     pbl_buf_pg_sz;/* buf chunk page size */
 405         u32                     pbl_hop_num;/* multi-hop number */
 406 };
 407
 408 struct hns_roce_mr_table {
 409         struct hns_roce_bitmap          mtpt_bitmap;
 410         struct hns_roce_buddy           mtt_buddy;
 411         struct hns_roce_hem_table       mtt_table;
 412         struct hns_roce_hem_table       mtpt_table;
 413         struct hns_roce_buddy           mtt_cqe_buddy;
 414         struct hns_roce_hem_table       mtt_cqe_table;
 415         struct hns_roce_buddy           mtt_srqwqe_buddy;
 416         struct hns_roce_hem_table       mtt_srqwqe_table;
 417         struct hns_roce_buddy           mtt_idx_buddy;
 418         struct hns_roce_hem_table       mtt_idx_table;
 419 };
 420
 421 struct hns_roce_wq {
 422         u64             *wrid;     /* Work request ID */
 423         spinlock_t      lock;
 424         int             wqe_cnt;  /* WQE num */
 425         u32             max_post;
 426         int             max_gs;
 427         int             offset;
 428         int             wqe_shift;/* WQE size */
 429         u32             head;
 430         u32             tail;
 431         void __iomem    *db_reg_l;
 432 };
 433
 434 struct hns_roce_sge {
 435         int             sge_cnt;  /* SGE num */
 436         int             offset;
 437         int             sge_shift;/* SGE size */
 438 };
 439
 440 struct hns_roce_buf_list {
 441         void            *buf;
 442         dma_addr_t      map;
 443 };
 444
 445 struct hns_roce_buf {
 446         struct hns_roce_buf_list        direct;
 447         struct hns_roce_buf_list        *page_list;
 448         int                             nbufs;
 449         u32                             npages;
 450         int                             page_shift;
 451 };
 452
 453 struct hns_roce_db_pgdir {
 454         struct list_head        list;
 455         DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
 456         DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
 457         unsigned long           *bits[HNS_ROCE_DB_TYPE_COUNT];
 458         u32                     *page;
 459         dma_addr_t              db_dma;
 460 };
 461
 462 struct hns_roce_user_db_page {
 463         struct list_head        list;
 464         struct ib_umem          *umem;
 465         unsigned long           user_virt;
 466         refcount_t              refcount;
 467 };
 468
 469 struct hns_roce_db {
 470         u32             *db_record;
 471         union {
 472                 struct hns_roce_db_pgdir *pgdir;
 473                 struct hns_roce_user_db_page *user_page;
 474         } u;
 475         dma_addr_t      dma;
 476         void            *virt_addr;
 477         int             index;
 478         int             order;
 479 };
 480
 481 struct hns_roce_cq_buf {
 482         struct hns_roce_buf hr_buf;
 483         struct hns_roce_mtt hr_mtt;
 484 };
 485
 486 struct hns_roce_cq {
 487         struct ib_cq                    ib_cq;
 488         struct hns_roce_cq_buf          hr_buf;
 489         struct hns_roce_db              db;
 490         u8                              db_en;
 491         spinlock_t                      lock;
 492         struct ib_umem                  *umem;
 493         void (*comp)(struct hns_roce_cq *cq);
 494         void (*event)(struct hns_roce_cq *cq, enum hns_roce_event event_type);
 495
 496         struct hns_roce_uar             *uar;
 497         u32                             cq_depth;
 498         u32                             cons_index;
 499         u32                             *set_ci_db;
 500         void __iomem                    *cq_db_l;
 501         u16                             *tptr_addr;
 502         int                             arm_sn;
 503         unsigned long                   cqn;
 504         u32                             vector;
 505         atomic_t                        refcount;
 506         struct completion               free;
 507 };
 508
 509 struct hns_roce_idx_que {
 510         struct hns_roce_buf             idx_buf;
 511         int                             entry_sz;
 512         u32                             buf_size;
 513         struct ib_umem                  *umem;
 514         struct hns_roce_mtt             mtt;
 515         unsigned long                   *bitmap;
 516 };
 517
 518 struct hns_roce_srq {
 519         struct ib_srq           ibsrq;
 520         void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
 521         unsigned long           srqn;
 522         int                     max;
 523         int                     max_gs;
 524         int                     wqe_shift;
 525         void __iomem            *db_reg_l;
 526
 527         atomic_t                refcount;
 528         struct completion       free;
 529
 530         struct hns_roce_buf     buf;
 531         u64                    *wrid;
 532         struct ib_umem         *umem;
 533         struct hns_roce_mtt     mtt;
 534         struct hns_roce_idx_que idx_que;
 535         spinlock_t              lock;
 536         int                     head;
 537         int                     tail;
 538         u16                     wqe_ctr;
 539         struct mutex            mutex;
 540 };
 541
 542 struct hns_roce_uar_table {
 543         struct hns_roce_bitmap bitmap;
 544 };
 545
 546 struct hns_roce_qp_table {
 547         struct hns_roce_bitmap          bitmap;
 548         struct hns_roce_hem_table       qp_table;
 549         struct hns_roce_hem_table       irrl_table;
 550         struct hns_roce_hem_table       trrl_table;
 551         struct hns_roce_hem_table       sccc_table;
 552         struct mutex                    scc_mutex;
 553 };
 554
 555 struct hns_roce_cq_table {
 556         struct hns_roce_bitmap          bitmap;
 557         struct xarray                   array;
 558         struct hns_roce_hem_table       table;
 559 };
 560
 561 struct hns_roce_srq_table {
 562         struct hns_roce_bitmap          bitmap;
 563         struct xarray                   xa;
 564         struct hns_roce_hem_table       table;
 565 };
 566
 567 struct hns_roce_raq_table {
 568         struct hns_roce_buf_list        *e_raq_buf;
 569 };
 570
 571 struct hns_roce_av {
 572         __le32      port_pd;
 573         u8          gid_index;
 574         u8          stat_rate;
 575         u8          hop_limit;
 576         __le32      sl_tclass_flowlabel;
 577         u8          dgid[HNS_ROCE_GID_SIZE];
 578         u8          mac[ETH_ALEN];
 579         __le16      vlan;
 580         bool        vlan_en;
 581 };
 582
 583 struct hns_roce_ah {
 584         struct ib_ah            ibah;
 585         struct hns_roce_av      av;
 586 };
 587
 588 struct hns_roce_cmd_context {
 589         struct completion       done;
 590         int                     result;
 591         int                     next;
 592         u64                     out_param;
 593         u16                     token;
 594 };
 595
 596 struct hns_roce_cmdq {
 597         struct dma_pool         *pool;
 598         struct mutex            hcr_mutex;
 599         struct semaphore        poll_sem;
 600         /*
 601          * Event mode: cmd register mutex protection,
 602          * ensure to not exceed max_cmds and user use limit region
 603          */
 604         struct semaphore        event_sem;
 605         int                     max_cmds;
 606         spinlock_t              context_lock;
 607         int                     free_head;
 608         struct hns_roce_cmd_context *context;
 609         /*
 610          * Result of get integer part
 611          * which max_comds compute according a power of 2
 612          */
 613         u16                     token_mask;
 614         /*
 615          * Process whether use event mode, init default non-zero
 616          * After the event queue of cmd event ready,
 617          * can switch into event mode
 618          * close device, switch into poll mode(non event mode)
 619          */
 620         u8                      use_events;
 621         u8                      toggle;
 622 };
 623
 624 struct hns_roce_cmd_mailbox {
 625         void                   *buf;
 626         dma_addr_t              dma;
 627 };
 628
 629 struct hns_roce_dev;
 630
 631 struct hns_roce_rinl_sge {
 632         void                    *addr;
 633         u32                     len;
 634 };
 635
 636 struct hns_roce_rinl_wqe {
 637         struct hns_roce_rinl_sge *sg_list;
 638         u32                      sge_cnt;
 639 };
 640
 641 struct hns_roce_rinl_buf {
 642         struct hns_roce_rinl_wqe *wqe_list;
 643         u32                      wqe_cnt;
 644 };
 645
 646 struct hns_roce_qp {
 647         struct ib_qp            ibqp;
 648         struct hns_roce_buf     hr_buf;
 649         struct hns_roce_wq      rq;
 650         struct hns_roce_db      rdb;
 651         struct hns_roce_db      sdb;
 652         u8                      rdb_en;
 653         u8                      sdb_en;
 654         u32                     doorbell_qpn;
 655         __le32                  sq_signal_bits;
 656         u32                     sq_next_wqe;
 657         int                     sq_max_wqes_per_wr;
 658         int                     sq_spare_wqes;
 659         struct hns_roce_wq      sq;
 660
 661         struct ib_umem          *umem;
 662         struct hns_roce_mtt     mtt;
 663         struct hns_roce_mtr     mtr;
 664
 665         /* this define must less than HNS_ROCE_MAX_BT_REGION */
 666 #define HNS_ROCE_WQE_REGION_MAX  3
 667         struct hns_roce_buf_region regions[HNS_ROCE_WQE_REGION_MAX];
 668         int                     region_cnt;
 669         int                     wqe_bt_pg_shift;
 670
 671         u32                     buff_size;
 672         struct mutex            mutex;
 673         u8                      port;
 674         u8                      phy_port;
 675         u8                      sl;
 676         u8                      resp_depth;
 677         u8                      state;
 678         u32                     access_flags;
 679         u32                     atomic_rd_en;
 680         u32                     pkey_index;
 681         u32                     qkey;
 682         void                    (*event)(struct hns_roce_qp *qp,
 683                                          enum hns_roce_event event_type);
 684         unsigned long           qpn;
 685
 686         atomic_t                refcount;
 687         struct completion       free;
 688
 689         struct hns_roce_sge     sge;
 690         u32                     next_sge;
 691
 692         struct hns_roce_rinl_buf rq_inl_buf;
 693 };
 694
 695 struct hns_roce_sqp {
 696         struct hns_roce_qp      hr_qp;
 697 };
 698
 699 struct hns_roce_ib_iboe {
 700         spinlock_t              lock;
 701         struct net_device      *netdevs[HNS_ROCE_MAX_PORTS];
 702         struct notifier_block   nb;
 703         u8                      phy_port[HNS_ROCE_MAX_PORTS];
 704 };
 705
 706 enum {
 707         HNS_ROCE_EQ_STAT_INVALID  = 0,
 708         HNS_ROCE_EQ_STAT_VALID    = 2,
 709 };
 710
 711 struct hns_roce_ceqe {
 712         u32                     comp;
 713 };
 714
 715 struct hns_roce_aeqe {
 716         __le32 asyn;
 717         union {
 718                 struct {
 719                         __le32 qp;
 720                         u32 rsv0;
 721                         u32 rsv1;
 722                 } qp_event;
 723
 724                 struct {
 725                         __le32 srq;
 726                         u32 rsv0;
 727                         u32 rsv1;
 728                 } srq_event;
 729
 730                 struct {
 731                         __le32 cq;
 732                         u32 rsv0;
 733                         u32 rsv1;
 734                 } cq_event;
 735
 736                 struct {
 737                         __le32 ceqe;
 738                         u32 rsv0;
 739                         u32 rsv1;
 740                 } ce_event;
 741
 742                 struct {
 743                         __le64  out_param;
 744                         __le16  token;
 745                         u8      status;
 746                         u8      rsv0;
 747                 } __packed cmd;
 748          } event;
 749 };
 750
 751 struct hns_roce_eq {
 752         struct hns_roce_dev             *hr_dev;
 753         void __iomem                    *doorbell;
 754
 755         int                             type_flag;/* Aeq:1 ceq:0 */
 756         int                             eqn;
 757         u32                             entries;
 758         int                             log_entries;
 759         int                             eqe_size;
 760         int                             irq;
 761         int                             log_page_size;
 762         int                             cons_index;
 763         struct hns_roce_buf_list        *buf_list;
 764         int                             over_ignore;
 765         int                             coalesce;
 766         int                             arm_st;
 767         u64                             eqe_ba;
 768         int                             eqe_ba_pg_sz;
 769         int                             eqe_buf_pg_sz;
 770         int                             hop_num;
 771         u64                             *bt_l0; /* Base address table for L0 */
 772         u64                             **bt_l1; /* Base address table for L1 */
 773         u64                             **buf;
 774         dma_addr_t                      l0_dma;
 775         dma_addr_t                      *l1_dma;
 776         dma_addr_t                      *buf_dma;
 777         u32                             l0_last_num; /* L0 last chunk num */
 778         u32                             l1_last_num; /* L1 last chunk num */
 779         int                             eq_max_cnt;
 780         int                             eq_period;
 781         int                             shift;
 782         dma_addr_t                      cur_eqe_ba;
 783         dma_addr_t                      nxt_eqe_ba;
 784         int                             event_type;
 785         int                             sub_type;
 786 };
 787
 788 struct hns_roce_eq_table {
 789         struct hns_roce_eq      *eq;
 790         void __iomem            **eqc_base; /* only for hw v1 */
 791 };
 792
 793 struct hns_roce_caps {
 794         u64             fw_ver;
 795         u8              num_ports;
 796         int             gid_table_len[HNS_ROCE_MAX_PORTS];
 797         int             pkey_table_len[HNS_ROCE_MAX_PORTS];
 798         int             local_ca_ack_delay;
 799         int             num_uars;
 800         u32             phy_num_uars;
 801         u32             max_sq_sg;      /* 2 */
 802         u32             max_sq_inline;  /* 32 */
 803         u32             max_rq_sg;      /* 2 */
 804         u32             max_extend_sg;
 805         int             num_qps;        /* 256k */
 806         int             reserved_qps;
 807         int             num_qpc_timer;
 808         int             num_cqc_timer;
 809         u32             max_srq_sg;
 810         int             num_srqs;
 811         u32             max_wqes;       /* 16k */
 812         u32             max_srqs;
 813         u32             max_srq_wrs;
 814         u32             max_srq_sges;
 815         u32             max_sq_desc_sz; /* 64 */
 816         u32             max_rq_desc_sz; /* 64 */
 817         u32             max_srq_desc_sz;
 818         int             max_qp_init_rdma;
 819         int             max_qp_dest_rdma;
 820         int             num_cqs;
 821         int             max_cqes;
 822         int             min_cqes;
 823         u32             min_wqes;
 824         int             reserved_cqs;
 825         int             reserved_srqs;
 826         u32             max_srqwqes;
 827         int             num_aeq_vectors;        /* 1 */
 828         int             num_comp_vectors;
 829         int             num_other_vectors;
 830         int             num_mtpts;
 831         u32             num_mtt_segs;
 832         u32             num_cqe_segs;
 833         u32             num_srqwqe_segs;
 834         u32             num_idx_segs;
 835         int             reserved_mrws;
 836         int             reserved_uars;
 837         int             num_pds;
 838         int             reserved_pds;
 839         u32             mtt_entry_sz;
 840         u32             cq_entry_sz;
 841         u32             page_size_cap;
 842         u32             reserved_lkey;
 843         int             mtpt_entry_sz;
 844         int             qpc_entry_sz;
 845         int             irrl_entry_sz;
 846         int             trrl_entry_sz;
 847         int             cqc_entry_sz;
 848         int             sccc_entry_sz;
 849         int             qpc_timer_entry_sz;
 850         int             cqc_timer_entry_sz;
 851         int             srqc_entry_sz;
 852         int             idx_entry_sz;
 853         u32             pbl_ba_pg_sz;
 854         u32             pbl_buf_pg_sz;
 855         u32             pbl_hop_num;
 856         int             aeqe_depth;
 857         int             ceqe_depth;
 858         enum ib_mtu     max_mtu;
 859         u32             qpc_bt_num;
 860         u32             qpc_timer_bt_num;
 861         u32             srqc_bt_num;
 862         u32             cqc_bt_num;
 863         u32             cqc_timer_bt_num;
 864         u32             mpt_bt_num;
 865         u32             sccc_bt_num;
 866         u32             qpc_ba_pg_sz;
 867         u32             qpc_buf_pg_sz;
 868         u32             qpc_hop_num;
 869         u32             srqc_ba_pg_sz;
 870         u32             srqc_buf_pg_sz;
 871         u32             srqc_hop_num;
 872         u32             cqc_ba_pg_sz;
 873         u32             cqc_buf_pg_sz;
 874         u32             cqc_hop_num;
 875         u32             mpt_ba_pg_sz;
 876         u32             mpt_buf_pg_sz;
 877         u32             mpt_hop_num;
 878         u32             mtt_ba_pg_sz;
 879         u32             mtt_buf_pg_sz;
 880         u32             mtt_hop_num;
 881         u32             wqe_sq_hop_num;
 882         u32             wqe_sge_hop_num;
 883         u32             wqe_rq_hop_num;
 884         u32             sccc_ba_pg_sz;
 885         u32             sccc_buf_pg_sz;
 886         u32             sccc_hop_num;
 887         u32             qpc_timer_ba_pg_sz;
 888         u32             qpc_timer_buf_pg_sz;
 889         u32             qpc_timer_hop_num;
 890         u32             cqc_timer_ba_pg_sz;
 891         u32             cqc_timer_buf_pg_sz;
 892         u32             cqc_timer_hop_num;
 893         u32             cqe_ba_pg_sz;
 894         u32             cqe_buf_pg_sz;
 895         u32             cqe_hop_num;
 896         u32             srqwqe_ba_pg_sz;
 897         u32             srqwqe_buf_pg_sz;
 898         u32             srqwqe_hop_num;
 899         u32             idx_ba_pg_sz;
 900         u32             idx_buf_pg_sz;
 901         u32             idx_hop_num;
 902         u32             eqe_ba_pg_sz;
 903         u32             eqe_buf_pg_sz;
 904         u32             eqe_hop_num;
 905         u32             sl_num;
 906         u32             tsq_buf_pg_sz;
 907         u32             tpq_buf_pg_sz;
 908         u32             chunk_sz;       /* chunk size in non multihop mode*/
 909         u64             flags;
 910 };
 911
 912 struct hns_roce_work {
 913         struct hns_roce_dev *hr_dev;
 914         struct work_struct work;
 915         u32 qpn;
 916         u32 cqn;
 917         int event_type;
 918         int sub_type;
 919 };
 920
 921 struct hns_roce_dfx_hw {
 922         int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
 923                               int *buffer);
 924 };
 925
 926 struct hns_roce_hw {
 927         int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
 928         int (*cmq_init)(struct hns_roce_dev *hr_dev);
 929         void (*cmq_exit)(struct hns_roce_dev *hr_dev);
 930         int (*hw_profile)(struct hns_roce_dev *hr_dev);
 931         int (*hw_init)(struct hns_roce_dev *hr_dev);
 932         void (*hw_exit)(struct hns_roce_dev *hr_dev);
 933         int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
 934                          u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
 935                          u16 token, int event);
 936         int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout);
 937         int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev);
 938         int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
 939                        const union ib_gid *gid, const struct ib_gid_attr *attr);
 940         int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
 941         void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
 942                         enum ib_mtu mtu);
 943         int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr,
 944                           unsigned long mtpt_idx);
 945         int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
 946                                 struct hns_roce_mr *mr, int flags, u32 pdn,
 947                                 int mr_access_flags, u64 iova, u64 size,
 948                                 void *mb_buf);
 949         int (*frmr_write_mtpt)(void *mb_buf, struct hns_roce_mr *mr);
 950         int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
 951         void (*write_cqc)(struct hns_roce_dev *hr_dev,
 952                           struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
 953                           dma_addr_t dma_handle, int nent, u32 vector);
 954         int (*set_hem)(struct hns_roce_dev *hr_dev,
 955                        struct hns_roce_hem_table *table, int obj, int step_idx);
 956         int (*clear_hem)(struct hns_roce_dev *hr_dev,
 957                          struct hns_roce_hem_table *table, int obj,
 958                          int step_idx);
 959         int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
 960                         int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
 961         int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
 962                          int attr_mask, enum ib_qp_state cur_state,
 963                          enum ib_qp_state new_state);
 964         int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata);
 965         int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
 966                          struct hns_roce_qp *hr_qp);
 967         int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr,
 968                          const struct ib_send_wr **bad_wr);
 969         int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr,
 970                          const struct ib_recv_wr **bad_recv_wr);
 971         int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 972         int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 973         int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr,
 974                         struct ib_udata *udata);
 975         void (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata);
 976         int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
 977         int (*init_eq)(struct hns_roce_dev *hr_dev);
 978         void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
 979         void (*write_srqc)(struct hns_roce_dev *hr_dev,
 980                            struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn,
 981                            void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx,
 982                            dma_addr_t dma_handle_wqe,
 983                            dma_addr_t dma_handle_idx);
 984         int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
 985                        enum ib_srq_attr_mask srq_attr_mask,
 986                        struct ib_udata *udata);
 987         int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr);
 988         int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
 989                              const struct ib_recv_wr **bad_wr);
 990         const struct ib_device_ops *hns_roce_dev_ops;
 991         const struct ib_device_ops *hns_roce_dev_srq_ops;
 992 };
 993
 994 enum hns_phy_state {
 995         HNS_ROCE_PHY_SLEEP              = 1,
 996         HNS_ROCE_PHY_POLLING            = 2,
 997         HNS_ROCE_PHY_DISABLED           = 3,
 998         HNS_ROCE_PHY_TRAINING           = 4,
 999         HNS_ROCE_PHY_LINKUP             = 5,
1000         HNS_ROCE_PHY_LINKERR            = 6,
1001         HNS_ROCE_PHY_TEST               = 7
1002 };
1003
1004 struct hns_roce_dev {
1005         struct ib_device        ib_dev;
1006         struct platform_device  *pdev;
1007         struct pci_dev          *pci_dev;
1008         struct device           *dev;
1009         struct hns_roce_uar     priv_uar;
1010         const char              *irq_names[HNS_ROCE_MAX_IRQ_NUM];
1011         spinlock_t              sm_lock;
1012         spinlock_t              bt_cmd_lock;
1013         bool                    active;
1014         bool                    is_reset;
1015         bool                    dis_db;
1016         unsigned long           reset_cnt;
1017         struct hns_roce_ib_iboe iboe;
1018
1019         struct list_head        pgdir_list;
1020         struct mutex            pgdir_mutex;
1021         int                     irq[HNS_ROCE_MAX_IRQ_NUM];
1022         u8 __iomem              *reg_base;
1023         struct hns_roce_caps    caps;
1024         struct xarray           qp_table_xa;
1025
1026         unsigned char   dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
1027         u64                     sys_image_guid;
1028         u32                     vendor_id;
1029         u32                     vendor_part_id;
1030         u32                     hw_rev;
1031         void __iomem            *priv_addr;
1032
1033         struct hns_roce_cmdq    cmd;
1034         struct hns_roce_bitmap    pd_bitmap;
1035         struct hns_roce_uar_table uar_table;
1036         struct hns_roce_mr_table  mr_table;
1037         struct hns_roce_cq_table  cq_table;
1038         struct hns_roce_srq_table srq_table;
1039         struct hns_roce_qp_table  qp_table;
1040         struct hns_roce_eq_table  eq_table;
1041         struct hns_roce_hem_table  qpc_timer_table;
1042         struct hns_roce_hem_table  cqc_timer_table;
1043
1044         int                     cmd_mod;
1045         int                     loop_idc;
1046         u32                     sdb_offset;
1047         u32                     odb_offset;
1048         dma_addr_t              tptr_dma_addr; /*only for hw v1*/
1049         u32                     tptr_size; /*only for hw v1*/
1050         const struct hns_roce_hw *hw;
1051         void                    *priv;
1052         struct workqueue_struct *irq_workq;
1053         const struct hns_roce_dfx_hw *dfx;
1054 };
1055
1056 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
1057 {
1058         return container_of(ib_dev, struct hns_roce_dev, ib_dev);
1059 }
1060
1061 static inline struct hns_roce_ucontext
1062                         *to_hr_ucontext(struct ib_ucontext *ibucontext)
1063 {
1064         return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
1065 }
1066
1067 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
1068 {
1069         return container_of(ibpd, struct hns_roce_pd, ibpd);
1070 }
1071
1072 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
1073 {
1074         return container_of(ibah, struct hns_roce_ah, ibah);
1075 }
1076
1077 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
1078 {
1079         return container_of(ibmr, struct hns_roce_mr, ibmr);
1080 }
1081
1082 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
1083 {
1084         return container_of(ibmw, struct hns_roce_mw, ibmw);
1085 }
1086
1087 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1088 {
1089         return container_of(ibqp, struct hns_roce_qp, ibqp);
1090 }
1091
1092 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1093 {
1094         return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1095 }
1096
1097 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1098 {
1099         return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1100 }
1101
1102 static inline struct hns_roce_sqp *hr_to_hr_sqp(struct hns_roce_qp *hr_qp)
1103 {
1104         return container_of(hr_qp, struct hns_roce_sqp, hr_qp);
1105 }
1106
1107 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1108 {
1109         __raw_writeq(*(u64 *) val, dest);
1110 }
1111
1112 static inline struct hns_roce_qp
1113         *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1114 {
1115         return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1));
1116 }
1117
1118 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset)
1119 {
1120         u32 page_size = 1 << buf->page_shift;
1121
1122         if (buf->nbufs == 1)
1123                 return (char *)(buf->direct.buf) + offset;
1124         else
1125                 return (char *)(buf->page_list[offset >> buf->page_shift].buf) +
1126                        (offset & (page_size - 1));
1127 }
1128
1129 int hns_roce_init_uar_table(struct hns_roce_dev *dev);
1130 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1131 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1132 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
1133
1134 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1135 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1136 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1137                         u64 out_param);
1138 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1139 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1140
1141 int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift,
1142                       struct hns_roce_mtt *mtt);
1143 void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev,
1144                           struct hns_roce_mtt *mtt);
1145 int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev,
1146                            struct hns_roce_mtt *mtt, struct hns_roce_buf *buf);
1147
1148 void hns_roce_mtr_init(struct hns_roce_mtr *mtr, int bt_pg_shift,
1149                        int buf_pg_shift);
1150 int hns_roce_mtr_attach(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1151                         dma_addr_t **bufs, struct hns_roce_buf_region *regions,
1152                         int region_cnt);
1153 void hns_roce_mtr_cleanup(struct hns_roce_dev *hr_dev,
1154                           struct hns_roce_mtr *mtr);
1155
1156 /* hns roce hw need current block and next block addr from mtt */
1157 #define MTT_MIN_COUNT    2
1158 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1159                       int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1160
1161 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1162 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1163 int hns_roce_init_eq_table(struct hns_roce_dev *hr_dev);
1164 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1165 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1166 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1167
1168 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
1169 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
1170 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1171 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1172 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1173 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev);
1174
1175 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
1176 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
1177                          int rr);
1178 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
1179                          u32 reserved_bot, u32 resetrved_top);
1180 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
1181 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1182 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
1183                                 int align, unsigned long *obj);
1184 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
1185                                 unsigned long obj, int cnt,
1186                                 int rr);
1187
1188 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_attr *ah_attr,
1189                        u32 flags, struct ib_udata *udata);
1190 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1191 void hns_roce_destroy_ah(struct ib_ah *ah, u32 flags);
1192
1193 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1194 void hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1195
1196 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1197 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1198                                    u64 virt_addr, int access_flags,
1199                                    struct ib_udata *udata);
1200 int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length,
1201                            u64 virt_addr, int mr_access_flags, struct ib_pd *pd,
1202                            struct ib_udata *udata);
1203 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1204                                 u32 max_num_sg, struct ib_udata *udata);
1205 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1206                        unsigned int *sg_offset);
1207 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1208 int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev,
1209                        struct hns_roce_cmd_mailbox *mailbox,
1210                        unsigned long mpt_index);
1211 unsigned long key_to_hw_index(u32 key);
1212
1213 struct ib_mw *hns_roce_alloc_mw(struct ib_pd *pd, enum ib_mw_type,
1214                                 struct ib_udata *udata);
1215 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1216
1217 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size,
1218                        struct hns_roce_buf *buf);
1219 int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
1220                        struct hns_roce_buf *buf, u32 page_shift);
1221
1222 int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev,
1223                                struct hns_roce_mtt *mtt, struct ib_umem *umem);
1224
1225 void hns_roce_init_buf_region(struct hns_roce_buf_region *region, int hopnum,
1226                               int offset, int buf_cnt);
1227 int hns_roce_alloc_buf_list(struct hns_roce_buf_region *regions,
1228                             dma_addr_t **bufs, int count);
1229 void hns_roce_free_buf_list(dma_addr_t **bufs, int count);
1230
1231 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1232                            int buf_cnt, int start, struct hns_roce_buf *buf);
1233 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1234                            int buf_cnt, int start, struct ib_umem *umem,
1235                            int page_shift);
1236
1237 int hns_roce_create_srq(struct ib_srq *srq,
1238                         struct ib_srq_init_attr *srq_init_attr,
1239                         struct ib_udata *udata);
1240 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1241                         enum ib_srq_attr_mask srq_attr_mask,
1242                         struct ib_udata *udata);
1243 void hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1244
1245 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
1246                                  struct ib_qp_init_attr *init_attr,
1247                                  struct ib_udata *udata);
1248 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1249                        int attr_mask, struct ib_udata *udata);
1250 void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n);
1251 void *get_send_wqe(struct hns_roce_qp *hr_qp, int n);
1252 void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n);
1253 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
1254                           struct ib_cq *ib_cq);
1255 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
1256 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1257                        struct hns_roce_cq *recv_cq);
1258 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1259                          struct hns_roce_cq *recv_cq);
1260 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1261 void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1262 void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn,
1263                                int cnt);
1264 __be32 send_ieth(const struct ib_send_wr *wr);
1265 int to_hr_qp_type(int qp_type);
1266
1267 int hns_roce_ib_create_cq(struct ib_cq *ib_cq,
1268                           const struct ib_cq_init_attr *attr,
1269                           struct ib_udata *udata);
1270
1271 void hns_roce_ib_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1272 void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq);
1273
1274 int hns_roce_db_map_user(struct hns_roce_ucontext *context,
1275                          struct ib_udata *udata, unsigned long virt,
1276                          struct hns_roce_db *db);
1277 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1278                             struct hns_roce_db *db);
1279 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1280                       int order);
1281 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1282
1283 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1284 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1285 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1286 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1287 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
1288 int hns_roce_init(struct hns_roce_dev *hr_dev);
1289 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1290
1291 int hns_roce_fill_res_entry(struct sk_buff *msg,
1292                             struct rdma_restrack_entry *res);
1293 #endif /* _HNS_ROCE_DEVICE_H */