2 * INCA-IP internal switch ethernet driver.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
30 && defined(CONFIG_INCA_IP_SWITCH)
34 #include <asm/inca-ip.h>
35 #include <asm/addrspace.h>
38 #define NUM_RX_DESC PKTBUFSRX
40 #define TOUT_LOOP 1000000
43 #define DELAY udelay(10000)
45 #define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value;
46 #define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
47 #define SW_WRITE_REG(reg, value) \
48 *((volatile u32*)reg) = (u32)value;\
50 *((volatile u32*)reg) = (u32)value;
52 #define SW_READ_REG(reg, value) \
53 value = (u32)*((volatile u32*)reg);\
55 value = (u32)*((volatile u32*)reg);
57 #define INCA_DMA_TX_POLLING_TIME 0x07
58 #define INCA_DMA_RX_POLLING_TIME 0x07
60 #define INCA_DMA_TX_HOLD 0x80000000
61 #define INCA_DMA_TX_EOP 0x40000000
62 #define INCA_DMA_TX_SOP 0x20000000
63 #define INCA_DMA_TX_ICPT 0x10000000
64 #define INCA_DMA_TX_IEOP 0x08000000
66 #define INCA_DMA_RX_C 0x80000000
67 #define INCA_DMA_RX_SOP 0x40000000
68 #define INCA_DMA_RX_EOP 0x20000000
70 /************************ Auto MDIX settings ************************/
71 #define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR
72 #define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL
73 #define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT
74 #define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16
76 #define WAIT_SIGNAL_RETRIES 100
77 #define WAIT_LINK_RETRIES 100
78 #define LINK_RETRY_DELAY 300 /* ms */
79 /********************************************************************/
88 volatile u32 offset :3;
89 volatile u32 reserved0 :4;
96 volatile u32 nextRxDescPtr;
98 volatile u32 RxDataPtr;
105 volatile u32 reserved3 :12;
106 volatile u32 NBT :17;
112 } inca_rx_descriptor_t;
119 volatile u32 HOLD :1;
122 volatile u32 ICpt :1;
123 volatile u32 IEop :1;
124 volatile u32 reserved0 :5;
125 volatile u32 NBA :22;
131 volatile u32 nextTxDescPtr;
133 volatile u32 TxDataPtr;
136 volatile u32 reserved3 :31;
138 } inca_tx_descriptor_t;
141 static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16)));
142 static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16)));
144 static int tx_new, rx_new, tx_hold, rx_hold;
145 static int tx_old_hold = -1;
146 static int initialized = 0;
149 static int inca_switch_init(struct eth_device *dev, bd_t * bis);
150 static int inca_switch_send(struct eth_device *dev, volatile void *packet,
152 static int inca_switch_recv(struct eth_device *dev);
153 static void inca_switch_halt(struct eth_device *dev);
154 static void inca_init_switch_chip(void);
155 static void inca_dma_init(void);
156 static int inca_amdix(void);
159 int inca_switch_initialize(bd_t * bis)
161 struct eth_device *dev;
164 printf("Entered inca_switch_initialize()\n");
167 if (!(dev = (struct eth_device *) malloc (sizeof *dev))) {
168 printf("Failed to allocate memory\n");
171 memset(dev, 0, sizeof(*dev));
175 inca_init_switch_chip();
179 sprintf(dev->name, "INCA-IP Switch");
180 dev->init = inca_switch_init;
181 dev->halt = inca_switch_halt;
182 dev->send = inca_switch_send;
183 dev->recv = inca_switch_recv;
188 printf("Leaving inca_switch_initialize()\n");
195 static int inca_switch_init(struct eth_device *dev, bd_t * bis)
202 printf("Entering inca_switch_init()\n");
207 wTmp = (u16)dev->enetaddr[0];
208 regValue = (wTmp << 8) | dev->enetaddr[1];
210 SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue);
212 wTmp = (u16)dev->enetaddr[2];
213 regValue = (wTmp << 8) | dev->enetaddr[3];
214 regValue = regValue << 16;
215 wTmp = (u16)dev->enetaddr[4];
216 regValue |= (wTmp<<8) | dev->enetaddr[5];
218 SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue);
220 /* Initialize the descriptor rings.
222 for (i = 0; i < NUM_RX_DESC; i++)
224 inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]);
225 memset(rx_desc, 0, sizeof(rx_ring[i]));
227 /* Set maximum size of receive buffer.
229 rx_desc->params.field.NFB = PKTSIZE_ALIGN;
231 /* Set the offset of the receive buffer. Zero means
232 * that the offset mechanism is not used.
234 rx_desc->params.field.offset = 0;
236 /* Check if it is the last descriptor.
238 if (i == (NUM_RX_DESC - 1)) {
239 /* Let the last descriptor point to the first
242 rx_desc->nextRxDescPtr = KSEG1ADDR((u32)rx_ring);
244 /* Set the address of the next descriptor.
246 rx_desc->nextRxDescPtr = (u32)KSEG1ADDR(&rx_ring[i+1]);
249 rx_desc->RxDataPtr = (u32)KSEG1ADDR(NetRxPackets[i]);
253 printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]);
254 printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]);
257 for (i = 0; i < NUM_TX_DESC; i++) {
258 inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[i]);
260 memset(tx_desc, 0, sizeof(tx_ring[i]));
262 tx_desc->params.word = 0;
263 tx_desc->params.field.HOLD = 1;
266 /* Check if it is the last descriptor.
268 if (i == (NUM_TX_DESC - 1)) {
269 /* Let the last descriptor point to the
272 tx_desc->nextTxDescPtr = KSEG1ADDR((u32)tx_ring);
274 /* Set the address of the next descriptor.
276 tx_desc->nextTxDescPtr = (u32)KSEG1ADDR(&tx_ring[i+1]);
282 DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v);
284 printf("RX status = 0x%08X\n", v);
287 /* Writing to the FRDA of CHANNEL.
289 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring);
291 /* Writing to the COMMAND REG.
293 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0,
294 INCA_IP_DMA_DMA_RXCCR0_INIT);
298 DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v);
300 printf("TX status = 0x%08X\n", v);
303 /* Writing to the FRDA of CHANNEL.
305 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring);
309 tx_hold = NUM_TX_DESC - 1;
310 rx_hold = NUM_RX_DESC - 1;
313 rx_ring[rx_hold].params.field.HOLD = 1;
315 /* enable spanning tree forwarding, enable the CPU port */
317 * CPS (CPU port status) 0x3 (forwarding)
318 * LPS (LAN port status) 0x3 (forwarding)
319 * PPS (PC port status) 0x3 (forwarding)
321 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f);
324 printf("Leaving inca_switch_init()\n");
331 static int inca_switch_send(struct eth_device *dev, volatile void *packet,
338 inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[tx_new]);
341 printf("Entered inca_switch_send()\n");
345 printf ("%s: bad packet size: %d\n", dev->name, length);
349 for(i = 0; tx_desc->C == 0; i++) {
350 if (i >= TOUT_LOOP) {
351 printf("%s: tx error buffer not ready\n", dev->name);
356 if (tx_old_hold >= 0) {
357 KSEG1ADDR(&tx_ring[tx_old_hold])->params.field.HOLD = 1;
359 tx_old_hold = tx_hold;
361 tx_desc->params.word =
362 (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD);
365 tx_desc->TxDataPtr = (u32)packet;
366 tx_desc->params.field.NBA = length;
368 KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0;
371 tx_new = (tx_new + 1) % NUM_TX_DESC;
375 command = INCA_IP_DMA_DMA_TXCCR0_INIT;
378 command = INCA_IP_DMA_DMA_TXCCR0_HR;
381 DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
384 printf("regValue = 0x%x\n", regValue);
386 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
389 for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++) {
390 if (i >= TOUT_LOOP) {
391 printf("%s: tx buffer not ready\n", dev->name);
399 printf("Leaving inca_switch_send()\n");
405 static int inca_switch_recv(struct eth_device *dev)
408 inca_rx_descriptor_t * rx_desc;
411 printf("Entered inca_switch_recv()\n");
415 rx_desc = KSEG1ADDR(&rx_ring[rx_new]);
417 if (rx_desc->status.field.C == 0) {
422 rx_ring[rx_new].params.field.HOLD = 1;
425 if (! rx_desc->status.field.Eop) {
426 printf("Partly received packet!!!\n");
430 length = rx_desc->status.field.NBT;
431 rx_desc->status.word &=
432 ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C);
436 for (i=0;i<length - 4;i++) {
437 if (i % 16 == 0) printf("\n%04x: ", i);
438 printf("%02X ", NetRxPackets[rx_new][i]);
446 printf("Received %d bytes\n", length);
448 NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]),
452 printf("Zero length!!!\n");
457 KSEG1ADDR(&rx_ring[rx_hold])->params.field.HOLD = 0;
461 rx_new = (rx_new + 1) % NUM_RX_DESC;
465 printf("Leaving inca_switch_recv()\n");
472 static void inca_switch_halt(struct eth_device *dev)
475 printf("Entered inca_switch_halt()\n");
482 /* Disable forwarding to the CPU port.
484 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
486 /* Close RxDMA channel.
488 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
490 /* Close TxDMA channel.
492 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF);
497 printf("Leaving inca_switch_halt()\n");
502 static void inca_init_switch_chip(void)
506 /* To workaround a problem with collision counter
507 * (see Errata sheet).
509 SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001);
510 SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001);
513 /* init MDIO configuration:
514 * MDS (Poll speed): 0x01 (4ms)
517 * UEP (Use External PHY): 0x00 (Internal PHY is used)
518 * PS (Port Select): 0x00 (PT/UMM for LAN)
519 * PT (PHY Test): 0x00 (no test mode)
520 * UMM (Use MDIO Mode): 0x00 (state machine is disabled)
522 SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
525 * SL (Auto Neg. Speed for LAN)
526 * SP (Auto Neg. Speed for PC)
527 * LL (Link Status for LAN)
528 * LP (Link Status for PC)
529 * DL (Duplex Status for LAN)
530 * DP (Duplex Status for PC)
531 * PL (Auto Neg. Pause Status for LAN)
532 * PP (Auto Neg. Pause Status for PC)
534 SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff);
537 * RA (Request/Ack) 0x01 (Request)
538 * RW (Read/Write) 0x01 (Write)
540 * REG_ADDR 0x00 (PHY_BCR: basic control register)
542 * Reset - software reset
543 * LB (loop back) - normal
544 * SS (speed select) - 10 Mbit/s
545 * ANE (auto neg. enable) - enable
546 * PD (power down) - normal
547 * ISO (isolate) - normal
548 * RAN (restart auto neg.) - normal
549 * DM (duplex mode) - half duplex
550 * CT (collision test) - enable
552 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
555 * RA (Request/Ack) 0x01 (Request)
556 * RW (Read/Write) 0x01 (Write)
557 * PHY_ADDR 0x06 (LAN)
558 * REG_ADDR 0x00 (PHY_BCR: basic control register)
560 * Reset - software reset
561 * LB (loop back) - normal
562 * SS (speed select) - 10 Mbit/s
563 * ANE (auto neg. enable) - enable
564 * PD (power down) - normal
565 * ISO (isolate) - normal
566 * RAN (restart auto neg.) - normal
567 * DM (duplex mode) - half duplex
568 * CT (collision test) - enable
570 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
574 /* Make sure the CPU port is disabled for now. We
575 * don't want packets to get stacked for us until
576 * we enable DMA and are prepared to receive them.
578 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
580 SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue);
582 /* CRC GEN is enabled.
584 regValue |= 0x00000200;
585 SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue);
587 /* ADD TAG is disabled.
589 SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
590 regValue &= ~0x00000002;
591 SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
595 static void inca_dma_init(void)
597 /* Switch off all DMA channels.
599 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
600 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF);
602 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
603 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF);
604 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF);
606 /* Setup TX channel polling time.
608 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME);
610 /* Setup RX channel polling time.
612 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME);
614 /* ERRATA: write reset value into the DMA RX IMR register.
616 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF);
618 /* Just in case: disable all transmit interrupts also.
620 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF);
622 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF);
623 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF);
626 static int inca_amdix(void)
634 *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
635 *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
639 retries = WAIT_SIGNAL_RETRIES;
642 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
643 (0x1 << 31) | /* RA */
644 (0x0 << 30) | /* Read */
645 (0x6 << 21) | /* LAN */
646 (17 << 16)); /* PHY_MCSR */
649 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, regValue);
651 while (regValue & (1 << 31));
653 if (regValue & (1 << 1))
655 /* Signal detected */
665 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
670 retries = WAIT_LINK_RETRIES;
673 udelay(LINK_RETRY_DELAY * 1000);
674 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
675 (0x1 << 31) | /* RA */
676 (0x0 << 30) | /* Read */
677 (0x6 << 21) | /* LAN */
678 (1 << 16)); /* PHY_BSR */
681 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, regValue);
683 while (regValue & (1 << 31));
685 if (regValue & (1 << 2))
693 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
699 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);