drivers/iio/frequency/ad9523.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * AD9523 SPI Low Jitter Clock Generator
   4  *
   5  * Copyright 2012 Analog Devices Inc.
   6  */
   7
   8 #include <linux/device.h>
   9 #include <linux/kernel.h>
  10 #include <linux/slab.h>
  11 #include <linux/sysfs.h>
  12 #include <linux/spi/spi.h>
  13 #include <linux/regulator/consumer.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/err.h>
  16 #include <linux/module.h>
  17 #include <linux/delay.h>
  18
  19 #include <linux/iio/iio.h>
  20 #include <linux/iio/sysfs.h>
  21 #include <linux/iio/frequency/ad9523.h>
  22
  23 #define AD9523_READ     (1 << 15)
  24 #define AD9523_WRITE    (0 << 15)
  25 #define AD9523_CNT(x)   (((x) - 1) << 13)
  26 #define AD9523_ADDR(x)  ((x) & 0xFFF)
  27
  28 #define AD9523_R1B      (1 << 16)
  29 #define AD9523_R2B      (2 << 16)
  30 #define AD9523_R3B      (3 << 16)
  31 #define AD9523_TRANSF_LEN(x)                    ((x) >> 16)
  32
  33 #define AD9523_SERIAL_PORT_CONFIG               (AD9523_R1B | 0x0)
  34 #define AD9523_VERSION_REGISTER                 (AD9523_R1B | 0x2)
  35 #define AD9523_PART_REGISTER                    (AD9523_R1B | 0x3)
  36 #define AD9523_READBACK_CTRL                    (AD9523_R1B | 0x4)
  37
  38 #define AD9523_EEPROM_CUSTOMER_VERSION_ID       (AD9523_R2B | 0x6)
  39
  40 #define AD9523_PLL1_REF_A_DIVIDER               (AD9523_R2B | 0x11)
  41 #define AD9523_PLL1_REF_B_DIVIDER               (AD9523_R2B | 0x13)
  42 #define AD9523_PLL1_REF_TEST_DIVIDER            (AD9523_R1B | 0x14)
  43 #define AD9523_PLL1_FEEDBACK_DIVIDER            (AD9523_R2B | 0x17)
  44 #define AD9523_PLL1_CHARGE_PUMP_CTRL            (AD9523_R2B | 0x19)
  45 #define AD9523_PLL1_INPUT_RECEIVERS_CTRL        (AD9523_R1B | 0x1A)
  46 #define AD9523_PLL1_REF_CTRL                    (AD9523_R1B | 0x1B)
  47 #define AD9523_PLL1_MISC_CTRL                   (AD9523_R1B | 0x1C)
  48 #define AD9523_PLL1_LOOP_FILTER_CTRL            (AD9523_R1B | 0x1D)
  49
  50 #define AD9523_PLL2_CHARGE_PUMP                 (AD9523_R1B | 0xF0)
  51 #define AD9523_PLL2_FEEDBACK_DIVIDER_AB         (AD9523_R1B | 0xF1)
  52 #define AD9523_PLL2_CTRL                        (AD9523_R1B | 0xF2)
  53 #define AD9523_PLL2_VCO_CTRL                    (AD9523_R1B | 0xF3)
  54 #define AD9523_PLL2_VCO_DIVIDER                 (AD9523_R1B | 0xF4)
  55 #define AD9523_PLL2_LOOP_FILTER_CTRL            (AD9523_R2B | 0xF6)
  56 #define AD9523_PLL2_R2_DIVIDER                  (AD9523_R1B | 0xF7)
  57
  58 #define AD9523_CHANNEL_CLOCK_DIST(ch)           (AD9523_R3B | (0x192 + 3 * ch))
  59
  60 #define AD9523_PLL1_OUTPUT_CTRL                 (AD9523_R1B | 0x1BA)
  61 #define AD9523_PLL1_OUTPUT_CHANNEL_CTRL         (AD9523_R1B | 0x1BB)
  62
  63 #define AD9523_READBACK_0                       (AD9523_R1B | 0x22C)
  64 #define AD9523_READBACK_1                       (AD9523_R1B | 0x22D)
  65
  66 #define AD9523_STATUS_SIGNALS                   (AD9523_R3B | 0x232)
  67 #define AD9523_POWER_DOWN_CTRL                  (AD9523_R1B | 0x233)
  68 #define AD9523_IO_UPDATE                        (AD9523_R1B | 0x234)
  69
  70 #define AD9523_EEPROM_DATA_XFER_STATUS          (AD9523_R1B | 0xB00)
  71 #define AD9523_EEPROM_ERROR_READBACK            (AD9523_R1B | 0xB01)
  72 #define AD9523_EEPROM_CTRL1                     (AD9523_R1B | 0xB02)
  73 #define AD9523_EEPROM_CTRL2                     (AD9523_R1B | 0xB03)
  74
  75 /* AD9523_SERIAL_PORT_CONFIG */
  76
  77 #define AD9523_SER_CONF_SDO_ACTIVE              (1 << 7)
  78 #define AD9523_SER_CONF_SOFT_RESET              (1 << 5)
  79
  80 /* AD9523_READBACK_CTRL */
  81 #define AD9523_READBACK_CTRL_READ_BUFFERED      (1 << 0)
  82
  83 /* AD9523_PLL1_CHARGE_PUMP_CTRL */
  84 #define AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(x)   (((x) / 500) & 0x7F)
  85 #define AD9523_PLL1_CHARGE_PUMP_TRISTATE        (1 << 7)
  86 #define AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL     (3 << 8)
  87 #define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN  (2 << 8)
  88 #define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP    (1 << 8)
  89 #define AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE   (0 << 8)
  90 #define AD9523_PLL1_BACKLASH_PW_MIN             (0 << 10)
  91 #define AD9523_PLL1_BACKLASH_PW_LOW             (1 << 10)
  92 #define AD9523_PLL1_BACKLASH_PW_HIGH            (2 << 10)
  93 #define AD9523_PLL1_BACKLASH_PW_MAX             (3 << 10)
  94
  95 /* AD9523_PLL1_INPUT_RECEIVERS_CTRL */
  96 #define AD9523_PLL1_REF_TEST_RCV_EN             (1 << 7)
  97 #define AD9523_PLL1_REFB_DIFF_RCV_EN            (1 << 6)
  98 #define AD9523_PLL1_REFA_DIFF_RCV_EN            (1 << 5)
  99 #define AD9523_PLL1_REFB_RCV_EN                 (1 << 4)
 100 #define AD9523_PLL1_REFA_RCV_EN                 (1 << 3)
 101 #define AD9523_PLL1_REFA_REFB_PWR_CTRL_EN       (1 << 2)
 102 #define AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN      (1 << 1)
 103 #define AD9523_PLL1_OSC_IN_DIFF_EN              (1 << 0)
 104
 105 /* AD9523_PLL1_REF_CTRL */
 106 #define AD9523_PLL1_BYPASS_REF_TEST_DIV_EN      (1 << 7)
 107 #define AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN      (1 << 6)
 108 #define AD9523_PLL1_ZERO_DELAY_MODE_INT         (1 << 5)
 109 #define AD9523_PLL1_ZERO_DELAY_MODE_EXT         (0 << 5)
 110 #define AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN      (1 << 4)
 111 #define AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN       (1 << 3)
 112 #define AD9523_PLL1_ZD_IN_DIFF_EN               (1 << 2)
 113 #define AD9523_PLL1_REFB_CMOS_NEG_INP_EN        (1 << 1)
 114 #define AD9523_PLL1_REFA_CMOS_NEG_INP_EN        (1 << 0)
 115
 116 /* AD9523_PLL1_MISC_CTRL */
 117 #define AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN      (1 << 7)
 118 #define AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN    (1 << 6)
 119 #define AD9523_PLL1_REF_MODE(x)                 ((x) << 2)
 120 #define AD9523_PLL1_BYPASS_REFB_DIV             (1 << 1)
 121 #define AD9523_PLL1_BYPASS_REFA_DIV             (1 << 0)
 122
 123 /* AD9523_PLL1_LOOP_FILTER_CTRL */
 124 #define AD9523_PLL1_LOOP_FILTER_RZERO(x)        ((x) & 0xF)
 125
 126 /* AD9523_PLL2_CHARGE_PUMP */
 127 #define AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(x)   ((x) / 3500)
 128
 129 /* AD9523_PLL2_FEEDBACK_DIVIDER_AB */
 130 #define AD9523_PLL2_FB_NDIV_A_CNT(x)            (((x) & 0x3) << 6)
 131 #define AD9523_PLL2_FB_NDIV_B_CNT(x)            (((x) & 0x3F) << 0)
 132 #define AD9523_PLL2_FB_NDIV(a, b)               (4 * (b) + (a))
 133
 134 /* AD9523_PLL2_CTRL */
 135 #define AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL     (3 << 0)
 136 #define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN  (2 << 0)
 137 #define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP    (1 << 0)
 138 #define AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE   (0 << 0)
 139 #define AD9523_PLL2_BACKLASH_PW_MIN             (0 << 2)
 140 #define AD9523_PLL2_BACKLASH_PW_LOW             (1 << 2)
 141 #define AD9523_PLL2_BACKLASH_PW_HIGH            (2 << 2)
 142 #define AD9523_PLL2_BACKLASH_PW_MAX             (3 << 1)
 143 #define AD9523_PLL2_BACKLASH_CTRL_EN            (1 << 4)
 144 #define AD9523_PLL2_FREQ_DOUBLER_EN             (1 << 5)
 145 #define AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN     (1 << 7)
 146
 147 /* AD9523_PLL2_VCO_CTRL */
 148 #define AD9523_PLL2_VCO_CALIBRATE               (1 << 1)
 149 #define AD9523_PLL2_FORCE_VCO_MIDSCALE          (1 << 2)
 150 #define AD9523_PLL2_FORCE_REFERENCE_VALID       (1 << 3)
 151 #define AD9523_PLL2_FORCE_RELEASE_SYNC          (1 << 4)
 152
 153 /* AD9523_PLL2_VCO_DIVIDER */
 154 #define AD9523_PLL2_VCO_DIV_M1(x)               ((((x) - 3) & 0x3) << 0)
 155 #define AD9523_PLL2_VCO_DIV_M2(x)               ((((x) - 3) & 0x3) << 4)
 156 #define AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN      (1 << 2)
 157 #define AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN      (1 << 6)
 158
 159 /* AD9523_PLL2_LOOP_FILTER_CTRL */
 160 #define AD9523_PLL2_LOOP_FILTER_CPOLE1(x)       (((x) & 0x7) << 0)
 161 #define AD9523_PLL2_LOOP_FILTER_RZERO(x)        (((x) & 0x7) << 3)
 162 #define AD9523_PLL2_LOOP_FILTER_RPOLE2(x)       (((x) & 0x7) << 6)
 163 #define AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8)
 164
 165 /* AD9523_PLL2_R2_DIVIDER */
 166 #define AD9523_PLL2_R2_DIVIDER_VAL(x)           (((x) & 0x1F) << 0)
 167
 168 /* AD9523_CHANNEL_CLOCK_DIST */
 169 #define AD9523_CLK_DIST_DIV_PHASE(x)            (((x) & 0x3F) << 18)
 170 #define AD9523_CLK_DIST_DIV_PHASE_REV(x)        ((ret >> 18) & 0x3F)
 171 #define AD9523_CLK_DIST_DIV(x)                  ((((x) - 1) & 0x3FF) << 8)
 172 #define AD9523_CLK_DIST_DIV_REV(x)              (((ret >> 8) & 0x3FF) + 1)
 173 #define AD9523_CLK_DIST_INV_DIV_OUTPUT_EN       (1 << 7)
 174 #define AD9523_CLK_DIST_IGNORE_SYNC_EN          (1 << 6)
 175 #define AD9523_CLK_DIST_PWR_DOWN_EN             (1 << 5)
 176 #define AD9523_CLK_DIST_LOW_PWR_MODE_EN         (1 << 4)
 177 #define AD9523_CLK_DIST_DRIVER_MODE(x)          (((x) & 0xF) << 0)
 178
 179 /* AD9523_PLL1_OUTPUT_CTRL */
 180 #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2        (1 << 7)
 181 #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2        (1 << 6)
 182 #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2        (1 << 5)
 183 #define AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK             (1 << 4)
 184 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1              (0 << 0)
 185 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2              (1 << 0)
 186 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4              (2 << 0)
 187 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8              (4 << 0)
 188 #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16             (8 << 0)
 189
 190 /* AD9523_PLL1_OUTPUT_CHANNEL_CTRL */
 191 #define AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN     (1 << 7)
 192 #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2     (1 << 6)
 193 #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2     (1 << 5)
 194 #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2     (1 << 4)
 195 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3       (1 << 3)
 196 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2       (1 << 2)
 197 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1       (1 << 1)
 198 #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0       (1 << 0)
 199
 200 /* AD9523_READBACK_0 */
 201 #define AD9523_READBACK_0_STAT_PLL2_REF_CLK             (1 << 7)
 202 #define AD9523_READBACK_0_STAT_PLL2_FB_CLK              (1 << 6)
 203 #define AD9523_READBACK_0_STAT_VCXO                     (1 << 5)
 204 #define AD9523_READBACK_0_STAT_REF_TEST                 (1 << 4)
 205 #define AD9523_READBACK_0_STAT_REFB                     (1 << 3)
 206 #define AD9523_READBACK_0_STAT_REFA                     (1 << 2)
 207 #define AD9523_READBACK_0_STAT_PLL2_LD                  (1 << 1)
 208 #define AD9523_READBACK_0_STAT_PLL1_LD                  (1 << 0)
 209
 210 /* AD9523_READBACK_1 */
 211 #define AD9523_READBACK_1_HOLDOVER_ACTIVE               (1 << 3)
 212 #define AD9523_READBACK_1_AUTOMODE_SEL_REFB             (1 << 2)
 213 #define AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS         (1 << 0)
 214
 215 /* AD9523_STATUS_SIGNALS */
 216 #define AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL             (1 << 16)
 217 #define AD9523_STATUS_MONITOR_01_PLL12_LOCKED           (0x302)
 218 /* AD9523_POWER_DOWN_CTRL */
 219 #define AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN            (1 << 2)
 220 #define AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN            (1 << 1)
 221 #define AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN            (1 << 0)
 222
 223 /* AD9523_IO_UPDATE */
 224 #define AD9523_IO_UPDATE_EN                             (1 << 0)
 225
 226 /* AD9523_EEPROM_DATA_XFER_STATUS */
 227 #define AD9523_EEPROM_DATA_XFER_IN_PROGRESS             (1 << 0)
 228
 229 /* AD9523_EEPROM_ERROR_READBACK */
 230 #define AD9523_EEPROM_ERROR_READBACK_FAIL               (1 << 0)
 231
 232 /* AD9523_EEPROM_CTRL1 */
 233 #define AD9523_EEPROM_CTRL1_SOFT_EEPROM                 (1 << 1)
 234 #define AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS       (1 << 0)
 235
 236 /* AD9523_EEPROM_CTRL2 */
 237 #define AD9523_EEPROM_CTRL2_REG2EEPROM                  (1 << 0)
 238
 239 #define AD9523_NUM_CHAN                                 14
 240 #define AD9523_NUM_CHAN_ALT_CLK_SRC                     10
 241
 242 /* Helpers to avoid excess line breaks */
 243 #define AD_IFE(_pde, _a, _b) ((pdata->_pde) ? _a : _b)
 244 #define AD_IF(_pde, _a) AD_IFE(_pde, _a, 0)
 245
 246 enum {
 247         AD9523_STAT_PLL1_LD,
 248         AD9523_STAT_PLL2_LD,
 249         AD9523_STAT_REFA,
 250         AD9523_STAT_REFB,
 251         AD9523_STAT_REF_TEST,
 252         AD9523_STAT_VCXO,
 253         AD9523_STAT_PLL2_FB_CLK,
 254         AD9523_STAT_PLL2_REF_CLK,
 255         AD9523_SYNC,
 256         AD9523_EEPROM,
 257 };
 258
 259 enum {
 260         AD9523_VCO1,
 261         AD9523_VCO2,
 262         AD9523_VCXO,
 263         AD9523_NUM_CLK_SRC,
 264 };
 265
 266 struct ad9523_state {
 267         struct spi_device               *spi;
 268         struct regulator                *reg;
 269         struct ad9523_platform_data     *pdata;
 270         struct iio_chan_spec            ad9523_channels[AD9523_NUM_CHAN];
 271         struct gpio_desc                *pwrdown_gpio;
 272         struct gpio_desc                *reset_gpio;
 273         struct gpio_desc                *sync_gpio;
 274
 275         unsigned long           vcxo_freq;
 276         unsigned long           vco_freq;
 277         unsigned long           vco_out_freq[AD9523_NUM_CLK_SRC];
 278         unsigned char           vco_out_map[AD9523_NUM_CHAN_ALT_CLK_SRC];
 279
 280         /*
 281          * Lock for accessing device registers. Some operations require
 282          * multiple consecutive R/W operations, during which the device
 283          * shouldn't be interrupted.  The buffers are also shared across
 284          * all operations so need to be protected on stand alone reads and
 285          * writes.
 286          */
 287         struct mutex            lock;
 288
 289         /*
 290          * DMA (thus cache coherency maintenance) requires the
 291          * transfer buffers to live in their own cache lines.
 292          */
 293         union {
 294                 __be32 d32;
 295                 u8 d8[4];
 296         } data[2] ____cacheline_aligned;
 297 };
 298
 299 static int ad9523_read(struct iio_dev *indio_dev, unsigned int addr)
 300 {
 301         struct ad9523_state *st = iio_priv(indio_dev);
 302         int ret;
 303
 304         /* We encode the register size 1..3 bytes into the register address.
 305          * On transfer we get the size from the register datum, and make sure
 306          * the result is properly aligned.
 307          */
 308
 309         struct spi_transfer t[] = {
 310                 {
 311                         .tx_buf = &st->data[0].d8[2],
 312                         .len = 2,
 313                 }, {
 314                         .rx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)],
 315                         .len = AD9523_TRANSF_LEN(addr),
 316                 },
 317         };
 318
 319         st->data[0].d32 = cpu_to_be32(AD9523_READ |
 320                                       AD9523_CNT(AD9523_TRANSF_LEN(addr)) |
 321                                       AD9523_ADDR(addr));
 322
 323         ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
 324         if (ret < 0)
 325                 dev_err(&indio_dev->dev, "read failed (%d)", ret);
 326         else
 327                 ret = be32_to_cpu(st->data[1].d32) & (0xFFFFFF >>
 328                                   (8 * (3 - AD9523_TRANSF_LEN(addr))));
 329
 330         return ret;
 331 };
 332
 333 static int ad9523_write(struct iio_dev *indio_dev,
 334                 unsigned int addr, unsigned int val)
 335 {
 336         struct ad9523_state *st = iio_priv(indio_dev);
 337         int ret;
 338         struct spi_transfer t[] = {
 339                 {
 340                         .tx_buf = &st->data[0].d8[2],
 341                         .len = 2,
 342                 }, {
 343                         .tx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)],
 344                         .len = AD9523_TRANSF_LEN(addr),
 345                 },
 346         };
 347
 348         st->data[0].d32 = cpu_to_be32(AD9523_WRITE |
 349                                       AD9523_CNT(AD9523_TRANSF_LEN(addr)) |
 350                                       AD9523_ADDR(addr));
 351         st->data[1].d32 = cpu_to_be32(val);
 352
 353         ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
 354
 355         if (ret < 0)
 356                 dev_err(&indio_dev->dev, "write failed (%d)", ret);
 357
 358         return ret;
 359 }
 360
 361 static int ad9523_io_update(struct iio_dev *indio_dev)
 362 {
 363         return ad9523_write(indio_dev, AD9523_IO_UPDATE, AD9523_IO_UPDATE_EN);
 364 }
 365
 366 static int ad9523_vco_out_map(struct iio_dev *indio_dev,
 367                               unsigned int ch, unsigned int out)
 368 {
 369         struct ad9523_state *st = iio_priv(indio_dev);
 370         int ret;
 371         unsigned int mask;
 372
 373         switch (ch) {
 374         case 0 ... 3:
 375                 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);
 376                 if (ret < 0)
 377                         break;
 378                 mask = AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 << ch;
 379                 if (out) {
 380                         ret |= mask;
 381                         out = 2;
 382                 } else {
 383                         ret &= ~mask;
 384                 }
 385                 ret = ad9523_write(indio_dev,
 386                                    AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);
 387                 break;
 388         case 4 ... 6:
 389                 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CTRL);
 390                 if (ret < 0)
 391                         break;
 392                 mask = AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 << (ch - 4);
 393                 if (out)
 394                         ret |= mask;
 395                 else
 396                         ret &= ~mask;
 397                 ret = ad9523_write(indio_dev, AD9523_PLL1_OUTPUT_CTRL, ret);
 398                 break;
 399         case 7 ... 9:
 400                 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);
 401                 if (ret < 0)
 402                         break;
 403                 mask = AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 << (ch - 7);
 404                 if (out)
 405                         ret |= mask;
 406                 else
 407                         ret &= ~mask;
 408                 ret = ad9523_write(indio_dev,
 409                                    AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);
 410                 break;
 411         default:
 412                 return 0;
 413         }
 414
 415         st->vco_out_map[ch] = out;
 416
 417         return ret;
 418 }
 419
 420 static int ad9523_set_clock_provider(struct iio_dev *indio_dev,
 421                               unsigned int ch, unsigned long freq)
 422 {
 423         struct ad9523_state *st = iio_priv(indio_dev);
 424         long tmp1, tmp2;
 425         bool use_alt_clk_src;
 426
 427         switch (ch) {
 428         case 0 ... 3:
 429                 use_alt_clk_src = (freq == st->vco_out_freq[AD9523_VCXO]);
 430                 break;
 431         case 4 ... 9:
 432                 tmp1 = st->vco_out_freq[AD9523_VCO1] / freq;
 433                 tmp2 = st->vco_out_freq[AD9523_VCO2] / freq;
 434                 tmp1 *= freq;
 435                 tmp2 *= freq;
 436                 use_alt_clk_src = (abs(tmp1 - freq) > abs(tmp2 - freq));
 437                 break;
 438         default:
 439                 /* Ch 10..14: No action required, return success */
 440                 return 0;
 441         }
 442
 443         return ad9523_vco_out_map(indio_dev, ch, use_alt_clk_src);
 444 }
 445
 446 static int ad9523_store_eeprom(struct iio_dev *indio_dev)
 447 {
 448         int ret, tmp;
 449
 450         ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1,
 451                            AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS);
 452         if (ret < 0)
 453                 return ret;
 454         ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL2,
 455                            AD9523_EEPROM_CTRL2_REG2EEPROM);
 456         if (ret < 0)
 457                 return ret;
 458
 459         tmp = 4;
 460         do {
 461                 msleep(20);
 462                 ret = ad9523_read(indio_dev,
 463                                   AD9523_EEPROM_DATA_XFER_STATUS);
 464                 if (ret < 0)
 465                         return ret;
 466         } while ((ret & AD9523_EEPROM_DATA_XFER_IN_PROGRESS) && tmp--);
 467
 468         ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1, 0);
 469         if (ret < 0)
 470                 return ret;
 471
 472         ret = ad9523_read(indio_dev, AD9523_EEPROM_ERROR_READBACK);
 473         if (ret < 0)
 474                 return ret;
 475
 476         if (ret & AD9523_EEPROM_ERROR_READBACK_FAIL) {
 477                 dev_err(&indio_dev->dev, "Verify EEPROM failed");
 478                 ret = -EIO;
 479         }
 480
 481         return ret;
 482 }
 483
 484 static int ad9523_sync(struct iio_dev *indio_dev)
 485 {
 486         int ret, tmp;
 487
 488         ret = ad9523_read(indio_dev, AD9523_STATUS_SIGNALS);
 489         if (ret < 0)
 490                 return ret;
 491
 492         tmp = ret;
 493         tmp |= AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL;
 494
 495         ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);
 496         if (ret < 0)
 497                 return ret;
 498
 499         ad9523_io_update(indio_dev);
 500         tmp &= ~AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL;
 501
 502         ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);
 503         if (ret < 0)
 504                 return ret;
 505
 506         return ad9523_io_update(indio_dev);
 507 }
 508
 509 static ssize_t ad9523_store(struct device *dev,
 510                                 struct device_attribute *attr,
 511                                 const char *buf, size_t len)
 512 {
 513         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 514         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 515         struct ad9523_state *st = iio_priv(indio_dev);
 516         bool state;
 517         int ret;
 518
 519         ret = strtobool(buf, &state);
 520         if (ret < 0)
 521                 return ret;
 522
 523         if (!state)
 524                 return len;
 525
 526         mutex_lock(&st->lock);
 527         switch ((u32)this_attr->address) {
 528         case AD9523_SYNC:
 529                 ret = ad9523_sync(indio_dev);
 530                 break;
 531         case AD9523_EEPROM:
 532                 ret = ad9523_store_eeprom(indio_dev);
 533                 break;
 534         default:
 535                 ret = -ENODEV;
 536         }
 537         mutex_unlock(&st->lock);
 538
 539         return ret ? ret : len;
 540 }
 541
 542 static ssize_t ad9523_show(struct device *dev,
 543                         struct device_attribute *attr,
 544                         char *buf)
 545 {
 546         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 547         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 548         struct ad9523_state *st = iio_priv(indio_dev);
 549         int ret;
 550
 551         mutex_lock(&st->lock);
 552         ret = ad9523_read(indio_dev, AD9523_READBACK_0);
 553         if (ret >= 0) {
 554                 ret = sprintf(buf, "%d\n", !!(ret & (1 <<
 555                         (u32)this_attr->address)));
 556         }
 557         mutex_unlock(&st->lock);
 558
 559         return ret;
 560 }
 561
 562 static IIO_DEVICE_ATTR(pll1_locked, S_IRUGO,
 563                         ad9523_show,
 564                         NULL,
 565                         AD9523_STAT_PLL1_LD);
 566
 567 static IIO_DEVICE_ATTR(pll2_locked, S_IRUGO,
 568                         ad9523_show,
 569                         NULL,
 570                         AD9523_STAT_PLL2_LD);
 571
 572 static IIO_DEVICE_ATTR(pll1_reference_clk_a_present, S_IRUGO,
 573                         ad9523_show,
 574                         NULL,
 575                         AD9523_STAT_REFA);
 576
 577 static IIO_DEVICE_ATTR(pll1_reference_clk_b_present, S_IRUGO,
 578                         ad9523_show,
 579                         NULL,
 580                         AD9523_STAT_REFB);
 581
 582 static IIO_DEVICE_ATTR(pll1_reference_clk_test_present, S_IRUGO,
 583                         ad9523_show,
 584                         NULL,
 585                         AD9523_STAT_REF_TEST);
 586
 587 static IIO_DEVICE_ATTR(vcxo_clk_present, S_IRUGO,
 588                         ad9523_show,
 589                         NULL,
 590                         AD9523_STAT_VCXO);
 591
 592 static IIO_DEVICE_ATTR(pll2_feedback_clk_present, S_IRUGO,
 593                         ad9523_show,
 594                         NULL,
 595                         AD9523_STAT_PLL2_FB_CLK);
 596
 597 static IIO_DEVICE_ATTR(pll2_reference_clk_present, S_IRUGO,
 598                         ad9523_show,
 599                         NULL,
 600                         AD9523_STAT_PLL2_REF_CLK);
 601
 602 static IIO_DEVICE_ATTR(sync_dividers, S_IWUSR,
 603                         NULL,
 604                         ad9523_store,
 605                         AD9523_SYNC);
 606
 607 static IIO_DEVICE_ATTR(store_eeprom, S_IWUSR,
 608                         NULL,
 609                         ad9523_store,
 610                         AD9523_EEPROM);
 611
 612 static struct attribute *ad9523_attributes[] = {
 613         &iio_dev_attr_sync_dividers.dev_attr.attr,
 614         &iio_dev_attr_store_eeprom.dev_attr.attr,
 615         &iio_dev_attr_pll2_feedback_clk_present.dev_attr.attr,
 616         &iio_dev_attr_pll2_reference_clk_present.dev_attr.attr,
 617         &iio_dev_attr_pll1_reference_clk_a_present.dev_attr.attr,
 618         &iio_dev_attr_pll1_reference_clk_b_present.dev_attr.attr,
 619         &iio_dev_attr_pll1_reference_clk_test_present.dev_attr.attr,
 620         &iio_dev_attr_vcxo_clk_present.dev_attr.attr,
 621         &iio_dev_attr_pll1_locked.dev_attr.attr,
 622         &iio_dev_attr_pll2_locked.dev_attr.attr,
 623         NULL,
 624 };
 625
 626 static const struct attribute_group ad9523_attribute_group = {
 627         .attrs = ad9523_attributes,
 628 };
 629
 630 static int ad9523_read_raw(struct iio_dev *indio_dev,
 631                            struct iio_chan_spec const *chan,
 632                            int *val,
 633                            int *val2,
 634                            long m)
 635 {
 636         struct ad9523_state *st = iio_priv(indio_dev);
 637         unsigned int code;
 638         int ret;
 639
 640         mutex_lock(&st->lock);
 641         ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));
 642         mutex_unlock(&st->lock);
 643
 644         if (ret < 0)
 645                 return ret;
 646
 647         switch (m) {
 648         case IIO_CHAN_INFO_RAW:
 649                 *val = !(ret & AD9523_CLK_DIST_PWR_DOWN_EN);
 650                 return IIO_VAL_INT;
 651         case IIO_CHAN_INFO_FREQUENCY:
 652                 *val = st->vco_out_freq[st->vco_out_map[chan->channel]] /
 653                         AD9523_CLK_DIST_DIV_REV(ret);
 654                 return IIO_VAL_INT;
 655         case IIO_CHAN_INFO_PHASE:
 656                 code = (AD9523_CLK_DIST_DIV_PHASE_REV(ret) * 3141592) /
 657                         AD9523_CLK_DIST_DIV_REV(ret);
 658                 *val = code / 1000000;
 659                 *val2 = code % 1000000;
 660                 return IIO_VAL_INT_PLUS_MICRO;
 661         default:
 662                 return -EINVAL;
 663         }
 664 };
 665
 666 static int ad9523_write_raw(struct iio_dev *indio_dev,
 667                             struct iio_chan_spec const *chan,
 668                             int val,
 669                             int val2,
 670                             long mask)
 671 {
 672         struct ad9523_state *st = iio_priv(indio_dev);
 673         unsigned int reg;
 674         int ret, tmp, code;
 675
 676         mutex_lock(&st->lock);
 677         ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));
 678         if (ret < 0)
 679                 goto out;
 680
 681         reg = ret;
 682
 683         switch (mask) {
 684         case IIO_CHAN_INFO_RAW:
 685                 if (val)
 686                         reg &= ~AD9523_CLK_DIST_PWR_DOWN_EN;
 687                 else
 688                         reg |= AD9523_CLK_DIST_PWR_DOWN_EN;
 689                 break;
 690         case IIO_CHAN_INFO_FREQUENCY:
 691                 if (val <= 0) {
 692                         ret = -EINVAL;
 693                         goto out;
 694                 }
 695                 ret = ad9523_set_clock_provider(indio_dev, chan->channel, val);
 696                 if (ret < 0)
 697                         goto out;
 698                 tmp = st->vco_out_freq[st->vco_out_map[chan->channel]] / val;
 699                 tmp = clamp(tmp, 1, 1024);
 700                 reg &= ~(0x3FF << 8);
 701                 reg |= AD9523_CLK_DIST_DIV(tmp);
 702                 break;
 703         case IIO_CHAN_INFO_PHASE:
 704                 code = val * 1000000 + val2 % 1000000;
 705                 tmp = (code * AD9523_CLK_DIST_DIV_REV(ret)) / 3141592;
 706                 tmp = clamp(tmp, 0, 63);
 707                 reg &= ~AD9523_CLK_DIST_DIV_PHASE(~0);
 708                 reg |= AD9523_CLK_DIST_DIV_PHASE(tmp);
 709                 break;
 710         default:
 711                 ret = -EINVAL;
 712                 goto out;
 713         }
 714
 715         ret = ad9523_write(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel),
 716                            reg);
 717         if (ret < 0)
 718                 goto out;
 719
 720         ad9523_io_update(indio_dev);
 721 out:
 722         mutex_unlock(&st->lock);
 723         return ret;
 724 }
 725
 726 static int ad9523_reg_access(struct iio_dev *indio_dev,
 727                               unsigned int reg, unsigned int writeval,
 728                               unsigned int *readval)
 729 {
 730         struct ad9523_state *st = iio_priv(indio_dev);
 731         int ret;
 732
 733         mutex_lock(&st->lock);
 734         if (readval == NULL) {
 735                 ret = ad9523_write(indio_dev, reg | AD9523_R1B, writeval);
 736                 ad9523_io_update(indio_dev);
 737         } else {
 738                 ret = ad9523_read(indio_dev, reg | AD9523_R1B);
 739                 if (ret < 0)
 740                         goto out_unlock;
 741                 *readval = ret;
 742                 ret = 0;
 743         }
 744
 745 out_unlock:
 746         mutex_unlock(&st->lock);
 747
 748         return ret;
 749 }
 750
 751 static const struct iio_info ad9523_info = {
 752         .read_raw = &ad9523_read_raw,
 753         .write_raw = &ad9523_write_raw,
 754         .debugfs_reg_access = &ad9523_reg_access,
 755         .attrs = &ad9523_attribute_group,
 756 };
 757
 758 static int ad9523_setup(struct iio_dev *indio_dev)
 759 {
 760         struct ad9523_state *st = iio_priv(indio_dev);
 761         struct ad9523_platform_data *pdata = st->pdata;
 762         struct ad9523_channel_spec *chan;
 763         unsigned long active_mask = 0;
 764         int ret, i;
 765
 766         ret = ad9523_write(indio_dev, AD9523_SERIAL_PORT_CONFIG,
 767                            AD9523_SER_CONF_SOFT_RESET |
 768                           (st->spi->mode & SPI_3WIRE ? 0 :
 769                           AD9523_SER_CONF_SDO_ACTIVE));
 770         if (ret < 0)
 771                 return ret;
 772
 773         ret = ad9523_write(indio_dev, AD9523_READBACK_CTRL,
 774                           AD9523_READBACK_CTRL_READ_BUFFERED);
 775         if (ret < 0)
 776                 return ret;
 777
 778         ret = ad9523_io_update(indio_dev);
 779         if (ret < 0)
 780                 return ret;
 781
 782         /*
 783          * PLL1 Setup
 784          */
 785         ret = ad9523_write(indio_dev, AD9523_PLL1_REF_A_DIVIDER,
 786                 pdata->refa_r_div);
 787         if (ret < 0)
 788                 return ret;
 789
 790         ret = ad9523_write(indio_dev, AD9523_PLL1_REF_B_DIVIDER,
 791                 pdata->refb_r_div);
 792         if (ret < 0)
 793                 return ret;
 794
 795         ret = ad9523_write(indio_dev, AD9523_PLL1_FEEDBACK_DIVIDER,
 796                 pdata->pll1_feedback_div);
 797         if (ret < 0)
 798                 return ret;
 799
 800         ret = ad9523_write(indio_dev, AD9523_PLL1_CHARGE_PUMP_CTRL,
 801                 AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(pdata->
 802                         pll1_charge_pump_current_nA) |
 803                 AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL |
 804                 AD9523_PLL1_BACKLASH_PW_MIN);
 805         if (ret < 0)
 806                 return ret;
 807
 808         ret = ad9523_write(indio_dev, AD9523_PLL1_INPUT_RECEIVERS_CTRL,
 809                 AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_RCV_EN) |
 810                 AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_RCV_EN) |
 811                 AD_IF(osc_in_diff_en, AD9523_PLL1_OSC_IN_DIFF_EN) |
 812                 AD_IF(osc_in_cmos_neg_inp_en,
 813                       AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN) |
 814                 AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_DIFF_RCV_EN) |
 815                 AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_DIFF_RCV_EN));
 816         if (ret < 0)
 817                 return ret;
 818
 819         ret = ad9523_write(indio_dev, AD9523_PLL1_REF_CTRL,
 820                 AD_IF(zd_in_diff_en, AD9523_PLL1_ZD_IN_DIFF_EN) |
 821                 AD_IF(zd_in_cmos_neg_inp_en,
 822                       AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN) |
 823                 AD_IF(zero_delay_mode_internal_en,
 824                       AD9523_PLL1_ZERO_DELAY_MODE_INT) |
 825                 AD_IF(osc_in_feedback_en, AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN) |
 826                 AD_IF(refa_cmos_neg_inp_en, AD9523_PLL1_REFA_CMOS_NEG_INP_EN) |
 827                 AD_IF(refb_cmos_neg_inp_en, AD9523_PLL1_REFB_CMOS_NEG_INP_EN));
 828         if (ret < 0)
 829                 return ret;
 830
 831         ret = ad9523_write(indio_dev, AD9523_PLL1_MISC_CTRL,
 832                 AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN |
 833                 AD9523_PLL1_REF_MODE(pdata->ref_mode));
 834         if (ret < 0)
 835                 return ret;
 836
 837         ret = ad9523_write(indio_dev, AD9523_PLL1_LOOP_FILTER_CTRL,
 838                 AD9523_PLL1_LOOP_FILTER_RZERO(pdata->pll1_loop_filter_rzero));
 839         if (ret < 0)
 840                 return ret;
 841         /*
 842          * PLL2 Setup
 843          */
 844
 845         ret = ad9523_write(indio_dev, AD9523_PLL2_CHARGE_PUMP,
 846                 AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(pdata->
 847                         pll2_charge_pump_current_nA));
 848         if (ret < 0)
 849                 return ret;
 850
 851         ret = ad9523_write(indio_dev, AD9523_PLL2_FEEDBACK_DIVIDER_AB,
 852                 AD9523_PLL2_FB_NDIV_A_CNT(pdata->pll2_ndiv_a_cnt) |
 853                 AD9523_PLL2_FB_NDIV_B_CNT(pdata->pll2_ndiv_b_cnt));
 854         if (ret < 0)
 855                 return ret;
 856
 857         ret = ad9523_write(indio_dev, AD9523_PLL2_CTRL,
 858                 AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL |
 859                 AD9523_PLL2_BACKLASH_CTRL_EN |
 860                 AD_IF(pll2_freq_doubler_en, AD9523_PLL2_FREQ_DOUBLER_EN));
 861         if (ret < 0)
 862                 return ret;
 863
 864         st->vco_freq = div_u64((unsigned long long)pdata->vcxo_freq *
 865                                (pdata->pll2_freq_doubler_en ? 2 : 1) *
 866                                AD9523_PLL2_FB_NDIV(pdata->pll2_ndiv_a_cnt,
 867                                                    pdata->pll2_ndiv_b_cnt),
 868                                pdata->pll2_r2_div);
 869
 870         ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_CTRL,
 871                 AD9523_PLL2_VCO_CALIBRATE);
 872         if (ret < 0)
 873                 return ret;
 874
 875         ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_DIVIDER,
 876                 AD9523_PLL2_VCO_DIV_M1(pdata->pll2_vco_div_m1) |
 877                 AD9523_PLL2_VCO_DIV_M2(pdata->pll2_vco_div_m2) |
 878                 AD_IFE(pll2_vco_div_m1, 0,
 879                        AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN) |
 880                 AD_IFE(pll2_vco_div_m2, 0,
 881                        AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN));
 882         if (ret < 0)
 883                 return ret;
 884
 885         if (pdata->pll2_vco_div_m1)
 886                 st->vco_out_freq[AD9523_VCO1] =
 887                         st->vco_freq / pdata->pll2_vco_div_m1;
 888
 889         if (pdata->pll2_vco_div_m2)
 890                 st->vco_out_freq[AD9523_VCO2] =
 891                         st->vco_freq / pdata->pll2_vco_div_m2;
 892
 893         st->vco_out_freq[AD9523_VCXO] = pdata->vcxo_freq;
 894
 895         ret = ad9523_write(indio_dev, AD9523_PLL2_R2_DIVIDER,
 896                 AD9523_PLL2_R2_DIVIDER_VAL(pdata->pll2_r2_div));
 897         if (ret < 0)
 898                 return ret;
 899
 900         ret = ad9523_write(indio_dev, AD9523_PLL2_LOOP_FILTER_CTRL,
 901                 AD9523_PLL2_LOOP_FILTER_CPOLE1(pdata->cpole1) |
 902                 AD9523_PLL2_LOOP_FILTER_RZERO(pdata->rzero) |
 903                 AD9523_PLL2_LOOP_FILTER_RPOLE2(pdata->rpole2) |
 904                 AD_IF(rzero_bypass_en,
 905                       AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN));
 906         if (ret < 0)
 907                 return ret;
 908
 909         for (i = 0; i < pdata->num_channels; i++) {
 910                 chan = &pdata->channels[i];
 911                 if (chan->channel_num < AD9523_NUM_CHAN) {
 912                         __set_bit(chan->channel_num, &active_mask);
 913                         ret = ad9523_write(indio_dev,
 914                                 AD9523_CHANNEL_CLOCK_DIST(chan->channel_num),
 915                                 AD9523_CLK_DIST_DRIVER_MODE(chan->driver_mode) |
 916                                 AD9523_CLK_DIST_DIV(chan->channel_divider) |
 917                                 AD9523_CLK_DIST_DIV_PHASE(chan->divider_phase) |
 918                                 (chan->sync_ignore_en ?
 919                                         AD9523_CLK_DIST_IGNORE_SYNC_EN : 0) |
 920                                 (chan->divider_output_invert_en ?
 921                                         AD9523_CLK_DIST_INV_DIV_OUTPUT_EN : 0) |
 922                                 (chan->low_power_mode_en ?
 923                                         AD9523_CLK_DIST_LOW_PWR_MODE_EN : 0) |
 924                                 (chan->output_dis ?
 925                                         AD9523_CLK_DIST_PWR_DOWN_EN : 0));
 926                         if (ret < 0)
 927                                 return ret;
 928
 929                         ret = ad9523_vco_out_map(indio_dev, chan->channel_num,
 930                                            chan->use_alt_clock_src);
 931                         if (ret < 0)
 932                                 return ret;
 933
 934                         st->ad9523_channels[i].type = IIO_ALTVOLTAGE;
 935                         st->ad9523_channels[i].output = 1;
 936                         st->ad9523_channels[i].indexed = 1;
 937                         st->ad9523_channels[i].channel = chan->channel_num;
 938                         st->ad9523_channels[i].extend_name =
 939                                 chan->extended_name;
 940                         st->ad9523_channels[i].info_mask_separate =
 941                                 BIT(IIO_CHAN_INFO_RAW) |
 942                                 BIT(IIO_CHAN_INFO_PHASE) |
 943                                 BIT(IIO_CHAN_INFO_FREQUENCY);
 944                 }
 945         }
 946
 947         for_each_clear_bit(i, &active_mask, AD9523_NUM_CHAN) {
 948                 ret = ad9523_write(indio_dev,
 949                              AD9523_CHANNEL_CLOCK_DIST(i),
 950                              AD9523_CLK_DIST_DRIVER_MODE(TRISTATE) |
 951                              AD9523_CLK_DIST_PWR_DOWN_EN);
 952                 if (ret < 0)
 953                         return ret;
 954         }
 955
 956         ret = ad9523_write(indio_dev, AD9523_POWER_DOWN_CTRL, 0);
 957         if (ret < 0)
 958                 return ret;
 959
 960         ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS,
 961                            AD9523_STATUS_MONITOR_01_PLL12_LOCKED);
 962         if (ret < 0)
 963                 return ret;
 964
 965         ret = ad9523_io_update(indio_dev);
 966         if (ret < 0)
 967                 return ret;
 968
 969         return 0;
 970 }
 971
 972 static int ad9523_probe(struct spi_device *spi)
 973 {
 974         struct ad9523_platform_data *pdata = spi->dev.platform_data;
 975         struct iio_dev *indio_dev;
 976         struct ad9523_state *st;
 977         int ret;
 978
 979         if (!pdata) {
 980                 dev_err(&spi->dev, "no platform data?\n");
 981                 return -EINVAL;
 982         }
 983
 984         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 985         if (indio_dev == NULL)
 986                 return -ENOMEM;
 987
 988         st = iio_priv(indio_dev);
 989
 990         mutex_init(&st->lock);
 991
 992         st->reg = devm_regulator_get(&spi->dev, "vcc");
 993         if (!IS_ERR(st->reg)) {
 994                 ret = regulator_enable(st->reg);
 995                 if (ret)
 996                         return ret;
 997         }
 998
 999         st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown",
1000                 GPIOD_OUT_HIGH);
1001         if (IS_ERR(st->pwrdown_gpio)) {
1002                 ret = PTR_ERR(st->pwrdown_gpio);
1003                 goto error_disable_reg;
1004         }
1005
1006         st->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
1007                 GPIOD_OUT_LOW);
1008         if (IS_ERR(st->reset_gpio)) {
1009                 ret = PTR_ERR(st->reset_gpio);
1010                 goto error_disable_reg;
1011         }
1012
1013         if (st->reset_gpio) {
1014                 udelay(1);
1015                 gpiod_direction_output(st->reset_gpio, 1);
1016         }
1017
1018         st->sync_gpio = devm_gpiod_get_optional(&spi->dev, "sync",
1019                 GPIOD_OUT_HIGH);
1020         if (IS_ERR(st->sync_gpio)) {
1021                 ret = PTR_ERR(st->sync_gpio);
1022                 goto error_disable_reg;
1023         }
1024
1025         spi_set_drvdata(spi, indio_dev);
1026         st->spi = spi;
1027         st->pdata = pdata;
1028
1029         indio_dev->dev.parent = &spi->dev;
1030         indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
1031                           spi_get_device_id(spi)->name;
1032         indio_dev->info = &ad9523_info;
1033         indio_dev->modes = INDIO_DIRECT_MODE;
1034         indio_dev->channels = st->ad9523_channels;
1035         indio_dev->num_channels = pdata->num_channels;
1036
1037         ret = ad9523_setup(indio_dev);
1038         if (ret < 0)
1039                 goto error_disable_reg;
1040
1041         ret = iio_device_register(indio_dev);
1042         if (ret)
1043                 goto error_disable_reg;
1044
1045         dev_info(&spi->dev, "probed %s\n", indio_dev->name);
1046
1047         return 0;
1048
1049 error_disable_reg:
1050         if (!IS_ERR(st->reg))
1051                 regulator_disable(st->reg);
1052
1053         return ret;
1054 }
1055
1056 static int ad9523_remove(struct spi_device *spi)
1057 {
1058         struct iio_dev *indio_dev = spi_get_drvdata(spi);
1059         struct ad9523_state *st = iio_priv(indio_dev);
1060
1061         iio_device_unregister(indio_dev);
1062
1063         if (!IS_ERR(st->reg))
1064                 regulator_disable(st->reg);
1065
1066         return 0;
1067 }
1068
1069 static const struct spi_device_id ad9523_id[] = {
1070         {"ad9523-1", 9523},
1071         {}
1072 };
1073 MODULE_DEVICE_TABLE(spi, ad9523_id);
1074
1075 static struct spi_driver ad9523_driver = {
1076         .driver = {
1077                 .name   = "ad9523",
1078         },
1079         .probe          = ad9523_probe,
1080         .remove         = ad9523_remove,
1081         .id_table       = ad9523_id,
1082 };
1083 module_spi_driver(ad9523_driver);
1084
1085 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1086 MODULE_DESCRIPTION("Analog Devices AD9523 CLOCKDIST/PLL");
1087 MODULE_LICENSE("GPL v2");