drivers/iio/adc/ti-ads124s08.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* TI ADS124S0X chip family driver
   3  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   4  */
   5
   6 #include <linux/err.h>
   7 #include <linux/delay.h>
   8 #include <linux/device.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_gpio.h>
  13 #include <linux/slab.h>
  14 #include <linux/sysfs.h>
  15
  16 #include <linux/gpio/consumer.h>
  17 #include <linux/spi/spi.h>
  18
  19 #include <linux/iio/iio.h>
  20 #include <linux/iio/buffer.h>
  21 #include <linux/iio/trigger_consumer.h>
  22 #include <linux/iio/triggered_buffer.h>
  23 #include <linux/iio/sysfs.h>
  24
  25 /* Commands */
  26 #define ADS124S08_CMD_NOP       0x00
  27 #define ADS124S08_CMD_WAKEUP    0x02
  28 #define ADS124S08_CMD_PWRDWN    0x04
  29 #define ADS124S08_CMD_RESET     0x06
  30 #define ADS124S08_CMD_START     0x08
  31 #define ADS124S08_CMD_STOP      0x0a
  32 #define ADS124S08_CMD_SYOCAL    0x16
  33 #define ADS124S08_CMD_SYGCAL    0x17
  34 #define ADS124S08_CMD_SFOCAL    0x19
  35 #define ADS124S08_CMD_RDATA     0x12
  36 #define ADS124S08_CMD_RREG      0x20
  37 #define ADS124S08_CMD_WREG      0x40
  38
  39 /* Registers */
  40 #define ADS124S08_ID_REG        0x00
  41 #define ADS124S08_STATUS        0x01
  42 #define ADS124S08_INPUT_MUX     0x02
  43 #define ADS124S08_PGA           0x03
  44 #define ADS124S08_DATA_RATE     0x04
  45 #define ADS124S08_REF           0x05
  46 #define ADS124S08_IDACMAG       0x06
  47 #define ADS124S08_IDACMUX       0x07
  48 #define ADS124S08_VBIAS         0x08
  49 #define ADS124S08_SYS           0x09
  50 #define ADS124S08_OFCAL0        0x0a
  51 #define ADS124S08_OFCAL1        0x0b
  52 #define ADS124S08_OFCAL2        0x0c
  53 #define ADS124S08_FSCAL0        0x0d
  54 #define ADS124S08_FSCAL1        0x0e
  55 #define ADS124S08_FSCAL2        0x0f
  56 #define ADS124S08_GPIODAT       0x10
  57 #define ADS124S08_GPIOCON       0x11
  58
  59 /* ADS124S0x common channels */
  60 #define ADS124S08_AIN0          0x00
  61 #define ADS124S08_AIN1          0x01
  62 #define ADS124S08_AIN2          0x02
  63 #define ADS124S08_AIN3          0x03
  64 #define ADS124S08_AIN4          0x04
  65 #define ADS124S08_AIN5          0x05
  66 #define ADS124S08_AINCOM        0x0c
  67 /* ADS124S08 only channels */
  68 #define ADS124S08_AIN6          0x06
  69 #define ADS124S08_AIN7          0x07
  70 #define ADS124S08_AIN8          0x08
  71 #define ADS124S08_AIN9          0x09
  72 #define ADS124S08_AIN10         0x0a
  73 #define ADS124S08_AIN11         0x0b
  74 #define ADS124S08_MAX_CHANNELS  12
  75
  76 #define ADS124S08_POS_MUX_SHIFT 0x04
  77 #define ADS124S08_INT_REF               0x09
  78
  79 #define ADS124S08_START_REG_MASK        0x1f
  80 #define ADS124S08_NUM_BYTES_MASK        0x1f
  81
  82 #define ADS124S08_START_CONV    0x01
  83 #define ADS124S08_STOP_CONV     0x00
  84
  85 enum ads124s_id {
  86         ADS124S08_ID,
  87         ADS124S06_ID,
  88 };
  89
  90 struct ads124s_chip_info {
  91         const struct iio_chan_spec *channels;
  92         unsigned int num_channels;
  93 };
  94
  95 struct ads124s_private {
  96         const struct ads124s_chip_info  *chip_info;
  97         struct gpio_desc *reset_gpio;
  98         struct spi_device *spi;
  99         struct mutex lock;
 100         u8 data[5] ____cacheline_aligned;
 101 };
 102
 103 #define ADS124S08_CHAN(index)                                   \
 104 {                                                               \
 105         .type = IIO_VOLTAGE,                                    \
 106         .indexed = 1,                                           \
 107         .channel = index,                                       \
 108         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 109         .scan_index = index,                                    \
 110         .scan_type = {                                          \
 111                 .sign = 'u',                                    \
 112                 .realbits = 32,                                 \
 113                 .storagebits = 32,                              \
 114         },                                                      \
 115 }
 116
 117 static const struct iio_chan_spec ads124s06_channels[] = {
 118         ADS124S08_CHAN(0),
 119         ADS124S08_CHAN(1),
 120         ADS124S08_CHAN(2),
 121         ADS124S08_CHAN(3),
 122         ADS124S08_CHAN(4),
 123         ADS124S08_CHAN(5),
 124 };
 125
 126 static const struct iio_chan_spec ads124s08_channels[] = {
 127         ADS124S08_CHAN(0),
 128         ADS124S08_CHAN(1),
 129         ADS124S08_CHAN(2),
 130         ADS124S08_CHAN(3),
 131         ADS124S08_CHAN(4),
 132         ADS124S08_CHAN(5),
 133         ADS124S08_CHAN(6),
 134         ADS124S08_CHAN(7),
 135         ADS124S08_CHAN(8),
 136         ADS124S08_CHAN(9),
 137         ADS124S08_CHAN(10),
 138         ADS124S08_CHAN(11),
 139 };
 140
 141 static const struct ads124s_chip_info ads124s_chip_info_tbl[] = {
 142         [ADS124S08_ID] = {
 143                 .channels = ads124s08_channels,
 144                 .num_channels = ARRAY_SIZE(ads124s08_channels),
 145         },
 146         [ADS124S06_ID] = {
 147                 .channels = ads124s06_channels,
 148                 .num_channels = ARRAY_SIZE(ads124s06_channels),
 149         },
 150 };
 151
 152 static int ads124s_write_cmd(struct iio_dev *indio_dev, u8 command)
 153 {
 154         struct ads124s_private *priv = iio_priv(indio_dev);
 155
 156         priv->data[0] = command;
 157
 158         return spi_write(priv->spi, &priv->data[0], 1);
 159 }
 160
 161 static int ads124s_write_reg(struct iio_dev *indio_dev, u8 reg, u8 data)
 162 {
 163         struct ads124s_private *priv = iio_priv(indio_dev);
 164
 165         priv->data[0] = ADS124S08_CMD_WREG | reg;
 166         priv->data[1] = 0x0;
 167         priv->data[2] = data;
 168
 169         return spi_write(priv->spi, &priv->data[0], 3);
 170 }
 171
 172 static int ads124s_reset(struct iio_dev *indio_dev)
 173 {
 174         struct ads124s_private *priv = iio_priv(indio_dev);
 175
 176         if (priv->reset_gpio) {
 177                 gpiod_set_value(priv->reset_gpio, 0);
 178                 udelay(200);
 179                 gpiod_set_value(priv->reset_gpio, 1);
 180         } else {
 181                 return ads124s_write_cmd(indio_dev, ADS124S08_CMD_RESET);
 182         }
 183
 184         return 0;
 185 };
 186
 187 static int ads124s_read(struct iio_dev *indio_dev, unsigned int chan)
 188 {
 189         struct ads124s_private *priv = iio_priv(indio_dev);
 190         int ret;
 191         u32 tmp;
 192         struct spi_transfer t[] = {
 193                 {
 194                         .tx_buf = &priv->data[0],
 195                         .len = 4,
 196                         .cs_change = 1,
 197                 }, {
 198                         .tx_buf = &priv->data[1],
 199                         .rx_buf = &priv->data[1],
 200                         .len = 4,
 201                 },
 202         };
 203
 204         priv->data[0] = ADS124S08_CMD_RDATA;
 205         memset(&priv->data[1], ADS124S08_CMD_NOP, sizeof(priv->data) - 1);
 206
 207         ret = spi_sync_transfer(priv->spi, t, ARRAY_SIZE(t));
 208         if (ret < 0)
 209                 return ret;
 210
 211         tmp = priv->data[2] << 16 | priv->data[3] << 8 | priv->data[4];
 212
 213         return tmp;
 214 }
 215
 216 static int ads124s_read_raw(struct iio_dev *indio_dev,
 217                             struct iio_chan_spec const *chan,
 218                             int *val, int *val2, long m)
 219 {
 220         struct ads124s_private *priv = iio_priv(indio_dev);
 221         int ret;
 222
 223         mutex_lock(&priv->lock);
 224         switch (m) {
 225         case IIO_CHAN_INFO_RAW:
 226                 ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX,
 227                                         chan->channel);
 228                 if (ret) {
 229                         dev_err(&priv->spi->dev, "Set ADC CH failed\n");
 230                         goto out;
 231                 }
 232
 233                 ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV);
 234                 if (ret) {
 235                         dev_err(&priv->spi->dev, "Start conversions failed\n");
 236                         goto out;
 237                 }
 238
 239                 ret = ads124s_read(indio_dev, chan->channel);
 240                 if (ret < 0) {
 241                         dev_err(&priv->spi->dev, "Read ADC failed\n");
 242                         goto out;
 243                 }
 244
 245                 *val = ret;
 246
 247                 ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV);
 248                 if (ret) {
 249                         dev_err(&priv->spi->dev, "Stop conversions failed\n");
 250                         goto out;
 251                 }
 252
 253                 ret = IIO_VAL_INT;
 254                 break;
 255         default:
 256                 ret = -EINVAL;
 257                 break;
 258         }
 259 out:
 260         mutex_unlock(&priv->lock);
 261         return ret;
 262 }
 263
 264 static const struct iio_info ads124s_info = {
 265         .read_raw = &ads124s_read_raw,
 266 };
 267
 268 static irqreturn_t ads124s_trigger_handler(int irq, void *p)
 269 {
 270         struct iio_poll_func *pf = p;
 271         struct iio_dev *indio_dev = pf->indio_dev;
 272         struct ads124s_private *priv = iio_priv(indio_dev);
 273         u32 buffer[ADS124S08_MAX_CHANNELS + sizeof(s64)/sizeof(u16)];
 274         int scan_index, j = 0;
 275         int ret;
 276
 277         for_each_set_bit(scan_index, indio_dev->active_scan_mask,
 278                          indio_dev->masklength) {
 279                 ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX,
 280                                         scan_index);
 281                 if (ret)
 282                         dev_err(&priv->spi->dev, "Set ADC CH failed\n");
 283
 284                 ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV);
 285                 if (ret)
 286                         dev_err(&priv->spi->dev, "Start ADC conversions failed\n");
 287
 288                 buffer[j] = ads124s_read(indio_dev, scan_index);
 289                 ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV);
 290                 if (ret)
 291                         dev_err(&priv->spi->dev, "Stop ADC conversions failed\n");
 292
 293                 j++;
 294         }
 295
 296         iio_push_to_buffers_with_timestamp(indio_dev, buffer,
 297                         pf->timestamp);
 298
 299         iio_trigger_notify_done(indio_dev->trig);
 300
 301         return IRQ_HANDLED;
 302 }
 303
 304 static int ads124s_probe(struct spi_device *spi)
 305 {
 306         struct ads124s_private *ads124s_priv;
 307         struct iio_dev *indio_dev;
 308         const struct spi_device_id *spi_id = spi_get_device_id(spi);
 309         int ret;
 310
 311         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*ads124s_priv));
 312         if (indio_dev == NULL)
 313                 return -ENOMEM;
 314
 315         ads124s_priv = iio_priv(indio_dev);
 316
 317         ads124s_priv->reset_gpio = devm_gpiod_get_optional(&spi->dev,
 318                                                    "reset", GPIOD_OUT_LOW);
 319         if (IS_ERR(ads124s_priv->reset_gpio))
 320                 dev_info(&spi->dev, "Reset GPIO not defined\n");
 321
 322         ads124s_priv->chip_info = &ads124s_chip_info_tbl[spi_id->driver_data];
 323
 324         spi_set_drvdata(spi, indio_dev);
 325
 326         ads124s_priv->spi = spi;
 327
 328         indio_dev->name = spi_id->name;
 329         indio_dev->dev.parent = &spi->dev;
 330         indio_dev->dev.of_node = spi->dev.of_node;
 331         indio_dev->modes = INDIO_DIRECT_MODE;
 332         indio_dev->channels = ads124s_priv->chip_info->channels;
 333         indio_dev->num_channels = ads124s_priv->chip_info->num_channels;
 334         indio_dev->info = &ads124s_info;
 335
 336         mutex_init(&ads124s_priv->lock);
 337
 338         ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
 339                                               ads124s_trigger_handler, NULL);
 340         if (ret) {
 341                 dev_err(&spi->dev, "iio triggered buffer setup failed\n");
 342                 return ret;
 343         }
 344
 345         ads124s_reset(indio_dev);
 346
 347         return devm_iio_device_register(&spi->dev, indio_dev);
 348 }
 349
 350 static const struct spi_device_id ads124s_id[] = {
 351         { "ads124s06", ADS124S06_ID },
 352         { "ads124s08", ADS124S08_ID },
 353         { }
 354 };
 355 MODULE_DEVICE_TABLE(spi, ads124s_id);
 356
 357 static const struct of_device_id ads124s_of_table[] = {
 358         { .compatible = "ti,ads124s06" },
 359         { .compatible = "ti,ads124s08" },
 360         { },
 361 };
 362 MODULE_DEVICE_TABLE(of, ads124s_of_table);
 363
 364 static struct spi_driver ads124s_driver = {
 365         .driver = {
 366                 .name   = "ads124s08",
 367                 .of_match_table = ads124s_of_table,
 368         },
 369         .probe          = ads124s_probe,
 370         .id_table       = ads124s_id,
 371 };
 372 module_spi_driver(ads124s_driver);
 373
 374 MODULE_AUTHOR("Dan Murphy <dmuprhy@ti.com>");
 375 MODULE_DESCRIPTION("TI TI_ADS12S0X ADC");
 376 MODULE_LICENSE("GPL v2");