drivers/iio/adc/stm32-dfsdm-adc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * This file is the ADC part of the STM32 DFSDM driver
   4  *
   5  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   6  * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
   7  */
   8
   9 #include <linux/dmaengine.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/iio/adc/stm32-dfsdm-adc.h>
  12 #include <linux/iio/buffer.h>
  13 #include <linux/iio/hw-consumer.h>
  14 #include <linux/iio/sysfs.h>
  15 #include <linux/iio/timer/stm32-lptim-trigger.h>
  16 #include <linux/iio/timer/stm32-timer-trigger.h>
  17 #include <linux/iio/trigger.h>
  18 #include <linux/iio/trigger_consumer.h>
  19 #include <linux/iio/triggered_buffer.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/of_device.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regmap.h>
  25 #include <linux/slab.h>
  26
  27 #include "stm32-dfsdm.h"
  28
  29 #define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
  30
  31 /* Conversion timeout */
  32 #define DFSDM_TIMEOUT_US 100000
  33 #define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
  34
  35 /* Oversampling attribute default */
  36 #define DFSDM_DEFAULT_OVERSAMPLING  100
  37
  38 /* Oversampling max values */
  39 #define DFSDM_MAX_INT_OVERSAMPLING 256
  40 #define DFSDM_MAX_FL_OVERSAMPLING 1024
  41
  42 /* Limit filter output resolution to 31 bits. (i.e. sample range is +/-2^30) */
  43 #define DFSDM_DATA_MAX BIT(30)
  44 /*
  45  * Data are output as two's complement data in a 24 bit field.
  46  * Data from filters are in the range +/-2^(n-1)
  47  * 2^(n-1) maximum positive value cannot be coded in 2's complement n bits
  48  * An extra bit is required to avoid wrap-around of the binary code for 2^(n-1)
  49  * So, the resolution of samples from filter is actually limited to 23 bits
  50  */
  51 #define DFSDM_DATA_RES 24
  52
  53 /* Filter configuration */
  54 #define DFSDM_CR1_CFG_MASK (DFSDM_CR1_RCH_MASK | DFSDM_CR1_RCONT_MASK | \
  55                             DFSDM_CR1_RSYNC_MASK | DFSDM_CR1_JSYNC_MASK | \
  56                             DFSDM_CR1_JSCAN_MASK)
  57
  58 enum sd_converter_type {
  59         DFSDM_AUDIO,
  60         DFSDM_IIO,
  61 };
  62
  63 struct stm32_dfsdm_dev_data {
  64         int type;
  65         int (*init)(struct iio_dev *indio_dev);
  66         unsigned int num_channels;
  67         const struct regmap_config *regmap_cfg;
  68 };
  69
  70 struct stm32_dfsdm_adc {
  71         struct stm32_dfsdm *dfsdm;
  72         const struct stm32_dfsdm_dev_data *dev_data;
  73         unsigned int fl_id;
  74         unsigned int nconv;
  75         unsigned long smask;
  76
  77         /* ADC specific */
  78         unsigned int oversamp;
  79         struct iio_hw_consumer *hwc;
  80         struct completion completion;
  81         u32 *buffer;
  82
  83         /* Audio specific */
  84         unsigned int spi_freq;  /* SPI bus clock frequency */
  85         unsigned int sample_freq; /* Sample frequency after filter decimation */
  86         int (*cb)(const void *data, size_t size, void *cb_priv);
  87         void *cb_priv;
  88
  89         /* DMA */
  90         u8 *rx_buf;
  91         unsigned int bufi; /* Buffer current position */
  92         unsigned int buf_sz; /* Buffer size */
  93         struct dma_chan *dma_chan;
  94         dma_addr_t dma_buf;
  95 };
  96
  97 struct stm32_dfsdm_str2field {
  98         const char      *name;
  99         unsigned int    val;
 100 };
 101
 102 /* DFSDM channel serial interface type */
 103 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
 104         { "SPI_R", 0 }, /* SPI with data on rising edge */
 105         { "SPI_F", 1 }, /* SPI with data on falling edge */
 106         { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */
 107         { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */
 108         {},
 109 };
 110
 111 /* DFSDM channel clock source */
 112 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
 113         /* External SPI clock (CLKIN x) */
 114         { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
 115         /* Internal SPI clock (CLKOUT) */
 116         { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
 117         /* Internal SPI clock divided by 2 (falling edge) */
 118         { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
 119         /* Internal SPI clock divided by 2 (falling edge) */
 120         { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
 121         {},
 122 };
 123
 124 static int stm32_dfsdm_str2val(const char *str,
 125                                const struct stm32_dfsdm_str2field *list)
 126 {
 127         const struct stm32_dfsdm_str2field *p = list;
 128
 129         for (p = list; p && p->name; p++)
 130                 if (!strcmp(p->name, str))
 131                         return p->val;
 132
 133         return -EINVAL;
 134 }
 135
 136 /**
 137  * struct stm32_dfsdm_trig_info - DFSDM trigger info
 138  * @name:               name of the trigger, corresponding to its source
 139  * @jextsel:            trigger signal selection
 140  */
 141 struct stm32_dfsdm_trig_info {
 142         const char *name;
 143         unsigned int jextsel;
 144 };
 145
 146 /* hardware injected trigger enable, edge selection */
 147 enum stm32_dfsdm_jexten {
 148         STM32_DFSDM_JEXTEN_DISABLED,
 149         STM32_DFSDM_JEXTEN_RISING_EDGE,
 150         STM32_DFSDM_JEXTEN_FALLING_EDGE,
 151         STM32_DFSDM_EXTEN_BOTH_EDGES,
 152 };
 153
 154 static const struct stm32_dfsdm_trig_info stm32_dfsdm_trigs[] = {
 155         { TIM1_TRGO, 0 },
 156         { TIM1_TRGO2, 1 },
 157         { TIM8_TRGO, 2 },
 158         { TIM8_TRGO2, 3 },
 159         { TIM3_TRGO, 4 },
 160         { TIM4_TRGO, 5 },
 161         { TIM16_OC1, 6 },
 162         { TIM6_TRGO, 7 },
 163         { TIM7_TRGO, 8 },
 164         { LPTIM1_OUT, 26 },
 165         { LPTIM2_OUT, 27 },
 166         { LPTIM3_OUT, 28 },
 167         {},
 168 };
 169
 170 static int stm32_dfsdm_get_jextsel(struct iio_dev *indio_dev,
 171                                    struct iio_trigger *trig)
 172 {
 173         int i;
 174
 175         /* lookup triggers registered by stm32 timer trigger driver */
 176         for (i = 0; stm32_dfsdm_trigs[i].name; i++) {
 177                 /**
 178                  * Checking both stm32 timer trigger type and trig name
 179                  * should be safe against arbitrary trigger names.
 180                  */
 181                 if ((is_stm32_timer_trigger(trig) ||
 182                      is_stm32_lptim_trigger(trig)) &&
 183                     !strcmp(stm32_dfsdm_trigs[i].name, trig->name)) {
 184                         return stm32_dfsdm_trigs[i].jextsel;
 185                 }
 186         }
 187
 188         return -EINVAL;
 189 }
 190
 191 static int stm32_dfsdm_compute_osrs(struct stm32_dfsdm_filter *fl,
 192                                     unsigned int fast, unsigned int oversamp)
 193 {
 194         unsigned int i, d, fosr, iosr;
 195         u64 res, max;
 196         int bits, shift;
 197         unsigned int m = 1;     /* multiplication factor */
 198         unsigned int p = fl->ford;      /* filter order (ford) */
 199         struct stm32_dfsdm_filter_osr *flo = &fl->flo[fast];
 200
 201         pr_debug("%s: Requested oversampling: %d\n",  __func__, oversamp);
 202         /*
 203          * This function tries to compute filter oversampling and integrator
 204          * oversampling, base on oversampling ratio requested by user.
 205          *
 206          * Decimation d depends on the filter order and the oversampling ratios.
 207          * ford: filter order
 208          * fosr: filter over sampling ratio
 209          * iosr: integrator over sampling ratio
 210          */
 211         if (fl->ford == DFSDM_FASTSINC_ORDER) {
 212                 m = 2;
 213                 p = 2;
 214         }
 215
 216         /*
 217          * Look for filter and integrator oversampling ratios which allows
 218          * to maximize data output resolution.
 219          */
 220         for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
 221                 for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
 222                         if (fast)
 223                                 d = fosr * iosr;
 224                         else if (fl->ford == DFSDM_FASTSINC_ORDER)
 225                                 d = fosr * (iosr + 3) + 2;
 226                         else
 227                                 d = fosr * (iosr - 1 + p) + p;
 228
 229                         if (d > oversamp)
 230                                 break;
 231                         else if (d != oversamp)
 232                                 continue;
 233                         /*
 234                          * Check resolution (limited to signed 32 bits)
 235                          *   res <= 2^31
 236                          * Sincx filters:
 237                          *   res = m * fosr^p x iosr (with m=1, p=ford)
 238                          * FastSinc filter
 239                          *   res = m * fosr^p x iosr (with m=2, p=2)
 240                          */
 241                         res = fosr;
 242                         for (i = p - 1; i > 0; i--) {
 243                                 res = res * (u64)fosr;
 244                                 if (res > DFSDM_DATA_MAX)
 245                                         break;
 246                         }
 247                         if (res > DFSDM_DATA_MAX)
 248                                 continue;
 249
 250                         res = res * (u64)m * (u64)iosr;
 251                         if (res > DFSDM_DATA_MAX)
 252                                 continue;
 253
 254                         if (res >= flo->res) {
 255                                 flo->res = res;
 256                                 flo->fosr = fosr;
 257                                 flo->iosr = iosr;
 258
 259                                 bits = fls(flo->res);
 260                                 /* 8 LBSs in data register contain chan info */
 261                                 max = flo->res << 8;
 262
 263                                 /* if resolution is not a power of two */
 264                                 if (flo->res > BIT(bits - 1))
 265                                         bits++;
 266                                 else
 267                                         max--;
 268
 269                                 shift = DFSDM_DATA_RES - bits;
 270                                 /*
 271                                  * Compute right/left shift
 272                                  * Right shift is performed by hardware
 273                                  * when transferring samples to data register.
 274                                  * Left shift is done by software on buffer
 275                                  */
 276                                 if (shift > 0) {
 277                                         /* Resolution is lower than 24 bits */
 278                                         flo->rshift = 0;
 279                                         flo->lshift = shift;
 280                                 } else {
 281                                         /*
 282                                          * If resolution is 24 bits or more,
 283                                          * max positive value may be ambiguous
 284                                          * (equal to max negative value as sign
 285                                          * bit is dropped).
 286                                          * Reduce resolution to 23 bits (rshift)
 287                                          * to keep the sign on bit 23 and treat
 288                                          * saturation before rescaling on 24
 289                                          * bits (lshift).
 290                                          */
 291                                         flo->rshift = 1 - shift;
 292                                         flo->lshift = 1;
 293                                         max >>= flo->rshift;
 294                                 }
 295                                 flo->max = (s32)max;
 296
 297                                 pr_debug("%s: fast %d, fosr %d, iosr %d, res 0x%llx/%d bits, rshift %d, lshift %d\n",
 298                                          __func__, fast, flo->fosr, flo->iosr,
 299                                          flo->res, bits, flo->rshift,
 300                                          flo->lshift);
 301                         }
 302                 }
 303         }
 304
 305         if (!flo->res)
 306                 return -EINVAL;
 307
 308         return 0;
 309 }
 310
 311 static int stm32_dfsdm_compute_all_osrs(struct iio_dev *indio_dev,
 312                                         unsigned int oversamp)
 313 {
 314         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 315         struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
 316         int ret0, ret1;
 317
 318         memset(&fl->flo[0], 0, sizeof(fl->flo[0]));
 319         memset(&fl->flo[1], 0, sizeof(fl->flo[1]));
 320
 321         ret0 = stm32_dfsdm_compute_osrs(fl, 0, oversamp);
 322         ret1 = stm32_dfsdm_compute_osrs(fl, 1, oversamp);
 323         if (ret0 < 0 && ret1 < 0) {
 324                 dev_err(&indio_dev->dev,
 325                         "Filter parameters not found: errors %d/%d\n",
 326                         ret0, ret1);
 327                 return -EINVAL;
 328         }
 329
 330         return 0;
 331 }
 332
 333 static int stm32_dfsdm_start_channel(struct stm32_dfsdm_adc *adc)
 334 {
 335         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 336         struct regmap *regmap = adc->dfsdm->regmap;
 337         const struct iio_chan_spec *chan;
 338         unsigned int bit;
 339         int ret;
 340
 341         for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
 342                 chan = indio_dev->channels + bit;
 343                 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
 344                                          DFSDM_CHCFGR1_CHEN_MASK,
 345                                          DFSDM_CHCFGR1_CHEN(1));
 346                 if (ret < 0)
 347                         return ret;
 348         }
 349
 350         return 0;
 351 }
 352
 353 static void stm32_dfsdm_stop_channel(struct stm32_dfsdm_adc *adc)
 354 {
 355         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 356         struct regmap *regmap = adc->dfsdm->regmap;
 357         const struct iio_chan_spec *chan;
 358         unsigned int bit;
 359
 360         for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
 361                 chan = indio_dev->channels + bit;
 362                 regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
 363                                    DFSDM_CHCFGR1_CHEN_MASK,
 364                                    DFSDM_CHCFGR1_CHEN(0));
 365         }
 366 }
 367
 368 static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
 369                                       struct stm32_dfsdm_channel *ch)
 370 {
 371         unsigned int id = ch->id;
 372         struct regmap *regmap = dfsdm->regmap;
 373         int ret;
 374
 375         ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
 376                                  DFSDM_CHCFGR1_SITP_MASK,
 377                                  DFSDM_CHCFGR1_SITP(ch->type));
 378         if (ret < 0)
 379                 return ret;
 380         ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
 381                                  DFSDM_CHCFGR1_SPICKSEL_MASK,
 382                                  DFSDM_CHCFGR1_SPICKSEL(ch->src));
 383         if (ret < 0)
 384                 return ret;
 385         return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
 386                                   DFSDM_CHCFGR1_CHINSEL_MASK,
 387                                   DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
 388 }
 389
 390 static int stm32_dfsdm_start_filter(struct stm32_dfsdm_adc *adc,
 391                                     unsigned int fl_id,
 392                                     struct iio_trigger *trig)
 393 {
 394         struct stm32_dfsdm *dfsdm = adc->dfsdm;
 395         int ret;
 396
 397         /* Enable filter */
 398         ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
 399                                  DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
 400         if (ret < 0)
 401                 return ret;
 402
 403         /* Nothing more to do for injected (scan mode/triggered) conversions */
 404         if (adc->nconv > 1 || trig)
 405                 return 0;
 406
 407         /* Software start (single or continuous) regular conversion */
 408         return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
 409                                   DFSDM_CR1_RSWSTART_MASK,
 410                                   DFSDM_CR1_RSWSTART(1));
 411 }
 412
 413 static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm,
 414                                     unsigned int fl_id)
 415 {
 416         /* Disable conversion */
 417         regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
 418                            DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
 419 }
 420
 421 static int stm32_dfsdm_filter_set_trig(struct stm32_dfsdm_adc *adc,
 422                                        unsigned int fl_id,
 423                                        struct iio_trigger *trig)
 424 {
 425         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 426         struct regmap *regmap = adc->dfsdm->regmap;
 427         u32 jextsel = 0, jexten = STM32_DFSDM_JEXTEN_DISABLED;
 428         int ret;
 429
 430         if (trig) {
 431                 ret = stm32_dfsdm_get_jextsel(indio_dev, trig);
 432                 if (ret < 0)
 433                         return ret;
 434
 435                 /* set trigger source and polarity (default to rising edge) */
 436                 jextsel = ret;
 437                 jexten = STM32_DFSDM_JEXTEN_RISING_EDGE;
 438         }
 439
 440         ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
 441                                  DFSDM_CR1_JEXTSEL_MASK | DFSDM_CR1_JEXTEN_MASK,
 442                                  DFSDM_CR1_JEXTSEL(jextsel) |
 443                                  DFSDM_CR1_JEXTEN(jexten));
 444         if (ret < 0)
 445                 return ret;
 446
 447         return 0;
 448 }
 449
 450 static int stm32_dfsdm_channels_configure(struct stm32_dfsdm_adc *adc,
 451                                           unsigned int fl_id,
 452                                           struct iio_trigger *trig)
 453 {
 454         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 455         struct regmap *regmap = adc->dfsdm->regmap;
 456         struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
 457         struct stm32_dfsdm_filter_osr *flo = &fl->flo[0];
 458         const struct iio_chan_spec *chan;
 459         unsigned int bit;
 460         int ret;
 461
 462         fl->fast = 0;
 463
 464         /*
 465          * In continuous mode, use fast mode configuration,
 466          * if it provides a better resolution.
 467          */
 468         if (adc->nconv == 1 && !trig &&
 469             (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)) {
 470                 if (fl->flo[1].res >= fl->flo[0].res) {
 471                         fl->fast = 1;
 472                         flo = &fl->flo[1];
 473                 }
 474         }
 475
 476         if (!flo->res)
 477                 return -EINVAL;
 478
 479         for_each_set_bit(bit, &adc->smask,
 480                          sizeof(adc->smask) * BITS_PER_BYTE) {
 481                 chan = indio_dev->channels + bit;
 482
 483                 ret = regmap_update_bits(regmap,
 484                                          DFSDM_CHCFGR2(chan->channel),
 485                                          DFSDM_CHCFGR2_DTRBS_MASK,
 486                                          DFSDM_CHCFGR2_DTRBS(flo->rshift));
 487                 if (ret)
 488                         return ret;
 489         }
 490
 491         return 0;
 492 }
 493
 494 static int stm32_dfsdm_filter_configure(struct stm32_dfsdm_adc *adc,
 495                                         unsigned int fl_id,
 496                                         struct iio_trigger *trig)
 497 {
 498         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 499         struct regmap *regmap = adc->dfsdm->regmap;
 500         struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
 501         struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
 502         u32 cr1;
 503         const struct iio_chan_spec *chan;
 504         unsigned int bit, jchg = 0;
 505         int ret;
 506
 507         /* Average integrator oversampling */
 508         ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
 509                                  DFSDM_FCR_IOSR(flo->iosr - 1));
 510         if (ret)
 511                 return ret;
 512
 513         /* Filter order and Oversampling */
 514         ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
 515                                  DFSDM_FCR_FOSR(flo->fosr - 1));
 516         if (ret)
 517                 return ret;
 518
 519         ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
 520                                  DFSDM_FCR_FORD(fl->ford));
 521         if (ret)
 522                 return ret;
 523
 524         ret = stm32_dfsdm_filter_set_trig(adc, fl_id, trig);
 525         if (ret)
 526                 return ret;
 527
 528         ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
 529                                  DFSDM_CR1_FAST_MASK,
 530                                  DFSDM_CR1_FAST(fl->fast));
 531         if (ret)
 532                 return ret;
 533
 534         /*
 535          * DFSDM modes configuration W.R.T audio/iio type modes
 536          * ----------------------------------------------------------------
 537          * Modes         | regular |  regular     | injected | injected   |
 538          *               |         |  continuous  |          | + scan     |
 539          * --------------|---------|--------------|----------|------------|
 540          * single conv   |    x    |              |          |            |
 541          * (1 chan)      |         |              |          |            |
 542          * --------------|---------|--------------|----------|------------|
 543          * 1 Audio chan  |         | sample freq  |          |            |
 544          *               |         | or sync_mode |          |            |
 545          * --------------|---------|--------------|----------|------------|
 546          * 1 IIO chan    |         | sample freq  | trigger  |            |
 547          *               |         | or sync_mode |          |            |
 548          * --------------|---------|--------------|----------|------------|
 549          * 2+ IIO chans  |         |              |          | trigger or |
 550          *               |         |              |          | sync_mode  |
 551          * ----------------------------------------------------------------
 552          */
 553         if (adc->nconv == 1 && !trig) {
 554                 bit = __ffs(adc->smask);
 555                 chan = indio_dev->channels + bit;
 556
 557                 /* Use regular conversion for single channel without trigger */
 558                 cr1 = DFSDM_CR1_RCH(chan->channel);
 559
 560                 /* Continuous conversions triggered by SPI clk in buffer mode */
 561                 if (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)
 562                         cr1 |= DFSDM_CR1_RCONT(1);
 563
 564                 cr1 |= DFSDM_CR1_RSYNC(fl->sync_mode);
 565         } else {
 566                 /* Use injected conversion for multiple channels */
 567                 for_each_set_bit(bit, &adc->smask,
 568                                  sizeof(adc->smask) * BITS_PER_BYTE) {
 569                         chan = indio_dev->channels + bit;
 570                         jchg |= BIT(chan->channel);
 571                 }
 572                 ret = regmap_write(regmap, DFSDM_JCHGR(fl_id), jchg);
 573                 if (ret < 0)
 574                         return ret;
 575
 576                 /* Use scan mode for multiple channels */
 577                 cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0);
 578
 579                 /*
 580                  * Continuous conversions not supported in injected mode,
 581                  * either use:
 582                  * - conversions in sync with filter 0
 583                  * - triggered conversions
 584                  */
 585                 if (!fl->sync_mode && !trig)
 586                         return -EINVAL;
 587                 cr1 |= DFSDM_CR1_JSYNC(fl->sync_mode);
 588         }
 589
 590         return regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_CFG_MASK,
 591                                   cr1);
 592 }
 593
 594 static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
 595                                         struct iio_dev *indio_dev,
 596                                         struct iio_chan_spec *ch)
 597 {
 598         struct stm32_dfsdm_channel *df_ch;
 599         const char *of_str;
 600         int chan_idx = ch->scan_index;
 601         int ret, val;
 602
 603         ret = of_property_read_u32_index(indio_dev->dev.of_node,
 604                                          "st,adc-channels", chan_idx,
 605                                          &ch->channel);
 606         if (ret < 0) {
 607                 dev_err(&indio_dev->dev,
 608                         " Error parsing 'st,adc-channels' for idx %d\n",
 609                         chan_idx);
 610                 return ret;
 611         }
 612         if (ch->channel >= dfsdm->num_chs) {
 613                 dev_err(&indio_dev->dev,
 614                         " Error bad channel number %d (max = %d)\n",
 615                         ch->channel, dfsdm->num_chs);
 616                 return -EINVAL;
 617         }
 618
 619         ret = of_property_read_string_index(indio_dev->dev.of_node,
 620                                             "st,adc-channel-names", chan_idx,
 621                                             &ch->datasheet_name);
 622         if (ret < 0) {
 623                 dev_err(&indio_dev->dev,
 624                         " Error parsing 'st,adc-channel-names' for idx %d\n",
 625                         chan_idx);
 626                 return ret;
 627         }
 628
 629         df_ch =  &dfsdm->ch_list[ch->channel];
 630         df_ch->id = ch->channel;
 631
 632         ret = of_property_read_string_index(indio_dev->dev.of_node,
 633                                             "st,adc-channel-types", chan_idx,
 634                                             &of_str);
 635         if (!ret) {
 636                 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
 637                 if (val < 0)
 638                         return val;
 639         } else {
 640                 val = 0;
 641         }
 642         df_ch->type = val;
 643
 644         ret = of_property_read_string_index(indio_dev->dev.of_node,
 645                                             "st,adc-channel-clk-src", chan_idx,
 646                                             &of_str);
 647         if (!ret) {
 648                 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
 649                 if (val < 0)
 650                         return val;
 651         } else {
 652                 val = 0;
 653         }
 654         df_ch->src = val;
 655
 656         ret = of_property_read_u32_index(indio_dev->dev.of_node,
 657                                          "st,adc-alt-channel", chan_idx,
 658                                          &df_ch->alt_si);
 659         if (ret < 0)
 660                 df_ch->alt_si = 0;
 661
 662         return 0;
 663 }
 664
 665 static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
 666                                           uintptr_t priv,
 667                                           const struct iio_chan_spec *chan,
 668                                           char *buf)
 669 {
 670         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 671
 672         return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
 673 }
 674
 675 static int dfsdm_adc_set_samp_freq(struct iio_dev *indio_dev,
 676                                    unsigned int sample_freq,
 677                                    unsigned int spi_freq)
 678 {
 679         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 680         unsigned int oversamp;
 681         int ret;
 682
 683         oversamp = DIV_ROUND_CLOSEST(spi_freq, sample_freq);
 684         if (spi_freq % sample_freq)
 685                 dev_dbg(&indio_dev->dev,
 686                         "Rate not accurate. requested (%u), actual (%u)\n",
 687                         sample_freq, spi_freq / oversamp);
 688
 689         ret = stm32_dfsdm_compute_all_osrs(indio_dev, oversamp);
 690         if (ret < 0)
 691                 return ret;
 692
 693         adc->sample_freq = spi_freq / oversamp;
 694         adc->oversamp = oversamp;
 695
 696         return 0;
 697 }
 698
 699 static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
 700                                           uintptr_t priv,
 701                                           const struct iio_chan_spec *chan,
 702                                           const char *buf, size_t len)
 703 {
 704         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 705         struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
 706         unsigned int sample_freq = adc->sample_freq;
 707         unsigned int spi_freq;
 708         int ret;
 709
 710         dev_err(&indio_dev->dev, "enter %s\n", __func__);
 711         /* If DFSDM is master on SPI, SPI freq can not be updated */
 712         if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
 713                 return -EPERM;
 714
 715         ret = kstrtoint(buf, 0, &spi_freq);
 716         if (ret)
 717                 return ret;
 718
 719         if (!spi_freq)
 720                 return -EINVAL;
 721
 722         if (sample_freq) {
 723                 ret = dfsdm_adc_set_samp_freq(indio_dev, sample_freq, spi_freq);
 724                 if (ret < 0)
 725                         return ret;
 726         }
 727         adc->spi_freq = spi_freq;
 728
 729         return len;
 730 }
 731
 732 static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc,
 733                                   struct iio_trigger *trig)
 734 {
 735         struct regmap *regmap = adc->dfsdm->regmap;
 736         int ret;
 737
 738         ret = stm32_dfsdm_channels_configure(adc, adc->fl_id, trig);
 739         if (ret < 0)
 740                 return ret;
 741
 742         ret = stm32_dfsdm_start_channel(adc);
 743         if (ret < 0)
 744                 return ret;
 745
 746         ret = stm32_dfsdm_filter_configure(adc, adc->fl_id, trig);
 747         if (ret < 0)
 748                 goto stop_channels;
 749
 750         ret = stm32_dfsdm_start_filter(adc, adc->fl_id, trig);
 751         if (ret < 0)
 752                 goto filter_unconfigure;
 753
 754         return 0;
 755
 756 filter_unconfigure:
 757         regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
 758                            DFSDM_CR1_CFG_MASK, 0);
 759 stop_channels:
 760         stm32_dfsdm_stop_channel(adc);
 761
 762         return ret;
 763 }
 764
 765 static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc)
 766 {
 767         struct regmap *regmap = adc->dfsdm->regmap;
 768
 769         stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
 770
 771         regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
 772                            DFSDM_CR1_CFG_MASK, 0);
 773
 774         stm32_dfsdm_stop_channel(adc);
 775 }
 776
 777 static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
 778                                      unsigned int val)
 779 {
 780         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 781         unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
 782         unsigned int rx_buf_sz = DFSDM_DMA_BUFFER_SIZE;
 783
 784         /*
 785          * DMA cyclic transfers are used, buffer is split into two periods.
 786          * There should be :
 787          * - always one buffer (period) DMA is working on
 788          * - one buffer (period) driver pushed to ASoC side.
 789          */
 790         watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
 791         adc->buf_sz = min(rx_buf_sz, watermark * 2 * adc->nconv);
 792
 793         return 0;
 794 }
 795
 796 static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
 797 {
 798         struct dma_tx_state state;
 799         enum dma_status status;
 800
 801         status = dmaengine_tx_status(adc->dma_chan,
 802                                      adc->dma_chan->cookie,
 803                                      &state);
 804         if (status == DMA_IN_PROGRESS) {
 805                 /* Residue is size in bytes from end of buffer */
 806                 unsigned int i = adc->buf_sz - state.residue;
 807                 unsigned int size;
 808
 809                 /* Return available bytes */
 810                 if (i >= adc->bufi)
 811                         size = i - adc->bufi;
 812                 else
 813                         size = adc->buf_sz + i - adc->bufi;
 814
 815                 return size;
 816         }
 817
 818         return 0;
 819 }
 820
 821 static inline void stm32_dfsdm_process_data(struct stm32_dfsdm_adc *adc,
 822                                             s32 *buffer)
 823 {
 824         struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
 825         struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
 826         unsigned int i = adc->nconv;
 827         s32 *ptr = buffer;
 828
 829         while (i--) {
 830                 /* Mask 8 LSB that contains the channel ID */
 831                 *ptr &= 0xFFFFFF00;
 832                 /* Convert 2^(n-1) sample to 2^(n-1)-1 to avoid wrap-around */
 833                 if (*ptr > flo->max)
 834                         *ptr -= 1;
 835                 /*
 836                  * Samples from filter are retrieved with 23 bits resolution
 837                  * or less. Shift left to align MSB on 24 bits.
 838                  */
 839                 *ptr <<= flo->lshift;
 840
 841                 ptr++;
 842         }
 843 }
 844
 845 static irqreturn_t stm32_dfsdm_adc_trigger_handler(int irq, void *p)
 846 {
 847         struct iio_poll_func *pf = p;
 848         struct iio_dev *indio_dev = pf->indio_dev;
 849         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 850         int available = stm32_dfsdm_adc_dma_residue(adc);
 851
 852         while (available >= indio_dev->scan_bytes) {
 853                 s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi];
 854
 855                 stm32_dfsdm_process_data(adc, buffer);
 856
 857                 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
 858                                                    pf->timestamp);
 859                 available -= indio_dev->scan_bytes;
 860                 adc->bufi += indio_dev->scan_bytes;
 861                 if (adc->bufi >= adc->buf_sz)
 862                         adc->bufi = 0;
 863         }
 864
 865         iio_trigger_notify_done(indio_dev->trig);
 866
 867         return IRQ_HANDLED;
 868 }
 869
 870 static void stm32_dfsdm_dma_buffer_done(void *data)
 871 {
 872         struct iio_dev *indio_dev = data;
 873         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 874         int available = stm32_dfsdm_adc_dma_residue(adc);
 875         size_t old_pos;
 876
 877         if (indio_dev->currentmode & INDIO_BUFFER_TRIGGERED) {
 878                 iio_trigger_poll_chained(indio_dev->trig);
 879                 return;
 880         }
 881
 882         /*
 883          * FIXME: In Kernel interface does not support cyclic DMA buffer,and
 884          * offers only an interface to push data samples per samples.
 885          * For this reason IIO buffer interface is not used and interface is
 886          * bypassed using a private callback registered by ASoC.
 887          * This should be a temporary solution waiting a cyclic DMA engine
 888          * support in IIO.
 889          */
 890
 891         dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__,
 892                 adc->bufi, available);
 893         old_pos = adc->bufi;
 894
 895         while (available >= indio_dev->scan_bytes) {
 896                 s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi];
 897
 898                 stm32_dfsdm_process_data(adc, buffer);
 899
 900                 available -= indio_dev->scan_bytes;
 901                 adc->bufi += indio_dev->scan_bytes;
 902                 if (adc->bufi >= adc->buf_sz) {
 903                         if (adc->cb)
 904                                 adc->cb(&adc->rx_buf[old_pos],
 905                                          adc->buf_sz - old_pos, adc->cb_priv);
 906                         adc->bufi = 0;
 907                         old_pos = 0;
 908                 }
 909                 /* regular iio buffer without trigger */
 910                 if (adc->dev_data->type == DFSDM_IIO)
 911                         iio_push_to_buffers(indio_dev, buffer);
 912         }
 913         if (adc->cb)
 914                 adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
 915                         adc->cb_priv);
 916 }
 917
 918 static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
 919 {
 920         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 921         /*
 922          * The DFSDM supports half-word transfers. However, for 16 bits record,
 923          * 4 bytes buswidth is kept, to avoid losing samples LSBs when left
 924          * shift is required.
 925          */
 926         struct dma_slave_config config = {
 927                 .src_addr = (dma_addr_t)adc->dfsdm->phys_base,
 928                 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
 929         };
 930         struct dma_async_tx_descriptor *desc;
 931         dma_cookie_t cookie;
 932         int ret;
 933
 934         if (!adc->dma_chan)
 935                 return -EINVAL;
 936
 937         dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
 938                 adc->buf_sz, adc->buf_sz / 2);
 939
 940         if (adc->nconv == 1 && !indio_dev->trig)
 941                 config.src_addr += DFSDM_RDATAR(adc->fl_id);
 942         else
 943                 config.src_addr += DFSDM_JDATAR(adc->fl_id);
 944         ret = dmaengine_slave_config(adc->dma_chan, &config);
 945         if (ret)
 946                 return ret;
 947
 948         /* Prepare a DMA cyclic transaction */
 949         desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
 950                                          adc->dma_buf,
 951                                          adc->buf_sz, adc->buf_sz / 2,
 952                                          DMA_DEV_TO_MEM,
 953                                          DMA_PREP_INTERRUPT);
 954         if (!desc)
 955                 return -EBUSY;
 956
 957         desc->callback = stm32_dfsdm_dma_buffer_done;
 958         desc->callback_param = indio_dev;
 959
 960         cookie = dmaengine_submit(desc);
 961         ret = dma_submit_error(cookie);
 962         if (ret)
 963                 goto err_stop_dma;
 964
 965         /* Issue pending DMA requests */
 966         dma_async_issue_pending(adc->dma_chan);
 967
 968         if (adc->nconv == 1 && !indio_dev->trig) {
 969                 /* Enable regular DMA transfer*/
 970                 ret = regmap_update_bits(adc->dfsdm->regmap,
 971                                          DFSDM_CR1(adc->fl_id),
 972                                          DFSDM_CR1_RDMAEN_MASK,
 973                                          DFSDM_CR1_RDMAEN_MASK);
 974         } else {
 975                 /* Enable injected DMA transfer*/
 976                 ret = regmap_update_bits(adc->dfsdm->regmap,
 977                                          DFSDM_CR1(adc->fl_id),
 978                                          DFSDM_CR1_JDMAEN_MASK,
 979                                          DFSDM_CR1_JDMAEN_MASK);
 980         }
 981
 982         if (ret < 0)
 983                 goto err_stop_dma;
 984
 985         return 0;
 986
 987 err_stop_dma:
 988         dmaengine_terminate_all(adc->dma_chan);
 989
 990         return ret;
 991 }
 992
 993 static void stm32_dfsdm_adc_dma_stop(struct iio_dev *indio_dev)
 994 {
 995         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 996
 997         if (!adc->dma_chan)
 998                 return;
 999
1000         regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR1(adc->fl_id),
1001                            DFSDM_CR1_RDMAEN_MASK | DFSDM_CR1_JDMAEN_MASK, 0);
1002         dmaengine_terminate_all(adc->dma_chan);
1003 }
1004
1005 static int stm32_dfsdm_update_scan_mode(struct iio_dev *indio_dev,
1006                                         const unsigned long *scan_mask)
1007 {
1008         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1009
1010         adc->nconv = bitmap_weight(scan_mask, indio_dev->masklength);
1011         adc->smask = *scan_mask;
1012
1013         dev_dbg(&indio_dev->dev, "nconv=%d mask=%lx\n", adc->nconv, *scan_mask);
1014
1015         return 0;
1016 }
1017
1018 static int __stm32_dfsdm_postenable(struct iio_dev *indio_dev)
1019 {
1020         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1021         int ret;
1022
1023         /* Reset adc buffer index */
1024         adc->bufi = 0;
1025
1026         if (adc->hwc) {
1027                 ret = iio_hw_consumer_enable(adc->hwc);
1028                 if (ret < 0)
1029                         return ret;
1030         }
1031
1032         ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1033         if (ret < 0)
1034                 goto err_stop_hwc;
1035
1036         ret = stm32_dfsdm_adc_dma_start(indio_dev);
1037         if (ret) {
1038                 dev_err(&indio_dev->dev, "Can't start DMA\n");
1039                 goto stop_dfsdm;
1040         }
1041
1042         ret = stm32_dfsdm_start_conv(adc, indio_dev->trig);
1043         if (ret) {
1044                 dev_err(&indio_dev->dev, "Can't start conversion\n");
1045                 goto err_stop_dma;
1046         }
1047
1048         return 0;
1049
1050 err_stop_dma:
1051         stm32_dfsdm_adc_dma_stop(indio_dev);
1052 stop_dfsdm:
1053         stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1054 err_stop_hwc:
1055         if (adc->hwc)
1056                 iio_hw_consumer_disable(adc->hwc);
1057
1058         return ret;
1059 }
1060
1061 static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
1062 {
1063         int ret;
1064
1065         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
1066                 ret = iio_triggered_buffer_postenable(indio_dev);
1067                 if (ret < 0)
1068                         return ret;
1069         }
1070
1071         ret = __stm32_dfsdm_postenable(indio_dev);
1072         if (ret < 0)
1073                 goto err_predisable;
1074
1075         return 0;
1076
1077 err_predisable:
1078         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1079                 iio_triggered_buffer_predisable(indio_dev);
1080
1081         return ret;
1082 }
1083
1084 static void __stm32_dfsdm_predisable(struct iio_dev *indio_dev)
1085 {
1086         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1087
1088         stm32_dfsdm_stop_conv(adc);
1089
1090         stm32_dfsdm_adc_dma_stop(indio_dev);
1091
1092         stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1093
1094         if (adc->hwc)
1095                 iio_hw_consumer_disable(adc->hwc);
1096 }
1097
1098 static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
1099 {
1100         __stm32_dfsdm_predisable(indio_dev);
1101
1102         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1103                 iio_triggered_buffer_predisable(indio_dev);
1104
1105         return 0;
1106 }
1107
1108 static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
1109         .postenable = &stm32_dfsdm_postenable,
1110         .predisable = &stm32_dfsdm_predisable,
1111 };
1112
1113 /**
1114  * stm32_dfsdm_get_buff_cb() - register a callback that will be called when
1115  *                             DMA transfer period is achieved.
1116  *
1117  * @iio_dev: Handle to IIO device.
1118  * @cb: Pointer to callback function:
1119  *      - data: pointer to data buffer
1120  *      - size: size in byte of the data buffer
1121  *      - private: pointer to consumer private structure.
1122  * @private: Pointer to consumer private structure.
1123  */
1124 int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
1125                             int (*cb)(const void *data, size_t size,
1126                                       void *private),
1127                             void *private)
1128 {
1129         struct stm32_dfsdm_adc *adc;
1130
1131         if (!iio_dev)
1132                 return -EINVAL;
1133         adc = iio_priv(iio_dev);
1134
1135         adc->cb = cb;
1136         adc->cb_priv = private;
1137
1138         return 0;
1139 }
1140 EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
1141
1142 /**
1143  * stm32_dfsdm_release_buff_cb - unregister buffer callback
1144  *
1145  * @iio_dev: Handle to IIO device.
1146  */
1147 int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
1148 {
1149         struct stm32_dfsdm_adc *adc;
1150
1151         if (!iio_dev)
1152                 return -EINVAL;
1153         adc = iio_priv(iio_dev);
1154
1155         adc->cb = NULL;
1156         adc->cb_priv = NULL;
1157
1158         return 0;
1159 }
1160 EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
1161
1162 static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
1163                                    const struct iio_chan_spec *chan, int *res)
1164 {
1165         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1166         long timeout;
1167         int ret;
1168
1169         reinit_completion(&adc->completion);
1170
1171         adc->buffer = res;
1172
1173         ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1174         if (ret < 0)
1175                 return ret;
1176
1177         ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1178                                  DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
1179         if (ret < 0)
1180                 goto stop_dfsdm;
1181
1182         adc->nconv = 1;
1183         adc->smask = BIT(chan->scan_index);
1184         ret = stm32_dfsdm_start_conv(adc, NULL);
1185         if (ret < 0) {
1186                 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1187                                    DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1188                 goto stop_dfsdm;
1189         }
1190
1191         timeout = wait_for_completion_interruptible_timeout(&adc->completion,
1192                                                             DFSDM_TIMEOUT);
1193
1194         /* Mask IRQ for regular conversion achievement*/
1195         regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1196                            DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1197
1198         if (timeout == 0)
1199                 ret = -ETIMEDOUT;
1200         else if (timeout < 0)
1201                 ret = timeout;
1202         else
1203                 ret = IIO_VAL_INT;
1204
1205         stm32_dfsdm_stop_conv(adc);
1206
1207 stop_dfsdm:
1208         stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1209
1210         return ret;
1211 }
1212
1213 static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
1214                                  struct iio_chan_spec const *chan,
1215                                  int val, int val2, long mask)
1216 {
1217         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1218         struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
1219         unsigned int spi_freq;
1220         int ret = -EINVAL;
1221
1222         switch (mask) {
1223         case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1224                 ret = iio_device_claim_direct_mode(indio_dev);
1225                 if (ret)
1226                         return ret;
1227                 ret = stm32_dfsdm_compute_all_osrs(indio_dev, val);
1228                 if (!ret)
1229                         adc->oversamp = val;
1230                 iio_device_release_direct_mode(indio_dev);
1231                 return ret;
1232
1233         case IIO_CHAN_INFO_SAMP_FREQ:
1234                 if (!val)
1235                         return -EINVAL;
1236
1237                 ret = iio_device_claim_direct_mode(indio_dev);
1238                 if (ret)
1239                         return ret;
1240
1241                 switch (ch->src) {
1242                 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL:
1243                         spi_freq = adc->dfsdm->spi_master_freq;
1244                         break;
1245                 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING:
1246                 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING:
1247                         spi_freq = adc->dfsdm->spi_master_freq / 2;
1248                         break;
1249                 default:
1250                         spi_freq = adc->spi_freq;
1251                 }
1252
1253                 ret = dfsdm_adc_set_samp_freq(indio_dev, val, spi_freq);
1254                 iio_device_release_direct_mode(indio_dev);
1255                 return ret;
1256         }
1257
1258         return -EINVAL;
1259 }
1260
1261 static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
1262                                 struct iio_chan_spec const *chan, int *val,
1263                                 int *val2, long mask)
1264 {
1265         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1266         int ret;
1267
1268         switch (mask) {
1269         case IIO_CHAN_INFO_RAW:
1270                 ret = iio_device_claim_direct_mode(indio_dev);
1271                 if (ret)
1272                         return ret;
1273                 ret = iio_hw_consumer_enable(adc->hwc);
1274                 if (ret < 0) {
1275                         dev_err(&indio_dev->dev,
1276                                 "%s: IIO enable failed (channel %d)\n",
1277                                 __func__, chan->channel);
1278                         iio_device_release_direct_mode(indio_dev);
1279                         return ret;
1280                 }
1281                 ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
1282                 iio_hw_consumer_disable(adc->hwc);
1283                 if (ret < 0) {
1284                         dev_err(&indio_dev->dev,
1285                                 "%s: Conversion failed (channel %d)\n",
1286                                 __func__, chan->channel);
1287                         iio_device_release_direct_mode(indio_dev);
1288                         return ret;
1289                 }
1290                 iio_device_release_direct_mode(indio_dev);
1291                 return IIO_VAL_INT;
1292
1293         case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1294                 *val = adc->oversamp;
1295
1296                 return IIO_VAL_INT;
1297
1298         case IIO_CHAN_INFO_SAMP_FREQ:
1299                 *val = adc->sample_freq;
1300
1301                 return IIO_VAL_INT;
1302         }
1303
1304         return -EINVAL;
1305 }
1306
1307 static int stm32_dfsdm_validate_trigger(struct iio_dev *indio_dev,
1308                                         struct iio_trigger *trig)
1309 {
1310         return stm32_dfsdm_get_jextsel(indio_dev, trig) < 0 ? -EINVAL : 0;
1311 }
1312
1313 static const struct iio_info stm32_dfsdm_info_audio = {
1314         .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1315         .read_raw = stm32_dfsdm_read_raw,
1316         .write_raw = stm32_dfsdm_write_raw,
1317         .update_scan_mode = stm32_dfsdm_update_scan_mode,
1318 };
1319
1320 static const struct iio_info stm32_dfsdm_info_adc = {
1321         .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1322         .read_raw = stm32_dfsdm_read_raw,
1323         .write_raw = stm32_dfsdm_write_raw,
1324         .update_scan_mode = stm32_dfsdm_update_scan_mode,
1325         .validate_trigger = stm32_dfsdm_validate_trigger,
1326 };
1327
1328 static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
1329 {
1330         struct stm32_dfsdm_adc *adc = arg;
1331         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1332         struct regmap *regmap = adc->dfsdm->regmap;
1333         unsigned int status, int_en;
1334
1335         regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
1336         regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
1337
1338         if (status & DFSDM_ISR_REOCF_MASK) {
1339                 /* Read the data register clean the IRQ status */
1340                 regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
1341                 complete(&adc->completion);
1342         }
1343
1344         if (status & DFSDM_ISR_ROVRF_MASK) {
1345                 if (int_en & DFSDM_CR2_ROVRIE_MASK)
1346                         dev_warn(&indio_dev->dev, "Overrun detected\n");
1347                 regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id),
1348                                    DFSDM_ICR_CLRROVRF_MASK,
1349                                    DFSDM_ICR_CLRROVRF_MASK);
1350         }
1351
1352         return IRQ_HANDLED;
1353 }
1354
1355 /*
1356  * Define external info for SPI Frequency and audio sampling rate that can be
1357  * configured by ASoC driver through consumer.h API
1358  */
1359 static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
1360         /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */
1361         {
1362                 .name = "spi_clk_freq",
1363                 .shared = IIO_SHARED_BY_TYPE,
1364                 .read = dfsdm_adc_audio_get_spiclk,
1365                 .write = dfsdm_adc_audio_set_spiclk,
1366         },
1367         {},
1368 };
1369
1370 static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev)
1371 {
1372         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1373
1374         if (adc->dma_chan) {
1375                 dma_free_coherent(adc->dma_chan->device->dev,
1376                                   DFSDM_DMA_BUFFER_SIZE,
1377                                   adc->rx_buf, adc->dma_buf);
1378                 dma_release_channel(adc->dma_chan);
1379         }
1380 }
1381
1382 static int stm32_dfsdm_dma_request(struct iio_dev *indio_dev)
1383 {
1384         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1385
1386         adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx");
1387         if (!adc->dma_chan)
1388                 return -EINVAL;
1389
1390         adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1391                                          DFSDM_DMA_BUFFER_SIZE,
1392                                          &adc->dma_buf, GFP_KERNEL);
1393         if (!adc->rx_buf) {
1394                 dma_release_channel(adc->dma_chan);
1395                 return -ENOMEM;
1396         }
1397
1398         indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1399         indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops;
1400
1401         return 0;
1402 }
1403
1404 static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
1405                                          struct iio_chan_spec *ch)
1406 {
1407         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1408         int ret;
1409
1410         ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
1411         if (ret < 0)
1412                 return ret;
1413
1414         ch->type = IIO_VOLTAGE;
1415         ch->indexed = 1;
1416
1417         /*
1418          * IIO_CHAN_INFO_RAW: used to compute regular conversion
1419          * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling
1420          */
1421         ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
1422         ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) |
1423                                         BIT(IIO_CHAN_INFO_SAMP_FREQ);
1424
1425         if (adc->dev_data->type == DFSDM_AUDIO) {
1426                 ch->ext_info = dfsdm_adc_audio_ext_info;
1427         } else {
1428                 ch->scan_type.shift = 8;
1429         }
1430         ch->scan_type.sign = 's';
1431         ch->scan_type.realbits = 24;
1432         ch->scan_type.storagebits = 32;
1433
1434         return stm32_dfsdm_chan_configure(adc->dfsdm,
1435                                           &adc->dfsdm->ch_list[ch->channel]);
1436 }
1437
1438 static int stm32_dfsdm_audio_init(struct iio_dev *indio_dev)
1439 {
1440         struct iio_chan_spec *ch;
1441         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1442         struct stm32_dfsdm_channel *d_ch;
1443         int ret;
1444
1445         ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
1446         if (!ch)
1447                 return -ENOMEM;
1448
1449         ch->scan_index = 0;
1450
1451         ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
1452         if (ret < 0) {
1453                 dev_err(&indio_dev->dev, "Channels init failed\n");
1454                 return ret;
1455         }
1456         ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
1457
1458         d_ch = &adc->dfsdm->ch_list[ch->channel];
1459         if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
1460                 adc->spi_freq = adc->dfsdm->spi_master_freq;
1461
1462         indio_dev->num_channels = 1;
1463         indio_dev->channels = ch;
1464
1465         return stm32_dfsdm_dma_request(indio_dev);
1466 }
1467
1468 static int stm32_dfsdm_adc_init(struct iio_dev *indio_dev)
1469 {
1470         struct iio_chan_spec *ch;
1471         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1472         int num_ch;
1473         int ret, chan_idx;
1474
1475         adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
1476         ret = stm32_dfsdm_compute_all_osrs(indio_dev, adc->oversamp);
1477         if (ret < 0)
1478                 return ret;
1479
1480         num_ch = of_property_count_u32_elems(indio_dev->dev.of_node,
1481                                              "st,adc-channels");
1482         if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) {
1483                 dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
1484                 return num_ch < 0 ? num_ch : -EINVAL;
1485         }
1486
1487         /* Bind to SD modulator IIO device */
1488         adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
1489         if (IS_ERR(adc->hwc))
1490                 return -EPROBE_DEFER;
1491
1492         ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch),
1493                           GFP_KERNEL);
1494         if (!ch)
1495                 return -ENOMEM;
1496
1497         for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
1498                 ch[chan_idx].scan_index = chan_idx;
1499                 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &ch[chan_idx]);
1500                 if (ret < 0) {
1501                         dev_err(&indio_dev->dev, "Channels init failed\n");
1502                         return ret;
1503                 }
1504         }
1505
1506         indio_dev->num_channels = num_ch;
1507         indio_dev->channels = ch;
1508
1509         init_completion(&adc->completion);
1510
1511         /* Optionally request DMA */
1512         if (stm32_dfsdm_dma_request(indio_dev)) {
1513                 dev_dbg(&indio_dev->dev, "No DMA support\n");
1514                 return 0;
1515         }
1516
1517         ret = iio_triggered_buffer_setup(indio_dev,
1518                                          &iio_pollfunc_store_time,
1519                                          &stm32_dfsdm_adc_trigger_handler,
1520                                          &stm32_dfsdm_buffer_setup_ops);
1521         if (ret) {
1522                 stm32_dfsdm_dma_release(indio_dev);
1523                 dev_err(&indio_dev->dev, "buffer setup failed\n");
1524                 return ret;
1525         }
1526
1527         /* lptimer/timer hardware triggers */
1528         indio_dev->modes |= INDIO_HARDWARE_TRIGGERED;
1529
1530         return 0;
1531 }
1532
1533 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
1534         .type = DFSDM_IIO,
1535         .init = stm32_dfsdm_adc_init,
1536 };
1537
1538 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
1539         .type = DFSDM_AUDIO,
1540         .init = stm32_dfsdm_audio_init,
1541 };
1542
1543 static const struct of_device_id stm32_dfsdm_adc_match[] = {
1544         {
1545                 .compatible = "st,stm32-dfsdm-adc",
1546                 .data = &stm32h7_dfsdm_adc_data,
1547         },
1548         {
1549                 .compatible = "st,stm32-dfsdm-dmic",
1550                 .data = &stm32h7_dfsdm_audio_data,
1551         },
1552         {}
1553 };
1554
1555 static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
1556 {
1557         struct device *dev = &pdev->dev;
1558         struct stm32_dfsdm_adc *adc;
1559         struct device_node *np = dev->of_node;
1560         const struct stm32_dfsdm_dev_data *dev_data;
1561         struct iio_dev *iio;
1562         char *name;
1563         int ret, irq, val;
1564
1565         dev_data = of_device_get_match_data(dev);
1566         iio = devm_iio_device_alloc(dev, sizeof(*adc));
1567         if (!iio) {
1568                 dev_err(dev, "%s: Failed to allocate IIO\n", __func__);
1569                 return -ENOMEM;
1570         }
1571
1572         adc = iio_priv(iio);
1573         adc->dfsdm = dev_get_drvdata(dev->parent);
1574
1575         iio->dev.parent = dev;
1576         iio->dev.of_node = np;
1577         iio->modes = INDIO_DIRECT_MODE;
1578
1579         platform_set_drvdata(pdev, adc);
1580
1581         ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
1582         if (ret != 0 || adc->fl_id >= adc->dfsdm->num_fls) {
1583                 dev_err(dev, "Missing or bad reg property\n");
1584                 return -EINVAL;
1585         }
1586
1587         name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
1588         if (!name)
1589                 return -ENOMEM;
1590         if (dev_data->type == DFSDM_AUDIO) {
1591                 iio->info = &stm32_dfsdm_info_audio;
1592                 snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
1593         } else {
1594                 iio->info = &stm32_dfsdm_info_adc;
1595                 snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
1596         }
1597         iio->name = name;
1598
1599         /*
1600          * In a first step IRQs generated for channels are not treated.
1601          * So IRQ associated to filter instance 0 is dedicated to the Filter 0.
1602          */
1603         irq = platform_get_irq(pdev, 0);
1604         if (irq < 0) {
1605                 if (irq != -EPROBE_DEFER)
1606                         dev_err(dev, "Failed to get IRQ: %d\n", irq);
1607                 return irq;
1608         }
1609
1610         ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
1611                                0, pdev->name, adc);
1612         if (ret < 0) {
1613                 dev_err(dev, "Failed to request IRQ\n");
1614                 return ret;
1615         }
1616
1617         ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
1618         if (ret < 0) {
1619                 dev_err(dev, "Failed to set filter order\n");
1620                 return ret;
1621         }
1622
1623         adc->dfsdm->fl_list[adc->fl_id].ford = val;
1624
1625         ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
1626         if (!ret)
1627                 adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
1628
1629         adc->dev_data = dev_data;
1630         ret = dev_data->init(iio);
1631         if (ret < 0)
1632                 return ret;
1633
1634         ret = iio_device_register(iio);
1635         if (ret < 0)
1636                 goto err_cleanup;
1637
1638         if (dev_data->type == DFSDM_AUDIO) {
1639                 ret = of_platform_populate(np, NULL, NULL, dev);
1640                 if (ret < 0) {
1641                         dev_err(dev, "Failed to find an audio DAI\n");
1642                         goto err_unregister;
1643                 }
1644         }
1645
1646         return 0;
1647
1648 err_unregister:
1649         iio_device_unregister(iio);
1650 err_cleanup:
1651         stm32_dfsdm_dma_release(iio);
1652
1653         return ret;
1654 }
1655
1656 static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
1657 {
1658         struct stm32_dfsdm_adc *adc = platform_get_drvdata(pdev);
1659         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1660
1661         if (adc->dev_data->type == DFSDM_AUDIO)
1662                 of_platform_depopulate(&pdev->dev);
1663         iio_device_unregister(indio_dev);
1664         stm32_dfsdm_dma_release(indio_dev);
1665
1666         return 0;
1667 }
1668
1669 static int __maybe_unused stm32_dfsdm_adc_suspend(struct device *dev)
1670 {
1671         struct stm32_dfsdm_adc *adc = dev_get_drvdata(dev);
1672         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1673
1674         if (iio_buffer_enabled(indio_dev))
1675                 __stm32_dfsdm_predisable(indio_dev);
1676
1677         return 0;
1678 }
1679
1680 static int __maybe_unused stm32_dfsdm_adc_resume(struct device *dev)
1681 {
1682         struct stm32_dfsdm_adc *adc = dev_get_drvdata(dev);
1683         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1684         const struct iio_chan_spec *chan;
1685         struct stm32_dfsdm_channel *ch;
1686         int i, ret;
1687
1688         /* restore channels configuration */
1689         for (i = 0; i < indio_dev->num_channels; i++) {
1690                 chan = indio_dev->channels + i;
1691                 ch = &adc->dfsdm->ch_list[chan->channel];
1692                 ret = stm32_dfsdm_chan_configure(adc->dfsdm, ch);
1693                 if (ret)
1694                         return ret;
1695         }
1696
1697         if (iio_buffer_enabled(indio_dev))
1698                 __stm32_dfsdm_postenable(indio_dev);
1699
1700         return 0;
1701 }
1702
1703 static SIMPLE_DEV_PM_OPS(stm32_dfsdm_adc_pm_ops,
1704                          stm32_dfsdm_adc_suspend, stm32_dfsdm_adc_resume);
1705
1706 static struct platform_driver stm32_dfsdm_adc_driver = {
1707         .driver = {
1708                 .name = "stm32-dfsdm-adc",
1709                 .of_match_table = stm32_dfsdm_adc_match,
1710                 .pm = &stm32_dfsdm_adc_pm_ops,
1711         },
1712         .probe = stm32_dfsdm_adc_probe,
1713         .remove = stm32_dfsdm_adc_remove,
1714 };
1715 module_platform_driver(stm32_dfsdm_adc_driver);
1716
1717 MODULE_DESCRIPTION("STM32 sigma delta ADC");
1718 MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
1719 MODULE_LICENSE("GPL v2");