2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 ********************************************************************
25 * Lots of code copied from:
27 * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
28 * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
29 * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
41 #include <pcmcia/ss.h>
42 #include <pcmcia/i82365.h>
43 #include <pcmcia/yenta.h>
45 #include <pcmcia/cirrus.h>
47 #include <pcmcia/ti113x.h>
50 static struct pci_device_id supported[] = {
52 {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729},
54 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
59 #define CYCLE_TIME 120
62 extern int SPD67290Init (void);
66 static void i82365_dump_regions (pci_dev_t dev);
69 typedef struct socket_info_t {
72 u_char pci_lat, cb_lat, sub_bus, cache;
79 cirrus_state_t c_state;
86 /* These definitions must match the pcic table! */
87 typedef enum pcic_id {
88 IS_PD6710, IS_PD672X, IS_VT83C469
91 typedef struct pcic_t {
95 static pcic_t pcic[] = {
102 static socket_info_t socket;
103 static socket_state_t state;
104 static struct pccard_mem_map mem;
105 static struct pccard_io_map io;
107 /*====================================================================*/
109 /* Some PCI shortcuts */
111 static int pci_readb (socket_info_t * s, int r, u_char * v)
113 return pci_read_config_byte (s->dev, r, v);
115 static int pci_writeb (socket_info_t * s, int r, u_char v)
117 return pci_write_config_byte (s->dev, r, v);
119 static int pci_readw (socket_info_t * s, int r, u_short * v)
121 return pci_read_config_word (s->dev, r, v);
123 static int pci_writew (socket_info_t * s, int r, u_short v)
125 return pci_write_config_word (s->dev, r, v);
128 static int pci_readl (socket_info_t * s, int r, u_int * v)
130 return pci_read_config_dword (s->dev, r, v);
132 static int pci_writel (socket_info_t * s, int r, u_int v)
134 return pci_write_config_dword (s->dev, r, v);
136 #endif /* !CONFIG_CPC45 */
138 /*====================================================================*/
142 #define cb_readb(s) readb((s)->cb_phys + 1)
143 #define cb_writeb(s, v) writeb(v, (s)->cb_phys)
144 #define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1)
145 #define cb_readl(s, r) readl((s)->cb_phys + (r))
146 #define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
149 static u_char i365_get (socket_info_t * s, u_short reg)
153 #ifdef CONFIG_PCMCIA_SLOT_A
159 val = I365_REG (slot, reg);
164 debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val);
168 static void i365_set (socket_info_t * s, u_short reg, u_char data)
170 #ifdef CONFIG_PCMCIA_SLOT_A
176 u_char val = I365_REG (slot, reg);
179 cb_writeb2 (s, data);
181 debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data);
184 #else /* ! CONFIG_CPC45 */
186 #define cb_readb(s, r) readb((s)->cb_phys + (r))
187 #define cb_readl(s, r) readl((s)->cb_phys + (r))
188 #define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r))
189 #define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
191 static u_char i365_get (socket_info_t * s, u_short reg)
193 return cb_readb (s, 0x0800 + reg);
196 static void i365_set (socket_info_t * s, u_short reg, u_char data)
198 cb_writeb (s, 0x0800 + reg, data);
200 #endif /* CONFIG_CPC45 */
202 static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
204 i365_set (s, reg, i365_get (s, reg) | mask);
207 static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
209 i365_set (s, reg, i365_get (s, reg) & ~mask);
213 static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
215 u_char d = i365_get (s, reg);
217 i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
220 static u_short i365_get_pair (socket_info_t * s, u_short reg)
222 return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
224 #endif /* not used */
226 static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
228 i365_set (s, reg, data & 0xff);
229 i365_set (s, reg + 1, data >> 8);
233 /*======================================================================
235 Code to save and restore global state information for Cirrus
236 PD67xx controllers, and to set and report global configuration
239 ======================================================================*/
241 #define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
243 static void cirrus_get_state (socket_info_t * s)
246 cirrus_state_t *p = &s->c_state;
248 p->misc1 = i365_get (s, PD67_MISC_CTL_1);
249 p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
250 p->misc2 = i365_get (s, PD67_MISC_CTL_2);
251 for (i = 0; i < 6; i++)
252 p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i);
256 static void cirrus_set_state (socket_info_t * s)
260 cirrus_state_t *p = &s->c_state;
262 misc = i365_get (s, PD67_MISC_CTL_2);
263 i365_set (s, PD67_MISC_CTL_2, p->misc2);
264 if (misc & PD67_MC2_SUSPEND)
266 misc = i365_get (s, PD67_MISC_CTL_1);
267 misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
268 i365_set (s, PD67_MISC_CTL_1, misc | p->misc1);
269 for (i = 0; i < 6; i++)
270 i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]);
273 static u_int cirrus_set_opts (socket_info_t * s)
275 cirrus_state_t *p = &s->c_state;
281 memset (buf, 0, 200);
286 flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring);
287 flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
289 if (p->misc2 & PD67_MC2_IRQ15_RI)
290 strcat (buf, " [ring]");
291 if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
292 strcat (buf, " [dyn mode]");
293 if (p->misc1 & PD67_MC1_INPACK_ENA)
294 strcat (buf, " [inpack]");
297 if (p->misc2 & PD67_MC2_IRQ15_RI)
301 strcat (buf, " [led]");
307 strcat (buf, " [dma]");
310 flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
312 if (p->misc2 & PD67_MC2_FREQ_BYPASS)
313 strcat (buf, " [freq bypass]");
318 p->timer[0] = p->timer[3] = setup_time;
320 p->timer[1] = cmd_time;
321 p->timer[4] = cmd_time * 2 + 4;
323 if (p->timer[1] == 0) {
326 if (p->timer[0] == 0)
327 p->timer[0] = p->timer[3] = 1;
330 p->timer[2] = p->timer[5] = recov_time;
332 debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n",
334 p->timer[0], p->timer[1], p->timer[2],
335 p->timer[3], p->timer[4], p->timer[5]);
340 #else /* !CONFIG_CPC45 */
342 /*======================================================================
344 Code to save and restore global state information for TI 1130 and
345 TI 1131 controllers, and to set and report global configuration
348 ======================================================================*/
350 static void ti113x_get_state (socket_info_t * s)
352 ti113x_state_t *p = &s->state;
354 pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
355 pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
356 pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
357 pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
358 pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
361 static void ti113x_set_state (socket_info_t * s)
363 ti113x_state_t *p = &s->state;
365 pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
366 pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
367 pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
368 pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
369 pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
370 pci_writel (s, TI12XX_IRQMUX, p->irqmux);
371 i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
372 i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
375 static u_int ti113x_set_opts (socket_info_t * s)
377 ti113x_state_t *p = &s->state;
380 p->cardctl &= ~TI113X_CCR_ZVENABLE;
381 p->cardctl |= TI113X_CCR_SPKROUTEN;
385 #endif /* CONFIG_CPC45 */
387 /*======================================================================
389 Routines to handle common CardBus options
391 ======================================================================*/
393 /* Default settings for PCI command configuration register */
394 #define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
395 PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
397 static void cb_get_state (socket_info_t * s)
399 pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
400 pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
401 pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
402 pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
403 pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
404 pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
407 static void cb_set_state (socket_info_t * s)
410 pci_writel (s, CB_LEGACY_MODE_BASE, 0);
411 pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
413 pci_writew (s, PCI_COMMAND, CMD_DFLT);
414 pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
415 pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
416 pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
417 pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
418 pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
419 pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
422 static void cb_set_opts (socket_info_t * s)
434 /*======================================================================
436 Power control for Cardbus controllers: used both for 16-bit and
439 ======================================================================*/
441 static int cb_set_power (socket_info_t * s, socket_state_t * state)
447 if ((state->Vcc == 0) && (state->Vpp == 0)) {
448 u_char power, vcc, vpp;
450 power = i365_get (s, I365_POWER);
451 state->flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
452 state->flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
453 vcc = power & I365_VCC_MASK;
454 vpp = power & I365_VPP1_MASK;
455 state->Vcc = state->Vpp = 0;
456 if (i365_get (s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) {
457 if (power & I365_VCC_5V)
459 if (vpp == I365_VPP1_5V)
462 if (power & I365_VCC_5V)
464 if (vpp == I365_VPP1_5V)
467 if (power == I365_VPP1_12V)
469 printf ("POWER Vcc:%d Vpp: %d\n", state->Vcc, state->Vpp);
472 reg = I365_PWR_NORESET;
473 if (state->flags & SS_PWR_AUTO)
474 reg |= I365_PWR_AUTO;
475 if (state->flags & SS_OUTPUT_ENA)
477 if (state->Vpp != 0) {
478 if (state->Vpp == 120) {
479 reg |= I365_VPP1_12V;
480 puts (" 12V card found: ");
481 } else if (state->Vpp == state->Vcc) {
483 puts (" 5V card found: ");
485 puts (" power not found: ");
489 if (state->Vcc != 0) {
491 if (state->Vcc == 33) {
492 puts (" 3.3V card found: ");
493 i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
494 } else if (state->Vcc == 50) {
495 puts (" 5V card found: ");
496 i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
498 puts (" power not found: ");
502 if (reg != i365_get (s, I365_POWER))
503 i365_set (s, I365_POWER, reg);
505 #else /* ! CONFIG_CPC45 */
507 /* restart card voltage detection if it seems appropriate */
508 if ((state->Vcc == 0) && (state->Vpp == 0) &&
509 !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
510 cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
511 switch (state->Vcc) {
524 switch (state->Vpp) {
534 reg |= CB_SC_VPP_12V;
539 if (reg != cb_readl (s, CB_SOCKET_CONTROL))
540 cb_writel (s, CB_SOCKET_CONTROL, reg);
541 #endif /* CONFIG_CPC45 */
545 /*======================================================================
547 Generic routines to get and set controller options
549 ======================================================================*/
551 static void get_bridge_state (socket_info_t * s)
554 cirrus_get_state (s);
556 ti113x_get_state (s);
561 static void set_bridge_state (socket_info_t * s)
564 i365_set (s, I365_GBLCTL, 0x00);
565 i365_set (s, I365_GENCTL, 0x00);
567 cirrus_set_state (s);
569 ti113x_set_state (s);
573 static void set_bridge_opts (socket_info_t * s)
583 /*====================================================================*/
585 static int i365_get_status (socket_info_t * s, u_int * value)
591 u_char power, vcc, vpp;
594 status = i365_get (s, I365_IDENT);
595 status = i365_get (s, I365_STATUS);
596 *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
597 if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
598 *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
600 *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
601 *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
603 *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
604 *value |= (status & I365_CS_READY) ? SS_READY : 0;
605 *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
608 /* Check for Cirrus CL-PD67xx chips */
609 i365_set (s, PD67_CHIP_INFO, 0);
610 val = i365_get (s, PD67_CHIP_INFO);
612 if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
613 val = i365_get (s, PD67_CHIP_INFO);
614 if ((val & PD67_INFO_CHIP_ID) == 0) {
616 (val & PD67_INFO_SLOTS) ? IS_PD672X :
618 i365_set (s, PD67_EXT_INDEX, 0xe5);
619 if (i365_get (s, PD67_EXT_INDEX) != 0xe5)
620 s->type = IS_VT83C469;
623 printf ("no Cirrus Chip found\n");
628 i365_bset (s, I365_POWER, I365_VCC_5V);
629 power = i365_get (s, I365_POWER);
630 state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
631 state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
632 vcc = power & I365_VCC_MASK;
633 vpp = power & I365_VPP1_MASK;
634 state.Vcc = state.Vpp = 0;
635 if (i365_get (s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) {
636 if (power & I365_VCC_5V)
638 if (vpp == I365_VPP1_5V)
641 if (power & I365_VCC_5V)
643 if (vpp == I365_VPP1_5V)
646 if (power == I365_VPP1_12V)
649 /* IO card, RESET flags, IO interrupt */
650 power = i365_get (s, I365_INTCTL);
651 state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET;
652 if (power & I365_PC_IOCARD)
653 state.flags |= SS_IOCARD;
654 state.io_irq = power & I365_IRQ_MASK;
656 /* Card status change mask */
657 power = i365_get (s, I365_CSCINT);
658 state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0;
659 if (state.flags & SS_IOCARD)
660 state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0;
662 state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0;
663 state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0;
664 state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0;
666 debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, "
667 "io_irq %d, csc_mask %#2.2x\n", state.flags,
668 state.Vcc, state.Vpp, state.io_irq, state.csc_mask);
670 #else /* !CONFIG_CPC45 */
672 status = cb_readl (s, CB_SOCKET_STATE);
673 *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
674 *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
675 *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
676 *value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING;
677 /* For now, ignore cards with unsupported voltage keys */
678 if (*value & SS_XVCARD)
679 *value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
680 #endif /* CONFIG_CPC45 */
682 } /* i365_get_status */
684 static int i365_set_socket (socket_info_t * s, socket_state_t * state)
688 set_bridge_state (s);
690 /* IO card, RESET flag */
692 reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
693 reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
694 i365_set (s, I365_INTCTL, reg);
697 cb_set_power (s, state);
700 /* Card status change interrupt mask */
701 reg = s->cs_irq << 4;
702 if (state->csc_mask & SS_DETECT)
703 reg |= I365_CSC_DETECT;
704 if (state->flags & SS_IOCARD) {
705 if (state->csc_mask & SS_STSCHG)
706 reg |= I365_CSC_STSCHG;
708 if (state->csc_mask & SS_BATDEAD)
709 reg |= I365_CSC_BVD1;
710 if (state->csc_mask & SS_BATWARN)
711 reg |= I365_CSC_BVD2;
712 if (state->csc_mask & SS_READY)
713 reg |= I365_CSC_READY;
715 i365_set (s, I365_CSCINT, reg);
716 i365_get (s, I365_CSC);
719 #else /* !CONFIG_CPC45 */
721 reg = I365_PWR_NORESET;
722 if (state->flags & SS_PWR_AUTO)
723 reg |= I365_PWR_AUTO;
724 if (state->flags & SS_OUTPUT_ENA)
727 cb_set_power (s, state);
728 reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK);
730 if (reg != i365_get (s, I365_POWER))
731 i365_set (s, I365_POWER, reg);
732 #endif /* CONFIG_CPC45 */
735 } /* i365_set_socket */
737 /*====================================================================*/
739 static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
744 debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
745 mem->map, mem->flags, mem->speed,
746 mem->sys_start, mem->sys_stop, mem->card_start);
750 (mem->card_start > 0x3ffffff) ||
751 (mem->sys_start > mem->sys_stop) ||
752 (mem->speed > 1000)) {
756 /* Turn off the window before changing anything */
757 if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
758 i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
760 /* Take care of high byte, for PCI controllers */
761 i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
763 base = I365_MEM (map);
764 i = (mem->sys_start >> 12) & 0x0fff;
765 if (mem->flags & MAP_16BIT)
767 if (mem->flags & MAP_0WS)
769 i365_set_pair (s, base + I365_W_START, i);
771 i = (mem->sys_stop >> 12) & 0x0fff;
772 switch (mem->speed / CYCLE_TIME) {
782 i |= I365_MEM_WS1 | I365_MEM_WS0;
785 i365_set_pair (s, base + I365_W_STOP, i);
790 i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
792 if (mem->flags & MAP_WRPROT)
793 i |= I365_MEM_WRPROT;
794 if (mem->flags & MAP_ATTRIB)
796 i365_set_pair (s, base + I365_W_OFF, i);
799 /* set System Memory map Upper Adress */
800 i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
801 i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff));
804 /* Turn on the window if necessary */
805 if (mem->flags & MAP_ACTIVE)
806 i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
808 } /* i365_set_mem_map */
810 static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
815 /* comment out: comparison is always false due to limited range of data type */
816 if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
817 (io->stop < io->start))
819 /* Turn off the window before changing anything */
820 if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
821 i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
822 i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
823 i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
824 ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
826 ioctl |= I365_IOCTL_WAIT (map);
827 if (io->flags & MAP_0WS)
828 ioctl |= I365_IOCTL_0WS (map);
829 if (io->flags & MAP_16BIT)
830 ioctl |= I365_IOCTL_16BIT (map);
831 if (io->flags & MAP_AUTOSZ)
832 ioctl |= I365_IOCTL_IOCS16 (map);
833 i365_set (s, I365_IOCTL, ioctl);
834 /* Turn on the window if necessary */
835 if (io->flags & MAP_ACTIVE)
836 i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
838 } /* i365_set_io_map */
840 /*====================================================================*/
842 int i82365_init (void)
848 if (SPD67290Init () != 0)
851 if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
852 /* Controller not found */
855 debug ("i82365 Device Found!\n");
857 pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
858 socket.cb_phys &= ~0xf;
861 /* + 0xfe000000 see MPC 8245 Users Manual Adress Map B */
862 socket.cb_phys += 0xfe000000;
865 get_bridge_state (&socket);
866 set_bridge_opts (&socket);
868 i = i365_get_status (&socket, &val);
872 puts (pcic[socket.type].name);
874 printf ("i82365: Controller not found.\n");
877 #else /* !CONFIG_CPC45 */
878 if (val & SS_DETECT) {
879 if (val & SS_3VCARD) {
880 state.Vcc = state.Vpp = 33;
881 puts (" 3.3V card found: ");
882 } else if (!(val & SS_XVCARD)) {
883 state.Vcc = state.Vpp = 50;
884 puts (" 5.0V card found: ");
886 puts ("i82365: unsupported voltage key\n");
887 state.Vcc = state.Vpp = 0;
890 /* No card inserted */
894 #endif /* CONFIG_CPC45 */
897 state.flags |= SS_OUTPUT_ENA;
899 state.flags = SS_IOCARD | SS_OUTPUT_ENA;
904 i365_set_socket (&socket, &state);
906 for (i = 500; i; i--) {
907 if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
913 /* PC Card not ready for data transfer */
914 puts ("i82365 PC Card not ready for data transfer\n");
917 debug (" PC Card ready for data transfer: ");
920 mem.flags = MAP_ATTRIB | MAP_ACTIVE;
922 mem.sys_start = CFG_PCMCIA_MEM_ADDR;
923 mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1;
925 i365_set_mem_map (&socket, &mem);
929 mem.flags = MAP_ACTIVE;
931 mem.sys_start = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE;
932 mem.sys_stop = CFG_PCMCIA_MEM_ADDR + (2 * CFG_PCMCIA_MEM_SIZE) - 1;
934 i365_set_mem_map (&socket, &mem);
936 #else /* !CONFIG_CPC45 */
939 io.flags = MAP_AUTOSZ | MAP_ACTIVE;
943 i365_set_io_map (&socket, &io);
945 #endif /* CONFIG_CPC45 */
948 i82365_dump_regions (socket.dev);
954 void i82365_exit (void)
962 i365_set_io_map (&socket, &io);
968 mem.sys_stop = 0x1000;
971 i365_set_mem_map (&socket, &mem);
978 mem.sys_stop = 0x1000;
981 i365_set_mem_map (&socket, &mem);
982 #else /* !CONFIG_CPC45 */
983 socket.state.sysctl &= 0xFFFF00FF;
985 state.Vcc = state.Vpp = 0;
987 i365_set_socket (&socket, &state);
990 /*======================================================================
994 ======================================================================*/
997 static void i82365_dump_regions (pci_dev_t dev)
1000 u_int *mem = (void *) socket.cb_phys;
1001 u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR;
1002 u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET);
1004 pci_read_config_dword (dev, 0x00, tmp + 0);
1005 pci_read_config_dword (dev, 0x80, tmp + 1);
1007 printf ("PCI CONF: %08X ... %08X\n", tmp[0], tmp[1]);
1008 printf ("PCI MEM: ... %08X ... %08X\n", mem[0x8 / 4], mem[0x800 / 4]);
1009 printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
1010 cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
1011 cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
1012 printf ("CIS CONF: %02X %02X %02X ...\n",
1013 cis[0x200], cis[0x202], cis[0x204]);
1014 printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
1015 ide[0], ide[1], ide[2], ide[3],
1016 ide[4], ide[5], ide[6], ide[7]);
1020 #endif /* CONFIG_I82365 */