drivers/i3c/master/dw-i3c-master.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
   4  *
   5  * Author: Vitor Soares <vitor.soares@synopsys.com>
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/clk.h>
  10 #include <linux/completion.h>
  11 #include <linux/err.h>
  12 #include <linux/errno.h>
  13 #include <linux/i3c/master.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/ioport.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/list.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/reset.h>
  22 #include <linux/slab.h>
  23
  24 #define DEVICE_CTRL                     0x0
  25 #define DEV_CTRL_ENABLE                 BIT(31)
  26 #define DEV_CTRL_RESUME                 BIT(30)
  27 #define DEV_CTRL_HOT_JOIN_NACK          BIT(8)
  28 #define DEV_CTRL_I2C_SLAVE_PRESENT      BIT(7)
  29
  30 #define DEVICE_ADDR                     0x4
  31 #define DEV_ADDR_DYNAMIC_ADDR_VALID     BIT(31)
  32 #define DEV_ADDR_DYNAMIC(x)             (((x) << 16) & GENMASK(22, 16))
  33
  34 #define HW_CAPABILITY                   0x8
  35 #define COMMAND_QUEUE_PORT              0xc
  36 #define COMMAND_PORT_TOC                BIT(30)
  37 #define COMMAND_PORT_READ_TRANSFER      BIT(28)
  38 #define COMMAND_PORT_SDAP               BIT(27)
  39 #define COMMAND_PORT_ROC                BIT(26)
  40 #define COMMAND_PORT_SPEED(x)           (((x) << 21) & GENMASK(23, 21))
  41 #define COMMAND_PORT_DEV_INDEX(x)       (((x) << 16) & GENMASK(20, 16))
  42 #define COMMAND_PORT_CP                 BIT(15)
  43 #define COMMAND_PORT_CMD(x)             (((x) << 7) & GENMASK(14, 7))
  44 #define COMMAND_PORT_TID(x)             (((x) << 3) & GENMASK(6, 3))
  45
  46 #define COMMAND_PORT_ARG_DATA_LEN(x)    (((x) << 16) & GENMASK(31, 16))
  47 #define COMMAND_PORT_ARG_DATA_LEN_MAX   65536
  48 #define COMMAND_PORT_TRANSFER_ARG       0x01
  49
  50 #define COMMAND_PORT_SDA_DATA_BYTE_3(x) (((x) << 24) & GENMASK(31, 24))
  51 #define COMMAND_PORT_SDA_DATA_BYTE_2(x) (((x) << 16) & GENMASK(23, 16))
  52 #define COMMAND_PORT_SDA_DATA_BYTE_1(x) (((x) << 8) & GENMASK(15, 8))
  53 #define COMMAND_PORT_SDA_BYTE_STRB_3    BIT(5)
  54 #define COMMAND_PORT_SDA_BYTE_STRB_2    BIT(4)
  55 #define COMMAND_PORT_SDA_BYTE_STRB_1    BIT(3)
  56 #define COMMAND_PORT_SHORT_DATA_ARG     0x02
  57
  58 #define COMMAND_PORT_DEV_COUNT(x)       (((x) << 21) & GENMASK(25, 21))
  59 #define COMMAND_PORT_ADDR_ASSGN_CMD     0x03
  60
  61 #define RESPONSE_QUEUE_PORT             0x10
  62 #define RESPONSE_PORT_ERR_STATUS(x)     (((x) & GENMASK(31, 28)) >> 28)
  63 #define RESPONSE_NO_ERROR               0
  64 #define RESPONSE_ERROR_CRC              1
  65 #define RESPONSE_ERROR_PARITY           2
  66 #define RESPONSE_ERROR_FRAME            3
  67 #define RESPONSE_ERROR_IBA_NACK         4
  68 #define RESPONSE_ERROR_ADDRESS_NACK     5
  69 #define RESPONSE_ERROR_OVER_UNDER_FLOW  6
  70 #define RESPONSE_ERROR_TRANSF_ABORT     8
  71 #define RESPONSE_ERROR_I2C_W_NACK_ERR   9
  72 #define RESPONSE_PORT_TID(x)            (((x) & GENMASK(27, 24)) >> 24)
  73 #define RESPONSE_PORT_DATA_LEN(x)       ((x) & GENMASK(15, 0))
  74
  75 #define RX_TX_DATA_PORT                 0x14
  76 #define IBI_QUEUE_STATUS                0x18
  77 #define QUEUE_THLD_CTRL                 0x1c
  78 #define QUEUE_THLD_CTRL_RESP_BUF_MASK   GENMASK(15, 8)
  79 #define QUEUE_THLD_CTRL_RESP_BUF(x)     (((x) - 1) << 8)
  80
  81 #define DATA_BUFFER_THLD_CTRL           0x20
  82 #define DATA_BUFFER_THLD_CTRL_RX_BUF    GENMASK(11, 8)
  83
  84 #define IBI_QUEUE_CTRL                  0x24
  85 #define IBI_MR_REQ_REJECT               0x2C
  86 #define IBI_SIR_REQ_REJECT              0x30
  87 #define IBI_REQ_REJECT_ALL              GENMASK(31, 0)
  88
  89 #define RESET_CTRL                      0x34
  90 #define RESET_CTRL_IBI_QUEUE            BIT(5)
  91 #define RESET_CTRL_RX_FIFO              BIT(4)
  92 #define RESET_CTRL_TX_FIFO              BIT(3)
  93 #define RESET_CTRL_RESP_QUEUE           BIT(2)
  94 #define RESET_CTRL_CMD_QUEUE            BIT(1)
  95 #define RESET_CTRL_SOFT                 BIT(0)
  96
  97 #define SLV_EVENT_CTRL                  0x38
  98 #define INTR_STATUS                     0x3c
  99 #define INTR_STATUS_EN                  0x40
 100 #define INTR_SIGNAL_EN                  0x44
 101 #define INTR_FORCE                      0x48
 102 #define INTR_BUSOWNER_UPDATE_STAT       BIT(13)
 103 #define INTR_IBI_UPDATED_STAT           BIT(12)
 104 #define INTR_READ_REQ_RECV_STAT         BIT(11)
 105 #define INTR_DEFSLV_STAT                BIT(10)
 106 #define INTR_TRANSFER_ERR_STAT          BIT(9)
 107 #define INTR_DYN_ADDR_ASSGN_STAT        BIT(8)
 108 #define INTR_CCC_UPDATED_STAT           BIT(6)
 109 #define INTR_TRANSFER_ABORT_STAT        BIT(5)
 110 #define INTR_RESP_READY_STAT            BIT(4)
 111 #define INTR_CMD_QUEUE_READY_STAT       BIT(3)
 112 #define INTR_IBI_THLD_STAT              BIT(2)
 113 #define INTR_RX_THLD_STAT               BIT(1)
 114 #define INTR_TX_THLD_STAT               BIT(0)
 115 #define INTR_ALL                        (INTR_BUSOWNER_UPDATE_STAT |    \
 116                                         INTR_IBI_UPDATED_STAT |         \
 117                                         INTR_READ_REQ_RECV_STAT |       \
 118                                         INTR_DEFSLV_STAT |              \
 119                                         INTR_TRANSFER_ERR_STAT |        \
 120                                         INTR_DYN_ADDR_ASSGN_STAT |      \
 121                                         INTR_CCC_UPDATED_STAT |         \
 122                                         INTR_TRANSFER_ABORT_STAT |      \
 123                                         INTR_RESP_READY_STAT |          \
 124                                         INTR_CMD_QUEUE_READY_STAT |     \
 125                                         INTR_IBI_THLD_STAT |            \
 126                                         INTR_TX_THLD_STAT |             \
 127                                         INTR_RX_THLD_STAT)
 128
 129 #define INTR_MASTER_MASK                (INTR_TRANSFER_ERR_STAT |       \
 130                                          INTR_RESP_READY_STAT)
 131
 132 #define QUEUE_STATUS_LEVEL              0x4c
 133 #define QUEUE_STATUS_IBI_STATUS_CNT(x)  (((x) & GENMASK(28, 24)) >> 24)
 134 #define QUEUE_STATUS_IBI_BUF_BLR(x)     (((x) & GENMASK(23, 16)) >> 16)
 135 #define QUEUE_STATUS_LEVEL_RESP(x)      (((x) & GENMASK(15, 8)) >> 8)
 136 #define QUEUE_STATUS_LEVEL_CMD(x)       ((x) & GENMASK(7, 0))
 137
 138 #define DATA_BUFFER_STATUS_LEVEL        0x50
 139 #define DATA_BUFFER_STATUS_LEVEL_TX(x)  ((x) & GENMASK(7, 0))
 140
 141 #define PRESENT_STATE                   0x54
 142 #define CCC_DEVICE_STATUS               0x58
 143 #define DEVICE_ADDR_TABLE_POINTER       0x5c
 144 #define DEVICE_ADDR_TABLE_DEPTH(x)      (((x) & GENMASK(31, 16)) >> 16)
 145 #define DEVICE_ADDR_TABLE_ADDR(x)       ((x) & GENMASK(7, 0))
 146
 147 #define DEV_CHAR_TABLE_POINTER          0x60
 148 #define VENDOR_SPECIFIC_REG_POINTER     0x6c
 149 #define SLV_PID_VALUE                   0x74
 150 #define SLV_CHAR_CTRL                   0x78
 151 #define SLV_MAX_LEN                     0x7c
 152 #define MAX_READ_TURNAROUND             0x80
 153 #define MAX_DATA_SPEED                  0x84
 154 #define SLV_DEBUG_STATUS                0x88
 155 #define SLV_INTR_REQ                    0x8c
 156 #define DEVICE_CTRL_EXTENDED            0xb0
 157 #define SCL_I3C_OD_TIMING               0xb4
 158 #define SCL_I3C_PP_TIMING               0xb8
 159 #define SCL_I3C_TIMING_HCNT(x)          (((x) << 16) & GENMASK(23, 16))
 160 #define SCL_I3C_TIMING_LCNT(x)          ((x) & GENMASK(7, 0))
 161 #define SCL_I3C_TIMING_CNT_MIN          5
 162
 163 #define SCL_I2C_FM_TIMING               0xbc
 164 #define SCL_I2C_FM_TIMING_HCNT(x)       (((x) << 16) & GENMASK(31, 16))
 165 #define SCL_I2C_FM_TIMING_LCNT(x)       ((x) & GENMASK(15, 0))
 166
 167 #define SCL_I2C_FMP_TIMING              0xc0
 168 #define SCL_I2C_FMP_TIMING_HCNT(x)      (((x) << 16) & GENMASK(23, 16))
 169 #define SCL_I2C_FMP_TIMING_LCNT(x)      ((x) & GENMASK(15, 0))
 170
 171 #define SCL_EXT_LCNT_TIMING             0xc8
 172 #define SCL_EXT_LCNT_4(x)               (((x) << 24) & GENMASK(31, 24))
 173 #define SCL_EXT_LCNT_3(x)               (((x) << 16) & GENMASK(23, 16))
 174 #define SCL_EXT_LCNT_2(x)               (((x) << 8) & GENMASK(15, 8))
 175 #define SCL_EXT_LCNT_1(x)               ((x) & GENMASK(7, 0))
 176
 177 #define SCL_EXT_TERMN_LCNT_TIMING       0xcc
 178 #define BUS_FREE_TIMING                 0xd4
 179 #define BUS_I3C_MST_FREE(x)             ((x) & GENMASK(15, 0))
 180
 181 #define BUS_IDLE_TIMING                 0xd8
 182 #define I3C_VER_ID                      0xe0
 183 #define I3C_VER_TYPE                    0xe4
 184 #define EXTENDED_CAPABILITY             0xe8
 185 #define SLAVE_CONFIG                    0xec
 186
 187 #define DEV_ADDR_TABLE_LEGACY_I2C_DEV   BIT(31)
 188 #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x)  (((x) << 16) & GENMASK(23, 16))
 189 #define DEV_ADDR_TABLE_STATIC_ADDR(x)   ((x) & GENMASK(6, 0))
 190 #define DEV_ADDR_TABLE_LOC(start, idx)  ((start) + ((idx) << 2))
 191
 192 #define MAX_DEVS 32
 193
 194 #define I3C_BUS_SDR1_SCL_RATE           8000000
 195 #define I3C_BUS_SDR2_SCL_RATE           6000000
 196 #define I3C_BUS_SDR3_SCL_RATE           4000000
 197 #define I3C_BUS_SDR4_SCL_RATE           2000000
 198 #define I3C_BUS_I2C_FM_TLOW_MIN_NS      1300
 199 #define I3C_BUS_I2C_FMP_TLOW_MIN_NS     500
 200 #define I3C_BUS_THIGH_MAX_NS            41
 201
 202 #define XFER_TIMEOUT (msecs_to_jiffies(1000))
 203
 204 struct dw_i3c_master_caps {
 205         u8 cmdfifodepth;
 206         u8 datafifodepth;
 207 };
 208
 209 struct dw_i3c_cmd {
 210         u32 cmd_lo;
 211         u32 cmd_hi;
 212         u16 tx_len;
 213         const void *tx_buf;
 214         u16 rx_len;
 215         void *rx_buf;
 216         u8 error;
 217 };
 218
 219 struct dw_i3c_xfer {
 220         struct list_head node;
 221         struct completion comp;
 222         int ret;
 223         unsigned int ncmds;
 224         struct dw_i3c_cmd cmds[0];
 225 };
 226
 227 struct dw_i3c_master {
 228         struct i3c_master_controller base;
 229         u16 maxdevs;
 230         u16 datstartaddr;
 231         u32 free_pos;
 232         struct {
 233                 struct list_head list;
 234                 struct dw_i3c_xfer *cur;
 235                 spinlock_t lock;
 236         } xferqueue;
 237         struct dw_i3c_master_caps caps;
 238         void __iomem *regs;
 239         struct reset_control *core_rst;
 240         struct clk *core_clk;
 241         char version[5];
 242         char type[5];
 243         u8 addrs[MAX_DEVS];
 244 };
 245
 246 struct dw_i3c_i2c_dev_data {
 247         u8 index;
 248 };
 249
 250 static u8 even_parity(u8 p)
 251 {
 252         p ^= p >> 4;
 253         p &= 0xf;
 254
 255         return (0x9669 >> p) & 1;
 256 }
 257
 258 static bool dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m,
 259                                            const struct i3c_ccc_cmd *cmd)
 260 {
 261         if (cmd->ndests > 1)
 262                 return false;
 263
 264         switch (cmd->id) {
 265         case I3C_CCC_ENEC(true):
 266         case I3C_CCC_ENEC(false):
 267         case I3C_CCC_DISEC(true):
 268         case I3C_CCC_DISEC(false):
 269         case I3C_CCC_ENTAS(0, true):
 270         case I3C_CCC_ENTAS(0, false):
 271         case I3C_CCC_RSTDAA(true):
 272         case I3C_CCC_RSTDAA(false):
 273         case I3C_CCC_ENTDAA:
 274         case I3C_CCC_SETMWL(true):
 275         case I3C_CCC_SETMWL(false):
 276         case I3C_CCC_SETMRL(true):
 277         case I3C_CCC_SETMRL(false):
 278         case I3C_CCC_ENTHDR(0):
 279         case I3C_CCC_SETDASA:
 280         case I3C_CCC_SETNEWDA:
 281         case I3C_CCC_GETMWL:
 282         case I3C_CCC_GETMRL:
 283         case I3C_CCC_GETPID:
 284         case I3C_CCC_GETBCR:
 285         case I3C_CCC_GETDCR:
 286         case I3C_CCC_GETSTATUS:
 287         case I3C_CCC_GETMXDS:
 288         case I3C_CCC_GETHDRCAP:
 289                 return true;
 290         default:
 291                 return false;
 292         }
 293 }
 294
 295 static inline struct dw_i3c_master *
 296 to_dw_i3c_master(struct i3c_master_controller *master)
 297 {
 298         return container_of(master, struct dw_i3c_master, base);
 299 }
 300
 301 static void dw_i3c_master_disable(struct dw_i3c_master *master)
 302 {
 303         writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_ENABLE,
 304                master->regs + DEVICE_CTRL);
 305 }
 306
 307 static void dw_i3c_master_enable(struct dw_i3c_master *master)
 308 {
 309         writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_ENABLE,
 310                master->regs + DEVICE_CTRL);
 311 }
 312
 313 static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr)
 314 {
 315         int pos;
 316
 317         for (pos = 0; pos < master->maxdevs; pos++) {
 318                 if (addr == master->addrs[pos])
 319                         return pos;
 320         }
 321
 322         return -EINVAL;
 323 }
 324
 325 static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master)
 326 {
 327         if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0)))
 328                 return -ENOSPC;
 329
 330         return ffs(master->free_pos) - 1;
 331 }
 332
 333 static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master,
 334                                      const u8 *bytes, int nbytes)
 335 {
 336         writesl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4);
 337         if (nbytes & 3) {
 338                 u32 tmp = 0;
 339
 340                 memcpy(&tmp, bytes + (nbytes & ~3), nbytes & 3);
 341                 writesl(master->regs + RX_TX_DATA_PORT, &tmp, 1);
 342         }
 343 }
 344
 345 static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master,
 346                                        u8 *bytes, int nbytes)
 347 {
 348         readsl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4);
 349         if (nbytes & 3) {
 350                 u32 tmp;
 351
 352                 readsl(master->regs + RX_TX_DATA_PORT, &tmp, 1);
 353                 memcpy(bytes + (nbytes & ~3), &tmp, nbytes & 3);
 354         }
 355 }
 356
 357 static struct dw_i3c_xfer *
 358 dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds)
 359 {
 360         struct dw_i3c_xfer *xfer;
 361
 362         xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL);
 363         if (!xfer)
 364                 return NULL;
 365
 366         INIT_LIST_HEAD(&xfer->node);
 367         xfer->ncmds = ncmds;
 368         xfer->ret = -ETIMEDOUT;
 369
 370         return xfer;
 371 }
 372
 373 static void dw_i3c_master_free_xfer(struct dw_i3c_xfer *xfer)
 374 {
 375         kfree(xfer);
 376 }
 377
 378 static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master)
 379 {
 380         struct dw_i3c_xfer *xfer = master->xferqueue.cur;
 381         unsigned int i;
 382         u32 thld_ctrl;
 383
 384         if (!xfer)
 385                 return;
 386
 387         for (i = 0; i < xfer->ncmds; i++) {
 388                 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
 389
 390                 dw_i3c_master_wr_tx_fifo(master, cmd->tx_buf, cmd->tx_len);
 391         }
 392
 393         thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
 394         thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK;
 395         thld_ctrl |= QUEUE_THLD_CTRL_RESP_BUF(xfer->ncmds);
 396         writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
 397
 398         for (i = 0; i < xfer->ncmds; i++) {
 399                 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
 400
 401                 writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT);
 402                 writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT);
 403         }
 404 }
 405
 406 static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master,
 407                                        struct dw_i3c_xfer *xfer)
 408 {
 409         unsigned long flags;
 410
 411         init_completion(&xfer->comp);
 412         spin_lock_irqsave(&master->xferqueue.lock, flags);
 413         if (master->xferqueue.cur) {
 414                 list_add_tail(&xfer->node, &master->xferqueue.list);
 415         } else {
 416                 master->xferqueue.cur = xfer;
 417                 dw_i3c_master_start_xfer_locked(master);
 418         }
 419         spin_unlock_irqrestore(&master->xferqueue.lock, flags);
 420 }
 421
 422 static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master,
 423                                               struct dw_i3c_xfer *xfer)
 424 {
 425         if (master->xferqueue.cur == xfer) {
 426                 u32 status;
 427
 428                 master->xferqueue.cur = NULL;
 429
 430                 writel(RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO |
 431                        RESET_CTRL_RESP_QUEUE | RESET_CTRL_CMD_QUEUE,
 432                        master->regs + RESET_CTRL);
 433
 434                 readl_poll_timeout_atomic(master->regs + RESET_CTRL, status,
 435                                           !status, 10, 1000000);
 436         } else {
 437                 list_del_init(&xfer->node);
 438         }
 439 }
 440
 441 static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master,
 442                                        struct dw_i3c_xfer *xfer)
 443 {
 444         unsigned long flags;
 445
 446         spin_lock_irqsave(&master->xferqueue.lock, flags);
 447         dw_i3c_master_dequeue_xfer_locked(master, xfer);
 448         spin_unlock_irqrestore(&master->xferqueue.lock, flags);
 449 }
 450
 451 static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr)
 452 {
 453         struct dw_i3c_xfer *xfer = master->xferqueue.cur;
 454         int i, ret = 0;
 455         u32 nresp;
 456
 457         if (!xfer)
 458                 return;
 459
 460         nresp = readl(master->regs + QUEUE_STATUS_LEVEL);
 461         nresp = QUEUE_STATUS_LEVEL_RESP(nresp);
 462
 463         for (i = 0; i < nresp; i++) {
 464                 struct dw_i3c_cmd *cmd;
 465                 u32 resp;
 466
 467                 resp = readl(master->regs + RESPONSE_QUEUE_PORT);
 468
 469                 cmd = &xfer->cmds[RESPONSE_PORT_TID(resp)];
 470                 cmd->rx_len = RESPONSE_PORT_DATA_LEN(resp);
 471                 cmd->error = RESPONSE_PORT_ERR_STATUS(resp);
 472                 if (cmd->rx_len && !cmd->error)
 473                         dw_i3c_master_read_rx_fifo(master, cmd->rx_buf,
 474                                                    cmd->rx_len);
 475         }
 476
 477         for (i = 0; i < nresp; i++) {
 478                 switch (xfer->cmds[i].error) {
 479                 case RESPONSE_NO_ERROR:
 480                         break;
 481                 case RESPONSE_ERROR_PARITY:
 482                 case RESPONSE_ERROR_IBA_NACK:
 483                 case RESPONSE_ERROR_TRANSF_ABORT:
 484                 case RESPONSE_ERROR_CRC:
 485                 case RESPONSE_ERROR_FRAME:
 486                         ret = -EIO;
 487                         break;
 488                 case RESPONSE_ERROR_OVER_UNDER_FLOW:
 489                         ret = -ENOSPC;
 490                         break;
 491                 case RESPONSE_ERROR_I2C_W_NACK_ERR:
 492                 case RESPONSE_ERROR_ADDRESS_NACK:
 493                 default:
 494                         ret = -EINVAL;
 495                         break;
 496                 }
 497         }
 498
 499         xfer->ret = ret;
 500         complete(&xfer->comp);
 501
 502         if (ret < 0) {
 503                 dw_i3c_master_dequeue_xfer_locked(master, xfer);
 504                 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME,
 505                        master->regs + DEVICE_CTRL);
 506         }
 507
 508         xfer = list_first_entry_or_null(&master->xferqueue.list,
 509                                         struct dw_i3c_xfer,
 510                                         node);
 511         if (xfer)
 512                 list_del_init(&xfer->node);
 513
 514         master->xferqueue.cur = xfer;
 515         dw_i3c_master_start_xfer_locked(master);
 516 }
 517
 518 static int dw_i3c_clk_cfg(struct dw_i3c_master *master)
 519 {
 520         unsigned long core_rate, core_period;
 521         u32 scl_timing;
 522         u8 hcnt, lcnt;
 523
 524         core_rate = clk_get_rate(master->core_clk);
 525         if (!core_rate)
 526                 return -EINVAL;
 527
 528         core_period = DIV_ROUND_UP(1000000000, core_rate);
 529
 530         hcnt = DIV_ROUND_UP(I3C_BUS_THIGH_MAX_NS, core_period) - 1;
 531         if (hcnt < SCL_I3C_TIMING_CNT_MIN)
 532                 hcnt = SCL_I3C_TIMING_CNT_MIN;
 533
 534         lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_TYP_I3C_SCL_RATE) - hcnt;
 535         if (lcnt < SCL_I3C_TIMING_CNT_MIN)
 536                 lcnt = SCL_I3C_TIMING_CNT_MIN;
 537
 538         scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
 539         writel(scl_timing, master->regs + SCL_I3C_PP_TIMING);
 540
 541         if (!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_I2C_SLAVE_PRESENT))
 542                 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
 543
 544         lcnt = DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period);
 545         scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
 546         writel(scl_timing, master->regs + SCL_I3C_OD_TIMING);
 547
 548         lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR1_SCL_RATE) - hcnt;
 549         scl_timing = SCL_EXT_LCNT_1(lcnt);
 550         lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR2_SCL_RATE) - hcnt;
 551         scl_timing |= SCL_EXT_LCNT_2(lcnt);
 552         lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR3_SCL_RATE) - hcnt;
 553         scl_timing |= SCL_EXT_LCNT_3(lcnt);
 554         lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR4_SCL_RATE) - hcnt;
 555         scl_timing |= SCL_EXT_LCNT_4(lcnt);
 556         writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING);
 557
 558         return 0;
 559 }
 560
 561 static int dw_i2c_clk_cfg(struct dw_i3c_master *master)
 562 {
 563         unsigned long core_rate, core_period;
 564         u16 hcnt, lcnt;
 565         u32 scl_timing;
 566
 567         core_rate = clk_get_rate(master->core_clk);
 568         if (!core_rate)
 569                 return -EINVAL;
 570
 571         core_period = DIV_ROUND_UP(1000000000, core_rate);
 572
 573         lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FMP_TLOW_MIN_NS, core_period);
 574         hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_PLUS_SCL_RATE) - lcnt;
 575         scl_timing = SCL_I2C_FMP_TIMING_HCNT(hcnt) |
 576                      SCL_I2C_FMP_TIMING_LCNT(lcnt);
 577         writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING);
 578
 579         lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FM_TLOW_MIN_NS, core_period);
 580         hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_SCL_RATE) - lcnt;
 581         scl_timing = SCL_I2C_FM_TIMING_HCNT(hcnt) |
 582                      SCL_I2C_FM_TIMING_LCNT(lcnt);
 583         writel(scl_timing, master->regs + SCL_I2C_FM_TIMING);
 584
 585         writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
 586         writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT,
 587                master->regs + DEVICE_CTRL);
 588
 589         return 0;
 590 }
 591
 592 static int dw_i3c_master_bus_init(struct i3c_master_controller *m)
 593 {
 594         struct dw_i3c_master *master = to_dw_i3c_master(m);
 595         struct i3c_bus *bus = i3c_master_get_bus(m);
 596         struct i3c_device_info info = { };
 597         u32 thld_ctrl;
 598         int ret;
 599
 600         switch (bus->mode) {
 601         case I3C_BUS_MODE_MIXED_FAST:
 602         case I3C_BUS_MODE_MIXED_LIMITED:
 603                 ret = dw_i2c_clk_cfg(master);
 604                 if (ret)
 605                         return ret;
 606                 /* fall through */
 607         case I3C_BUS_MODE_PURE:
 608                 ret = dw_i3c_clk_cfg(master);
 609                 if (ret)
 610                         return ret;
 611                 break;
 612         default:
 613                 return -EINVAL;
 614         }
 615
 616         thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
 617         thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK;
 618         writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
 619
 620         thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL);
 621         thld_ctrl &= ~DATA_BUFFER_THLD_CTRL_RX_BUF;
 622         writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL);
 623
 624         writel(INTR_ALL, master->regs + INTR_STATUS);
 625         writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN);
 626         writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN);
 627
 628         ret = i3c_master_get_free_addr(m, 0);
 629         if (ret < 0)
 630                 return ret;
 631
 632         writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret),
 633                master->regs + DEVICE_ADDR);
 634
 635         memset(&info, 0, sizeof(info));
 636         info.dyn_addr = ret;
 637
 638         ret = i3c_master_set_info(&master->base, &info);
 639         if (ret)
 640                 return ret;
 641
 642         writel(IBI_REQ_REJECT_ALL, master->regs + IBI_SIR_REQ_REJECT);
 643         writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT);
 644
 645         /* For now don't support Hot-Join */
 646         writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK,
 647                master->regs + DEVICE_CTRL);
 648
 649         dw_i3c_master_enable(master);
 650
 651         return 0;
 652 }
 653
 654 static void dw_i3c_master_bus_cleanup(struct i3c_master_controller *m)
 655 {
 656         struct dw_i3c_master *master = to_dw_i3c_master(m);
 657
 658         dw_i3c_master_disable(master);
 659 }
 660
 661 static int dw_i3c_ccc_set(struct dw_i3c_master *master,
 662                           struct i3c_ccc_cmd *ccc)
 663 {
 664         struct dw_i3c_xfer *xfer;
 665         struct dw_i3c_cmd *cmd;
 666         int ret, pos = 0;
 667
 668         if (ccc->id & I3C_CCC_DIRECT) {
 669                 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
 670                 if (pos < 0)
 671                         return pos;
 672         }
 673
 674         xfer = dw_i3c_master_alloc_xfer(master, 1);
 675         if (!xfer)
 676                 return -ENOMEM;
 677
 678         cmd = xfer->cmds;
 679         cmd->tx_buf = ccc->dests[0].payload.data;
 680         cmd->tx_len = ccc->dests[0].payload.len;
 681
 682         cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) |
 683                       COMMAND_PORT_TRANSFER_ARG;
 684
 685         cmd->cmd_lo = COMMAND_PORT_CP |
 686                       COMMAND_PORT_DEV_INDEX(pos) |
 687                       COMMAND_PORT_CMD(ccc->id) |
 688                       COMMAND_PORT_TOC |
 689                       COMMAND_PORT_ROC;
 690
 691         dw_i3c_master_enqueue_xfer(master, xfer);
 692         if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
 693                 dw_i3c_master_dequeue_xfer(master, xfer);
 694
 695         ret = xfer->ret;
 696         if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK)
 697                 ccc->err = I3C_ERROR_M2;
 698
 699         dw_i3c_master_free_xfer(xfer);
 700
 701         return ret;
 702 }
 703
 704 static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc)
 705 {
 706         struct dw_i3c_xfer *xfer;
 707         struct dw_i3c_cmd *cmd;
 708         int ret, pos;
 709
 710         pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
 711         if (pos < 0)
 712                 return pos;
 713
 714         xfer = dw_i3c_master_alloc_xfer(master, 1);
 715         if (!xfer)
 716                 return -ENOMEM;
 717
 718         cmd = xfer->cmds;
 719         cmd->rx_buf = ccc->dests[0].payload.data;
 720         cmd->rx_len = ccc->dests[0].payload.len;
 721
 722         cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) |
 723                       COMMAND_PORT_TRANSFER_ARG;
 724
 725         cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER |
 726                       COMMAND_PORT_CP |
 727                       COMMAND_PORT_DEV_INDEX(pos) |
 728                       COMMAND_PORT_CMD(ccc->id) |
 729                       COMMAND_PORT_TOC |
 730                       COMMAND_PORT_ROC;
 731
 732         dw_i3c_master_enqueue_xfer(master, xfer);
 733         if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
 734                 dw_i3c_master_dequeue_xfer(master, xfer);
 735
 736         ret = xfer->ret;
 737         if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK)
 738                 ccc->err = I3C_ERROR_M2;
 739         dw_i3c_master_free_xfer(xfer);
 740
 741         return ret;
 742 }
 743
 744 static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
 745                                       struct i3c_ccc_cmd *ccc)
 746 {
 747         struct dw_i3c_master *master = to_dw_i3c_master(m);
 748         int ret = 0;
 749
 750         if (ccc->id == I3C_CCC_ENTDAA)
 751                 return -EINVAL;
 752
 753         if (ccc->rnw)
 754                 ret = dw_i3c_ccc_get(master, ccc);
 755         else
 756                 ret = dw_i3c_ccc_set(master, ccc);
 757
 758         return ret;
 759 }
 760
 761 static int dw_i3c_master_daa(struct i3c_master_controller *m)
 762 {
 763         struct dw_i3c_master *master = to_dw_i3c_master(m);
 764         struct dw_i3c_xfer *xfer;
 765         struct dw_i3c_cmd *cmd;
 766         u32 olddevs, newdevs;
 767         u8 p, last_addr = 0;
 768         int ret, pos;
 769
 770         olddevs = ~(master->free_pos);
 771
 772         /* Prepare DAT before launching DAA. */
 773         for (pos = 0; pos < master->maxdevs; pos++) {
 774                 if (olddevs & BIT(pos))
 775                         continue;
 776
 777                 ret = i3c_master_get_free_addr(m, last_addr + 1);
 778                 if (ret < 0)
 779                         return -ENOSPC;
 780
 781                 master->addrs[pos] = ret;
 782                 p = even_parity(ret);
 783                 last_addr = ret;
 784                 ret |= (p << 7);
 785
 786                 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(ret),
 787                        master->regs +
 788                        DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
 789         }
 790
 791         xfer = dw_i3c_master_alloc_xfer(master, 1);
 792         if (!xfer)
 793                 return -ENOMEM;
 794
 795         pos = dw_i3c_master_get_free_pos(master);
 796         cmd = &xfer->cmds[0];
 797         cmd->cmd_hi = 0x1;
 798         cmd->cmd_lo = COMMAND_PORT_DEV_COUNT(master->maxdevs - pos) |
 799                       COMMAND_PORT_DEV_INDEX(pos) |
 800                       COMMAND_PORT_CMD(I3C_CCC_ENTDAA) |
 801                       COMMAND_PORT_ADDR_ASSGN_CMD |
 802                       COMMAND_PORT_TOC |
 803                       COMMAND_PORT_ROC;
 804
 805         dw_i3c_master_enqueue_xfer(master, xfer);
 806         if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
 807                 dw_i3c_master_dequeue_xfer(master, xfer);
 808
 809         newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0);
 810         newdevs &= ~olddevs;
 811
 812         for (pos = 0; pos < master->maxdevs; pos++) {
 813                 if (newdevs & BIT(pos))
 814                         i3c_master_add_i3c_dev_locked(m, master->addrs[pos]);
 815         }
 816
 817         dw_i3c_master_free_xfer(xfer);
 818
 819         i3c_master_disec_locked(m, I3C_BROADCAST_ADDR,
 820                                 I3C_CCC_EVENT_HJ |
 821                                 I3C_CCC_EVENT_MR |
 822                                 I3C_CCC_EVENT_SIR);
 823
 824         return 0;
 825 }
 826
 827 static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
 828                                     struct i3c_priv_xfer *i3c_xfers,
 829                                     int i3c_nxfers)
 830 {
 831         struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
 832         struct i3c_master_controller *m = i3c_dev_get_master(dev);
 833         struct dw_i3c_master *master = to_dw_i3c_master(m);
 834         unsigned int nrxwords = 0, ntxwords = 0;
 835         struct dw_i3c_xfer *xfer;
 836         int i, ret = 0;
 837
 838         if (!i3c_nxfers)
 839                 return 0;
 840
 841         if (i3c_nxfers > master->caps.cmdfifodepth)
 842                 return -ENOTSUPP;
 843
 844         for (i = 0; i < i3c_nxfers; i++) {
 845                 if (i3c_xfers[i].rnw)
 846                         nrxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4);
 847                 else
 848                         ntxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4);
 849         }
 850
 851         if (ntxwords > master->caps.datafifodepth ||
 852             nrxwords > master->caps.datafifodepth)
 853                 return -ENOTSUPP;
 854
 855         xfer = dw_i3c_master_alloc_xfer(master, i3c_nxfers);
 856         if (!xfer)
 857                 return -ENOMEM;
 858
 859         for (i = 0; i < i3c_nxfers; i++) {
 860                 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
 861
 862                 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i3c_xfers[i].len) |
 863                         COMMAND_PORT_TRANSFER_ARG;
 864
 865                 if (i3c_xfers[i].rnw) {
 866                         cmd->rx_buf = i3c_xfers[i].data.in;
 867                         cmd->rx_len = i3c_xfers[i].len;
 868                         cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER |
 869                                       COMMAND_PORT_SPEED(dev->info.max_read_ds);
 870
 871                 } else {
 872                         cmd->tx_buf = i3c_xfers[i].data.out;
 873                         cmd->tx_len = i3c_xfers[i].len;
 874                         cmd->cmd_lo =
 875                                 COMMAND_PORT_SPEED(dev->info.max_write_ds);
 876                 }
 877
 878                 cmd->cmd_lo |= COMMAND_PORT_TID(i) |
 879                                COMMAND_PORT_DEV_INDEX(data->index) |
 880                                COMMAND_PORT_ROC;
 881
 882                 if (i == (i3c_nxfers - 1))
 883                         cmd->cmd_lo |= COMMAND_PORT_TOC;
 884         }
 885
 886         dw_i3c_master_enqueue_xfer(master, xfer);
 887         if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
 888                 dw_i3c_master_dequeue_xfer(master, xfer);
 889
 890         ret = xfer->ret;
 891         dw_i3c_master_free_xfer(xfer);
 892
 893         return ret;
 894 }
 895
 896 static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
 897                                           u8 old_dyn_addr)
 898 {
 899         struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
 900         struct i3c_master_controller *m = i3c_dev_get_master(dev);
 901         struct dw_i3c_master *master = to_dw_i3c_master(m);
 902
 903         writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(dev->info.dyn_addr),
 904                master->regs +
 905                DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
 906
 907         master->addrs[data->index] = dev->info.dyn_addr;
 908
 909         return 0;
 910 }
 911
 912 static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
 913 {
 914         struct i3c_master_controller *m = i3c_dev_get_master(dev);
 915         struct dw_i3c_master *master = to_dw_i3c_master(m);
 916         struct dw_i3c_i2c_dev_data *data;
 917         int pos;
 918
 919         pos = dw_i3c_master_get_free_pos(master);
 920         if (pos < 0)
 921                 return pos;
 922
 923         data = kzalloc(sizeof(*data), GFP_KERNEL);
 924         if (!data)
 925                 return -ENOMEM;
 926
 927         data->index = pos;
 928         master->addrs[pos] = dev->info.dyn_addr ? : dev->info.static_addr;
 929         master->free_pos &= ~BIT(pos);
 930         i3c_dev_set_master_data(dev, data);
 931
 932         writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->addrs[pos]),
 933                master->regs +
 934                DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
 935
 936         return 0;
 937 }
 938
 939 static void dw_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
 940 {
 941         struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
 942         struct i3c_master_controller *m = i3c_dev_get_master(dev);
 943         struct dw_i3c_master *master = to_dw_i3c_master(m);
 944
 945         writel(0,
 946                master->regs +
 947                DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
 948
 949         i3c_dev_set_master_data(dev, NULL);
 950         master->addrs[data->index] = 0;
 951         master->free_pos |= BIT(data->index);
 952         kfree(data);
 953 }
 954
 955 static int dw_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
 956                                    const struct i2c_msg *i2c_xfers,
 957                                    int i2c_nxfers)
 958 {
 959         struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
 960         struct i3c_master_controller *m = i2c_dev_get_master(dev);
 961         struct dw_i3c_master *master = to_dw_i3c_master(m);
 962         unsigned int nrxwords = 0, ntxwords = 0;
 963         struct dw_i3c_xfer *xfer;
 964         int i, ret = 0;
 965
 966         if (!i2c_nxfers)
 967                 return 0;
 968
 969         if (i2c_nxfers > master->caps.cmdfifodepth)
 970                 return -ENOTSUPP;
 971
 972         for (i = 0; i < i2c_nxfers; i++) {
 973                 if (i2c_xfers[i].flags & I2C_M_RD)
 974                         nrxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4);
 975                 else
 976                         ntxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4);
 977         }
 978
 979         if (ntxwords > master->caps.datafifodepth ||
 980             nrxwords > master->caps.datafifodepth)
 981                 return -ENOTSUPP;
 982
 983         xfer = dw_i3c_master_alloc_xfer(master, i2c_nxfers);
 984         if (!xfer)
 985                 return -ENOMEM;
 986
 987         for (i = 0; i < i2c_nxfers; i++) {
 988                 struct dw_i3c_cmd *cmd = &xfer->cmds[i];
 989
 990                 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i2c_xfers[i].len) |
 991                         COMMAND_PORT_TRANSFER_ARG;
 992
 993                 cmd->cmd_lo = COMMAND_PORT_TID(i) |
 994                               COMMAND_PORT_DEV_INDEX(data->index) |
 995                               COMMAND_PORT_ROC;
 996
 997                 if (i2c_xfers[i].flags & I2C_M_RD) {
 998                         cmd->cmd_lo |= COMMAND_PORT_READ_TRANSFER;
 999                         cmd->rx_buf = i2c_xfers[i].buf;
1000                         cmd->rx_len = i2c_xfers[i].len;
1001                 } else {
1002                         cmd->tx_buf = i2c_xfers[i].buf;
1003                         cmd->tx_len = i2c_xfers[i].len;
1004                 }
1005
1006                 if (i == (i2c_nxfers - 1))
1007                         cmd->cmd_lo |= COMMAND_PORT_TOC;
1008         }
1009
1010         dw_i3c_master_enqueue_xfer(master, xfer);
1011         if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
1012                 dw_i3c_master_dequeue_xfer(master, xfer);
1013
1014         ret = xfer->ret;
1015         dw_i3c_master_free_xfer(xfer);
1016
1017         return ret;
1018 }
1019
1020 static int dw_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
1021 {
1022         struct i3c_master_controller *m = i2c_dev_get_master(dev);
1023         struct dw_i3c_master *master = to_dw_i3c_master(m);
1024         struct dw_i3c_i2c_dev_data *data;
1025         int pos;
1026
1027         pos = dw_i3c_master_get_free_pos(master);
1028         if (pos < 0)
1029                 return pos;
1030
1031         data = kzalloc(sizeof(*data), GFP_KERNEL);
1032         if (!data)
1033                 return -ENOMEM;
1034
1035         data->index = pos;
1036         master->addrs[pos] = dev->boardinfo->base.addr;
1037         master->free_pos &= ~BIT(pos);
1038         i2c_dev_set_master_data(dev, data);
1039
1040         writel(DEV_ADDR_TABLE_LEGACY_I2C_DEV |
1041                DEV_ADDR_TABLE_STATIC_ADDR(dev->boardinfo->base.addr),
1042                master->regs +
1043                DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1044
1045         return 0;
1046 }
1047
1048 static void dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
1049 {
1050         struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
1051         struct i3c_master_controller *m = i2c_dev_get_master(dev);
1052         struct dw_i3c_master *master = to_dw_i3c_master(m);
1053
1054         writel(0,
1055                master->regs +
1056                DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1057
1058         i2c_dev_set_master_data(dev, NULL);
1059         master->addrs[data->index] = 0;
1060         master->free_pos |= BIT(data->index);
1061         kfree(data);
1062 }
1063
1064 static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id)
1065 {
1066         struct dw_i3c_master *master = dev_id;
1067         u32 status;
1068
1069         status = readl(master->regs + INTR_STATUS);
1070
1071         if (!(status & readl(master->regs + INTR_STATUS_EN))) {
1072                 writel(INTR_ALL, master->regs + INTR_STATUS);
1073                 return IRQ_NONE;
1074         }
1075
1076         spin_lock(&master->xferqueue.lock);
1077         dw_i3c_master_end_xfer_locked(master, status);
1078         if (status & INTR_TRANSFER_ERR_STAT)
1079                 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS);
1080         spin_unlock(&master->xferqueue.lock);
1081
1082         return IRQ_HANDLED;
1083 }
1084
1085 static const struct i3c_master_controller_ops dw_mipi_i3c_ops = {
1086         .bus_init = dw_i3c_master_bus_init,
1087         .bus_cleanup = dw_i3c_master_bus_cleanup,
1088         .attach_i3c_dev = dw_i3c_master_attach_i3c_dev,
1089         .reattach_i3c_dev = dw_i3c_master_reattach_i3c_dev,
1090         .detach_i3c_dev = dw_i3c_master_detach_i3c_dev,
1091         .do_daa = dw_i3c_master_daa,
1092         .supports_ccc_cmd = dw_i3c_master_supports_ccc_cmd,
1093         .send_ccc_cmd = dw_i3c_master_send_ccc_cmd,
1094         .priv_xfers = dw_i3c_master_priv_xfers,
1095         .attach_i2c_dev = dw_i3c_master_attach_i2c_dev,
1096         .detach_i2c_dev = dw_i3c_master_detach_i2c_dev,
1097         .i2c_xfers = dw_i3c_master_i2c_xfers,
1098 };
1099
1100 static int dw_i3c_probe(struct platform_device *pdev)
1101 {
1102         struct dw_i3c_master *master;
1103         struct resource *res;
1104         int ret, irq;
1105
1106         master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1107         if (!master)
1108                 return -ENOMEM;
1109
1110         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1111         master->regs = devm_ioremap_resource(&pdev->dev, res);
1112         if (IS_ERR(master->regs))
1113                 return PTR_ERR(master->regs);
1114
1115         master->core_clk = devm_clk_get(&pdev->dev, NULL);
1116         if (IS_ERR(master->core_clk))
1117                 return PTR_ERR(master->core_clk);
1118
1119         master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
1120                                                                     "core_rst");
1121         if (IS_ERR(master->core_rst))
1122                 return PTR_ERR(master->core_rst);
1123
1124         ret = clk_prepare_enable(master->core_clk);
1125         if (ret)
1126                 goto err_disable_core_clk;
1127
1128         reset_control_deassert(master->core_rst);
1129
1130         spin_lock_init(&master->xferqueue.lock);
1131         INIT_LIST_HEAD(&master->xferqueue.list);
1132
1133         writel(INTR_ALL, master->regs + INTR_STATUS);
1134         irq = platform_get_irq(pdev, 0);
1135         ret = devm_request_irq(&pdev->dev, irq,
1136                                dw_i3c_master_irq_handler, 0,
1137                                dev_name(&pdev->dev), master);
1138         if (ret)
1139                 goto err_assert_rst;
1140
1141         platform_set_drvdata(pdev, master);
1142
1143         /* Information regarding the FIFOs/QUEUEs depth */
1144         ret = readl(master->regs + QUEUE_STATUS_LEVEL);
1145         master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret);
1146
1147         ret = readl(master->regs + DATA_BUFFER_STATUS_LEVEL);
1148         master->caps.datafifodepth = DATA_BUFFER_STATUS_LEVEL_TX(ret);
1149
1150         ret = readl(master->regs + DEVICE_ADDR_TABLE_POINTER);
1151         master->datstartaddr = ret;
1152         master->maxdevs = ret >> 16;
1153         master->free_pos = GENMASK(master->maxdevs - 1, 0);
1154
1155         ret = i3c_master_register(&master->base, &pdev->dev,
1156                                   &dw_mipi_i3c_ops, false);
1157         if (ret)
1158                 goto err_assert_rst;
1159
1160         return 0;
1161
1162 err_assert_rst:
1163         reset_control_assert(master->core_rst);
1164
1165 err_disable_core_clk:
1166         clk_disable_unprepare(master->core_clk);
1167
1168         return ret;
1169 }
1170
1171 static int dw_i3c_remove(struct platform_device *pdev)
1172 {
1173         struct dw_i3c_master *master = platform_get_drvdata(pdev);
1174         int ret;
1175
1176         ret = i3c_master_unregister(&master->base);
1177         if (ret)
1178                 return ret;
1179
1180         reset_control_assert(master->core_rst);
1181
1182         clk_disable_unprepare(master->core_clk);
1183
1184         return 0;
1185 }
1186
1187 static const struct of_device_id dw_i3c_master_of_match[] = {
1188         { .compatible = "snps,dw-i3c-master-1.00a", },
1189         {},
1190 };
1191 MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match);
1192
1193 static struct platform_driver dw_i3c_driver = {
1194         .probe = dw_i3c_probe,
1195         .remove = dw_i3c_remove,
1196         .driver = {
1197                 .name = "dw-i3c-master",
1198                 .of_match_table = of_match_ptr(dw_i3c_master_of_match),
1199         },
1200 };
1201 module_platform_driver(dw_i3c_driver);
1202
1203 MODULE_AUTHOR("Vitor Soares <vitor.soares@synopsys.com>");
1204 MODULE_DESCRIPTION("DesignWare MIPI I3C driver");
1205 MODULE_LICENSE("GPL v2");