2 * Copyright (C) ST-Ericsson SA 2010
4 * Basic U-Boot I2C interface for STn8500/DB8500
5 * Author: Michael Brandt <Michael.Brandt@stericsson.com> for ST-Ericsson
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * Only 7-bit I2C device addresses are supported.
29 #include "u8500_i2c.h"
31 #include <asm/arch/clock.h>
33 #define U8500_I2C_ENDAD_COUNTER (CONFIG_SYS_HZ/100) /* I2C bus timeout */
34 #define U8500_I2C_FIFO_FLUSH_COUNTER 500000 /* flush "timeout" */
35 #define U8500_I2C_SCL_FREQ 100000 /* I2C bus clock freq */
36 #define U8500_I2C_INPUT_FREQ 48000000 /* Input clock freq */
37 #define TX_FIFO_THRESHOLD 0x4
38 #define RX_FIFO_THRESHOLD 0x4
39 #define SLAVE_SETUP_TIME 14 /* Slave data setup time, 250ns for 48MHz i2c_clk */
41 #define WRITE_FIELD(var, mask, shift, value) \
42 (var = ((var & ~(mask)) | ((value) << (shift))))
44 static unsigned int bus_initialized[CONFIG_SYS_U8500_I2C_BUS_MAX];
45 static unsigned int i2c_bus_num;
46 static unsigned int i2c_bus_speed[] = {
47 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED,
48 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED
50 static struct u8500_i2c_regs *i2c_dev[] = {
51 (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C0_BASE,
52 (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C1_BASE,
53 (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C2_BASE,
54 (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C3_BASE,
61 } i2c_clock_bits[] = {
68 static void i2c_set_bit(void *reg, u32 mask)
70 writel(readl(reg) | mask, reg);
73 static void i2c_clr_bit(void *reg, u32 mask)
75 writel(readl(reg) & ~mask, reg);
78 static void i2c_write_field(void *reg, u32 mask, uint shift, u32 value)
80 writel((readl(reg) & ~mask) | (value << shift), reg);
83 static int __i2c_set_bus_speed(unsigned int speed)
86 struct u8500_i2c_regs *i2c_regs;
88 i2c_regs = i2c_dev[i2c_bus_num];
90 /* Select standard (100 kbps) speed mode */
91 i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_SM,
92 U8500_I2C_CR_SHIFT_SM, 0x0);
95 * Set the Baud Rate Counter 2 value
96 * Baud rate (standard) = fi2cclk / ( (BRCNT2 x 2) + Foncycle )
97 * Foncycle = 0 (no digital filtering)
99 value = (u32) (U8500_I2C_INPUT_FREQ / (speed * 2));
100 i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT2,
101 U8500_I2C_BRCR_SHIFT_BRCNT2, value);
103 /* ensure that BRCNT value is zero */
104 i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT1,
105 U8500_I2C_BRCR_SHIFT_BRCNT1, 0);
107 return U8500_I2C_INPUT_FREQ/(value * 2);
111 * i2c_init - initialize the i2c bus
113 * speed: bus speed (in HZ)
114 * slaveaddr: address of device in slave mode
116 * Slave mode is not implemented.
118 void i2c_init(int speed, int slaveaddr)
120 struct u8500_i2c_regs *i2c_regs;
122 debug("i2c_init bus %d, speed %d\n", i2c_bus_num, speed);
124 u8500_clock_enable(i2c_clock_bits[i2c_bus_num].periph,
125 i2c_clock_bits[i2c_bus_num].pcken,
126 i2c_clock_bits[i2c_bus_num].kcken);
128 i2c_regs = i2c_dev[i2c_bus_num];
130 /* Disable the controller */
131 i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_PE);
133 /* Clear registers */
134 writel(0, &i2c_regs->cr);
135 writel(0, &i2c_regs->scr);
136 writel(0, &i2c_regs->hsmcr);
137 writel(0, &i2c_regs->tftr);
138 writel(0, &i2c_regs->rftr);
139 writel(0, &i2c_regs->dmar);
141 i2c_bus_speed[i2c_bus_num] = __i2c_set_bus_speed(speed);
144 * Set our own address.
145 * Set slave address mode to 7 bit addressing mode
147 i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_SAM);
148 i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_ADDR,
149 U8500_I2C_SCR_SHIFT_ADDR, slaveaddr);
150 /* Slave Data Set up Time */
151 i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_DATA_SETUP_TIME,
152 U8500_I2C_SCR_SHIFT_DATA_SETUP_TIME, SLAVE_SETUP_TIME);
154 /* Disable the DMA sync logic */
155 i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_DMA_SLE,
156 U8500_I2C_CR_SHIFT_DMA_SLE, 0);
158 /* Disable interrupts */
159 writel(0, &i2c_regs->imscr);
161 /* Configure bus master mode */
162 i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_OM, U8500_I2C_CR_SHIFT_OM,
163 U8500_I2C_BUS_MASTER_MODE);
164 /* Set FIFO threshold values */
165 writel(TX_FIFO_THRESHOLD, &i2c_regs->tftr);
166 writel(RX_FIFO_THRESHOLD, &i2c_regs->rftr);
168 /* Enable the I2C Controller */
169 i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_PE);
171 bus_initialized[i2c_bus_num] = 1;
176 * loop_till_bit_clear - polls on a bit till it clears
177 * ioreg: register where you want to check status
178 * mask: bit mask for the bit you wish to check
179 * timeout: timeout in ticks/s
181 static int loop_till_bit_clear(void *io_reg, u32 mask, unsigned long timeout)
183 unsigned long timebase = get_timer(0);
186 if ((readl(io_reg) & mask) == 0x0UL)
188 } while (get_timer(timebase) < timeout);
190 debug("loop_till_bit_clear timed out\n");
195 * loop_till_bit_set - polls on a bit till it is set.
196 * ioreg: register where you want to check status
197 * mask: bit mask for the bit you wish to check
198 * timeout: timeout in ticks/s
200 static int loop_till_bit_set(void *io_reg, u32 mask, unsigned long timeout)
202 unsigned long timebase = get_timer(0);
205 if ((readl(io_reg) & mask) != 0x0UL)
207 } while (get_timer(timebase) < timeout);
209 debug("loop_till_bit_set timed out\n");
214 * flush_fifo - flush the I2C TX and RX FIFOs
216 static void flush_fifo(struct u8500_i2c_regs *i2c_regs)
218 int counter = U8500_I2C_FIFO_FLUSH_COUNTER;
221 i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FTX);
223 i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FRX);
225 if (!(readl(&i2c_regs->cr) &
226 (U8500_I2C_CR_FTX | U8500_I2C_CR_FRX)))
233 static void print_abort_reason(struct u8500_i2c_regs *i2c_regs)
237 printf("abort: risr %08x, sr %08x\n", i2c_regs->risr, i2c_regs->sr);
238 cause = (readl(&i2c_regs->sr) & U8500_I2C_SR_CAUSE) >>
239 U8500_I2C_SR_SHIFT_CAUSE;
241 case U8500_I2C_NACK_ADDR:
242 printf("No Ack received after Slave Address xmission\n");
244 case U8500_I2C_NACK_DATA:
245 printf("Valid for MASTER_WRITE: No Ack received "
246 "during data phase\n");
248 case U8500_I2C_ACK_MCODE:
249 printf("Master recv ack after xmission of master code"
252 case U8500_I2C_ARB_LOST:
253 printf("Master Lost arbitration\n");
255 case U8500_I2C_BERR_START:
256 printf("Slave restarts\n");
258 case U8500_I2C_BERR_STOP:
259 printf("Slave reset\n");
262 printf("Overflow\n");
265 printf("Unknown error type\n");
271 * i2c_abort - called when a I2C transaction failed
273 static void i2c_abort(struct u8500_i2c_regs *i2c_regs)
276 print_abort_reason(i2c_regs);
278 /* flush RX and TX fifos */
279 flush_fifo(i2c_regs);
281 /* Acknowledge the Master Transaction Done */
282 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
284 /* Acknowledge the Master Transaction Done Without Stop */
285 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
287 i2c_init(i2c_bus_speed[i2c_bus_num], CONFIG_SYS_I2C_SLAVE);
291 * write addr, alias index, to I2C bus.
293 static int i2c_write_addr(struct u8500_i2c_regs *i2c_regs, uint addr, int alen)
296 /* Wait until the Tx Fifo is not full */
297 if (loop_till_bit_clear((void *)&i2c_regs->risr,
299 U8500_I2C_ENDAD_COUNTER)) {
305 writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->tfr);
312 * Internal simplified read function:
313 * i2c_regs: Pointer to I2C registers for current bus
314 * chip: I2C chip address, range 0..127
315 * addr: Memory (register) address within the chip
316 * alen: Number of bytes to use for addr (typically 1, 2 for larger
317 * memories, 0 for register type devices with only one register)
318 * value: Where to put the data
320 * Returns: 0 on success, not 0 on failure
322 static int i2c_read_byte(struct u8500_i2c_regs *i2c_regs, uchar chip,
323 uint addr, int alen, uchar *value)
327 /* Set the address mode to 7 bit */
328 WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
330 /* Store the slave address in the master control register */
331 WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip);
334 /* Master write operation */
335 mcr &= ~(U8500_I2C_MCR_OP);
337 /* Configure the Frame length to one byte */
338 WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH,
339 U8500_I2C_MCR_SHIFT_LENGTH, 1);
341 /* Repeated start, no stop */
342 mcr &= ~(U8500_I2C_MCR_STOP);
344 /* Write Master Control Register */
345 writel(mcr, &i2c_regs->mcr);
347 /* send addr/index */
348 if (i2c_write_addr(i2c_regs, addr, alen) != 0)
351 /* Check for the Master Transaction Done Without Stop */
352 if (loop_till_bit_set((void *)&i2c_regs->risr,
354 U8500_I2C_ENDAD_COUNTER)) {
358 /* Acknowledge the Master Transaction Done Without Stop */
359 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
362 /* Master control configuration for read operation */
363 mcr |= U8500_I2C_MCR_OP;
365 /* Configure the STOP condition, we read only one byte */
366 mcr |= U8500_I2C_MCR_STOP;
368 /* Set the frame length to one byte, we support only 1 byte reads */
369 WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1);
371 i2c_write_field(&i2c_regs->mcr, U8500_I2C_MCR_LENGTH_STOP_OP,
372 U8500_I2C_MCR_SHIFT_LENGTH_STOP_OP, mcr);
375 * receive_data_polling
378 /* Wait until the Rx FIFO is not empty */
379 if (loop_till_bit_clear((void *)&i2c_regs->risr,
381 U8500_I2C_ENDAD_COUNTER))
384 /* Read the data byte from Rx FIFO */
385 *value = readb(&i2c_regs->rfr);
387 /* Wait until the work is done */
388 if (loop_till_bit_set((void *)&i2c_regs->risr, U8500_I2C_INT_MTD,
389 U8500_I2C_ENDAD_COUNTER))
392 /* Acknowledge the Master Transaction Done */
393 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
395 /* If MTD is set, Master Transaction Done Without Stop is set too */
396 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
402 * Internal simplified write function:
403 * i2c_regs: Pointer to I2C registers for current bus
404 * chip: I2C chip address, range 0..127
405 * addr: Memory (register) address within the chip
406 * alen: Number of bytes to use for addr (typically 1, 2 for larger
407 * memories, 0 for register type devices with only one register)
408 * data: Where to read the data
409 * len: How many bytes to write
411 * Returns: 0 on success, not 0 on failure
413 static int __i2c_write(struct u8500_i2c_regs *i2c_regs, u8 chip, uint addr,
414 int alen, u8 *data, int len)
419 /* Set the address mode to 7 bit */
420 WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
422 /* Store the slave address in the master control register */
423 WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip);
425 /* Write operation */
426 mcr &= ~(U8500_I2C_MCR_OP);
428 /* Current transaction is terminated by STOP condition */
429 mcr |= U8500_I2C_MCR_STOP;
431 /* Frame length: addr byte + len */
432 WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH,
435 /* Write MCR register */
436 writel(mcr, &i2c_regs->mcr);
438 if (i2c_write_addr(i2c_regs, addr, alen) != 0)
441 for (i = 0; i < len; i++) {
442 /* Wait until the Tx FIFO is not full */
443 if (loop_till_bit_clear((void *)&i2c_regs->risr,
445 U8500_I2C_ENDAD_COUNTER))
448 /* it is a 32 bit register with upper 24 reserved R/O */
449 writeb(data[i], &i2c_regs->tfr);
452 /* Check for Master Transaction Done */
453 if (loop_till_bit_set((void *)&i2c_regs->risr,
455 U8500_I2C_ENDAD_COUNTER)) {
456 printf("i2c_write_byte error2: risr %08x\n",
461 /* Acknowledge Master Transaction Done */
462 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
464 /* Acknowledge Master Transaction Done Without Stop */
465 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
471 * Probe the given I2C chip address. Returns 0 if a chip responded,
474 int i2c_probe(uchar chip)
477 struct u8500_i2c_regs *i2c_regs;
479 if (chip == CONFIG_SYS_I2C_SLAVE)
482 i2c_regs = i2c_dev[i2c_bus_num];
484 /* Set the address mode to 7 bit */
485 WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
487 /* Store the slave address in the master control register */
488 WRITE_FIELD(mcr, U8500_I2C_MCR_A10, U8500_I2C_MCR_SHIFT_A7, chip);
491 mcr |= U8500_I2C_MCR_OP;
493 /* Set the frame length to one byte */
494 WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1);
496 /* Current transaction is terminated by STOP condition */
497 mcr |= U8500_I2C_MCR_STOP;
499 /* Write MCR register */
500 writel(mcr, &i2c_regs->mcr);
502 /* Wait until the Rx Fifo is not empty */
503 if (loop_till_bit_clear((void *)&i2c_regs->risr,
505 U8500_I2C_ENDAD_COUNTER)) {
510 flush_fifo(i2c_regs);
512 /* Acknowledge the Master Transaction Done */
513 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
515 /* Acknowledge the Master Transaction Done Without Stop */
516 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
522 * Read/Write interface:
523 * chip: I2C chip address, range 0..127
524 * addr: Memory (register) address within the chip
525 * alen: Number of bytes to use for addr (typically 1, 2 for larger
526 * memories, 0 for register type devices with only one
528 * buffer: Where to read/write the data
529 * len: How many bytes to read/write
531 * Returns: 0 on success, not 0 on failure
533 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
537 struct u8500_i2c_regs *i2c_regs;
540 debug("I2C read: addr len %d not supported\n", alen);
544 i2c_regs = i2c_dev[i2c_bus_num];
546 for (i = 0; i < len; i++) {
547 rc = i2c_read_byte(i2c_regs, chip, addr + i, alen, &buffer[i]);
549 debug("I2C read: I/O error: %d\n", rc);
558 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
561 struct u8500_i2c_regs *i2c_regs;
562 i2c_regs = i2c_dev[i2c_bus_num];
564 rc = __i2c_write(i2c_regs, chip, addr, alen, buffer,
567 debug("I2C write: I/O error\n");
574 int i2c_set_bus_num(unsigned int bus)
576 if (bus > ARRAY_SIZE(i2c_dev) - 1) {
577 debug("i2c_set_bus_num: only up to bus %d supported\n",
578 ARRAY_SIZE(i2c_dev)-1);
584 if (!bus_initialized[i2c_bus_num])
585 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
590 int i2c_set_bus_speed(unsigned int speed)
593 if (speed > U8500_I2C_MAX_STANDARD_SCL) {
594 debug("i2c_set_bus_speed: only up to %d supported\n",
595 U8500_I2C_MAX_STANDARD_SCL);
599 /* sets as side effect i2c_bus_speed[i2c_bus_num] */
600 i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
605 unsigned int i2c_get_bus_num(void)
610 unsigned int i2c_get_bus_speed(void)
612 return i2c_bus_speed[i2c_bus_num];