2 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
3 * Copyright (c) 2010-2011 NVIDIA Corporation
4 * NVIDIA Corporation <www.nvidia.com>
6 * SPDX-License-Identifier: GPL-2.0+
15 #ifdef CONFIG_TEGRA186
19 #include <asm/arch/clock.h>
20 #include <asm/arch/funcmux.h>
21 #include <asm/arch/pinmux.h>
22 #include <asm/arch-tegra/clk_rst.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch-tegra/tegra_i2c.h>
28 * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
29 * should not be present. These are needed because newer Tegra SoCs support
30 * only the standard clock/reset APIs, whereas older Tegra SoCs support only
31 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
32 * fixed to implement the standard APIs, and all drivers converted to solely
33 * use the new standard APIs, with no ifdefs.
36 DECLARE_GLOBAL_DATA_PTR;
44 /* Information about i2c controller */
47 #ifdef CONFIG_TEGRA186
48 struct reset_ctl reset_ctl;
51 enum periph_id periph_id;
55 struct i2c_control *control;
56 struct i2c_ctlr *regs;
58 int inited; /* bus is inited */
61 static void set_packet_mode(struct i2c_bus *i2c_bus)
65 config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
67 if (i2c_bus->type == TYPE_DVC) {
68 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
70 writel(config, &dvc->cnfg);
72 writel(config, &i2c_bus->regs->cnfg);
74 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
75 * issues, i.e., some slaves may be wrongly detected.
77 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
81 static void i2c_reset_controller(struct i2c_bus *i2c_bus)
83 /* Reset I2C controller. */
84 #ifdef CONFIG_TEGRA186
85 reset_assert(&i2c_bus->reset_ctl);
87 reset_deassert(&i2c_bus->reset_ctl);
90 reset_periph(i2c_bus->periph_id, 1);
93 /* re-program config register to packet mode */
94 set_packet_mode(i2c_bus);
97 #ifdef CONFIG_TEGRA186
98 static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
102 ret = reset_assert(&i2c_bus->reset_ctl);
105 ret = clk_enable(&i2c_bus->clk);
108 ret = clk_set_rate(&i2c_bus->clk, rate);
109 if (IS_ERR_VALUE(ret))
111 ret = reset_deassert(&i2c_bus->reset_ctl);
119 static void i2c_init_controller(struct i2c_bus *i2c_bus)
123 debug("%s: speed=%d\n", __func__, i2c_bus->speed);
125 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
126 * here, in section 23.3.1, but in fact we seem to need a factor of
127 * 16 to get the right frequency.
129 #ifdef CONFIG_TEGRA186
130 i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);
132 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
133 i2c_bus->speed * 2 * 8);
136 if (i2c_bus->type == TYPE_114) {
138 * T114 I2C went to a single clock source for standard/fast and
139 * HS clock speeds. The new clock rate setting calculation is:
140 * SCL = CLK_SOURCE.I2C /
141 * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
142 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
144 * NOTE: We do this here, after the initial clock/pll start,
145 * because if we read the clk_div reg before the controller
146 * is running, we hang, and we need it for the new calc.
148 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
149 unsigned rate = CLK_MULT_STD_FAST_MODE *
150 (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2;
151 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
152 clk_div_stdfst_mode);
154 #ifdef CONFIG_TEGRA186
155 i2c_init_clock(i2c_bus, rate);
157 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
162 /* Reset I2C controller. */
163 i2c_reset_controller(i2c_bus);
165 /* Configure I2C controller. */
166 if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */
167 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
169 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
172 #ifndef CONFIG_TEGRA186
173 funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config);
177 static void send_packet_headers(
178 struct i2c_bus *i2c_bus,
179 struct i2c_trans_info *trans,
181 bool end_with_repeated_start)
185 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
186 data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
187 data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
188 data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
189 writel(data, &i2c_bus->control->tx_fifo);
190 debug("pkt header 1 sent (0x%x)\n", data);
192 /* prepare header2 */
193 data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
194 writel(data, &i2c_bus->control->tx_fifo);
195 debug("pkt header 2 sent (0x%x)\n", data);
197 /* prepare IO specific header: configure the slave address */
198 data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
200 /* Enable Read if it is not a write transaction */
201 if (!(trans->flags & I2C_IS_WRITE))
202 data |= PKT_HDR3_READ_MODE_MASK;
203 if (end_with_repeated_start)
204 data |= PKT_HDR3_REPEAT_START_MASK;
206 /* Write I2C specific header */
207 writel(data, &i2c_bus->control->tx_fifo);
208 debug("pkt header 3 sent (0x%x)\n", data);
211 static int wait_for_tx_fifo_empty(struct i2c_control *control)
214 int timeout_us = I2C_TIMEOUT_USEC;
216 while (timeout_us >= 0) {
217 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
218 >> TX_FIFO_EMPTY_CNT_SHIFT;
219 if (count == I2C_FIFO_DEPTH)
228 static int wait_for_rx_fifo_notempty(struct i2c_control *control)
231 int timeout_us = I2C_TIMEOUT_USEC;
233 while (timeout_us >= 0) {
234 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
235 >> TX_FIFO_FULL_CNT_SHIFT;
245 static int wait_for_transfer_complete(struct i2c_control *control)
248 int timeout_us = I2C_TIMEOUT_USEC;
250 while (timeout_us >= 0) {
251 int_status = readl(&control->int_status);
252 if (int_status & I2C_INT_NO_ACK_MASK)
254 if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
256 if (int_status & I2C_INT_XFER_COMPLETE_MASK)
266 static int send_recv_packets(struct i2c_bus *i2c_bus,
267 struct i2c_trans_info *trans)
269 struct i2c_control *control = i2c_bus->control;
276 int is_write = trans->flags & I2C_IS_WRITE;
278 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
279 int_status = readl(&control->int_status);
280 writel(int_status, &control->int_status);
282 send_packet_headers(i2c_bus, trans, 1,
283 trans->flags & I2C_USE_REPEATED_START);
285 words = DIV_ROUND_UP(trans->num_bytes, 4);
286 last_bytes = trans->num_bytes & 3;
290 u32 *wptr = (u32 *)dptr;
293 /* deal with word alignment */
294 if ((words == 1) && last_bytes) {
296 memcpy(&local, dptr, last_bytes);
297 } else if ((unsigned long)dptr & 3) {
298 memcpy(&local, dptr, sizeof(u32));
302 writel(local, &control->tx_fifo);
303 debug("pkt data sent (0x%x)\n", local);
304 if (!wait_for_tx_fifo_empty(control)) {
309 if (!wait_for_rx_fifo_notempty(control)) {
314 * for the last word, we read into our local buffer,
315 * in case that caller did not provide enough buffer.
317 local = readl(&control->rx_fifo);
318 if ((words == 1) && last_bytes)
319 memcpy(dptr, (char *)&local, last_bytes);
320 else if ((unsigned long)dptr & 3)
321 memcpy(dptr, &local, sizeof(u32));
324 debug("pkt data received (0x%x)\n", local);
330 if (wait_for_transfer_complete(control)) {
336 /* error, reset the controller. */
337 i2c_reset_controller(i2c_bus);
342 static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
343 u32 len, bool end_with_repeated_start)
346 struct i2c_trans_info trans_info;
348 trans_info.address = addr;
349 trans_info.buf = data;
350 trans_info.flags = I2C_IS_WRITE;
351 if (end_with_repeated_start)
352 trans_info.flags |= I2C_USE_REPEATED_START;
353 trans_info.num_bytes = len;
354 trans_info.is_10bit_address = 0;
356 error = send_recv_packets(i2c_bus, &trans_info);
358 debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
363 static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
367 struct i2c_trans_info trans_info;
369 trans_info.address = addr | 1;
370 trans_info.buf = data;
371 trans_info.flags = 0;
372 trans_info.num_bytes = len;
373 trans_info.is_10bit_address = 0;
375 error = send_recv_packets(i2c_bus, &trans_info);
377 debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
382 static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
384 struct i2c_bus *i2c_bus = dev_get_priv(dev);
386 i2c_bus->speed = speed;
387 i2c_init_controller(i2c_bus);
392 static int tegra_i2c_probe(struct udevice *dev)
394 struct i2c_bus *i2c_bus = dev_get_priv(dev);
395 #ifdef CONFIG_TEGRA186
398 const void *blob = gd->fdt_blob;
399 int node = dev->of_offset;
403 i2c_bus->id = dev->seq;
404 i2c_bus->type = dev_get_driver_data(dev);
405 i2c_bus->regs = (struct i2c_ctlr *)dev_get_addr(dev);
408 * We don't have a binding for pinmux yet. Leave it out for now. So
409 * far no one needs anything other than the default.
411 #ifdef CONFIG_TEGRA186
412 ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
414 error("reset_get_by_name() failed: %d\n", ret);
417 ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk);
419 error("clk_get_by_name() failed: %d\n", ret);
423 i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
424 i2c_bus->periph_id = clock_decode_periph_id(blob, node);
427 * We can't specify the pinmux config in the fdt, so I2C2 will not
428 * work on Seaboard. It normally has no devices on it anyway.
429 * You could add in this little hack if you need to use it.
430 * The correct solution is a pinmux binding in the fdt.
432 * if (i2c_bus->periph_id == PERIPH_ID_I2C2)
433 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
435 if (i2c_bus->periph_id == -1)
439 is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
442 &((struct dvc_ctlr *)i2c_bus->regs)->control;
444 i2c_bus->control = &i2c_bus->regs->control;
446 i2c_init_controller(i2c_bus);
447 debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
448 is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs,
449 #ifndef CONFIG_TEGRA186
459 /* i2c write version without the register address */
460 static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
461 int len, bool end_with_repeated_start)
465 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
466 debug("write_data: ");
467 /* use rc for counter */
468 for (rc = 0; rc < len; ++rc)
469 debug(" 0x%02x", buffer[rc]);
472 /* Shift 7-bit address over for lower-level i2c functions */
473 rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
474 end_with_repeated_start);
476 debug("i2c_write_data(): rc=%d\n", rc);
481 /* i2c read version without the register address */
482 static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
487 debug("inside i2c_read_data():\n");
488 /* Shift 7-bit address over for lower-level i2c functions */
489 rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
491 debug("i2c_read_data(): rc=%d\n", rc);
495 debug("i2c_read_data: ");
496 /* reuse rc for counter*/
497 for (rc = 0; rc < len; ++rc)
498 debug(" 0x%02x", buffer[rc]);
504 /* Probe to see if a chip is present. */
505 static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
508 struct i2c_bus *i2c_bus = dev_get_priv(bus);
512 /* Shift 7-bit address over for lower-level i2c functions */
513 rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, ®, sizeof(reg),
519 static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
522 struct i2c_bus *i2c_bus = dev_get_priv(bus);
525 debug("i2c_xfer: %d messages\n", nmsgs);
526 for (; nmsgs > 0; nmsgs--, msg++) {
527 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
529 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
530 if (msg->flags & I2C_M_RD) {
531 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
534 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
535 msg->len, next_is_read);
538 debug("i2c_write: error sending\n");
546 int tegra_i2c_get_dvc_bus(struct udevice **busp)
550 for (uclass_first_device(UCLASS_I2C, &bus);
552 uclass_next_device(&bus)) {
553 if (dev_get_driver_data(bus) == TYPE_DVC) {
562 static const struct dm_i2c_ops tegra_i2c_ops = {
563 .xfer = tegra_i2c_xfer,
564 .probe_chip = tegra_i2c_probe_chip,
565 .set_bus_speed = tegra_i2c_set_bus_speed,
568 static const struct udevice_id tegra_i2c_ids[] = {
569 { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
570 { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
571 { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
575 U_BOOT_DRIVER(i2c_tegra) = {
578 .of_match = tegra_i2c_ids,
579 .probe = tegra_i2c_probe,
580 .priv_auto_alloc_size = sizeof(struct i2c_bus),
581 .ops = &tegra_i2c_ops,