drivers/i2c/stm32f7_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 STMicroelectronics
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <i2c.h>
  10 #include <malloc.h>
  11 #include <reset.h>
  12
  13 #include <dm/device.h>
  14 #include <linux/io.h>
  15
  16 /* STM32 I2C registers */
  17 struct stm32_i2c_regs {
  18         u32 cr1;        /* I2C control register 1 */
  19         u32 cr2;        /* I2C control register 2 */
  20         u32 oar1;       /* I2C own address 1 register */
  21         u32 oar2;       /* I2C own address 2 register */
  22         u32 timingr;    /* I2C timing register */
  23         u32 timeoutr;   /* I2C timeout register */
  24         u32 isr;        /* I2C interrupt and status register */
  25         u32 icr;        /* I2C interrupt clear register */
  26         u32 pecr;       /* I2C packet error checking register */
  27         u32 rxdr;       /* I2C receive data register */
  28         u32 txdr;       /* I2C transmit data register */
  29 };
  30
  31 #define STM32_I2C_CR1                           0x00
  32 #define STM32_I2C_CR2                           0x04
  33 #define STM32_I2C_TIMINGR                       0x10
  34 #define STM32_I2C_ISR                           0x18
  35 #define STM32_I2C_ICR                           0x1C
  36 #define STM32_I2C_RXDR                          0x24
  37 #define STM32_I2C_TXDR                          0x28
  38
  39 /* STM32 I2C control 1 */
  40 #define STM32_I2C_CR1_ANFOFF                    BIT(12)
  41 #define STM32_I2C_CR1_ERRIE                     BIT(7)
  42 #define STM32_I2C_CR1_TCIE                      BIT(6)
  43 #define STM32_I2C_CR1_STOPIE                    BIT(5)
  44 #define STM32_I2C_CR1_NACKIE                    BIT(4)
  45 #define STM32_I2C_CR1_ADDRIE                    BIT(3)
  46 #define STM32_I2C_CR1_RXIE                      BIT(2)
  47 #define STM32_I2C_CR1_TXIE                      BIT(1)
  48 #define STM32_I2C_CR1_PE                        BIT(0)
  49
  50 /* STM32 I2C control 2 */
  51 #define STM32_I2C_CR2_AUTOEND                   BIT(25)
  52 #define STM32_I2C_CR2_RELOAD                    BIT(24)
  53 #define STM32_I2C_CR2_NBYTES_MASK               GENMASK(23, 16)
  54 #define STM32_I2C_CR2_NBYTES(n)                 ((n & 0xff) << 16)
  55 #define STM32_I2C_CR2_NACK                      BIT(15)
  56 #define STM32_I2C_CR2_STOP                      BIT(14)
  57 #define STM32_I2C_CR2_START                     BIT(13)
  58 #define STM32_I2C_CR2_HEAD10R                   BIT(12)
  59 #define STM32_I2C_CR2_ADD10                     BIT(11)
  60 #define STM32_I2C_CR2_RD_WRN                    BIT(10)
  61 #define STM32_I2C_CR2_SADD10_MASK               GENMASK(9, 0)
  62 #define STM32_I2C_CR2_SADD10(n)                 (n & STM32_I2C_CR2_SADD10_MASK)
  63 #define STM32_I2C_CR2_SADD7_MASK                GENMASK(7, 1)
  64 #define STM32_I2C_CR2_SADD7(n)                  ((n & 0x7f) << 1)
  65 #define STM32_I2C_CR2_RESET_MASK                (STM32_I2C_CR2_HEAD10R \
  66                                                 | STM32_I2C_CR2_NBYTES_MASK \
  67                                                 | STM32_I2C_CR2_SADD7_MASK \
  68                                                 | STM32_I2C_CR2_RELOAD \
  69                                                 | STM32_I2C_CR2_RD_WRN)
  70
  71 /* STM32 I2C Interrupt Status */
  72 #define STM32_I2C_ISR_BUSY                      BIT(15)
  73 #define STM32_I2C_ISR_ARLO                      BIT(9)
  74 #define STM32_I2C_ISR_BERR                      BIT(8)
  75 #define STM32_I2C_ISR_TCR                       BIT(7)
  76 #define STM32_I2C_ISR_TC                        BIT(6)
  77 #define STM32_I2C_ISR_STOPF                     BIT(5)
  78 #define STM32_I2C_ISR_NACKF                     BIT(4)
  79 #define STM32_I2C_ISR_ADDR                      BIT(3)
  80 #define STM32_I2C_ISR_RXNE                      BIT(2)
  81 #define STM32_I2C_ISR_TXIS                      BIT(1)
  82 #define STM32_I2C_ISR_TXE                       BIT(0)
  83 #define STM32_I2C_ISR_ERRORS                    (STM32_I2C_ISR_BERR \
  84                                                 | STM32_I2C_ISR_ARLO)
  85
  86 /* STM32 I2C Interrupt Clear */
  87 #define STM32_I2C_ICR_ARLOCF                    BIT(9)
  88 #define STM32_I2C_ICR_BERRCF                    BIT(8)
  89 #define STM32_I2C_ICR_STOPCF                    BIT(5)
  90 #define STM32_I2C_ICR_NACKCF                    BIT(4)
  91
  92 /* STM32 I2C Timing */
  93 #define STM32_I2C_TIMINGR_PRESC(n)              ((n & 0xf) << 28)
  94 #define STM32_I2C_TIMINGR_SCLDEL(n)             ((n & 0xf) << 20)
  95 #define STM32_I2C_TIMINGR_SDADEL(n)             ((n & 0xf) << 16)
  96 #define STM32_I2C_TIMINGR_SCLH(n)               ((n & 0xff) << 8)
  97 #define STM32_I2C_TIMINGR_SCLL(n)               (n & 0xff)
  98
  99 #define STM32_I2C_MAX_LEN                       0xff
 100
 101 #define STM32_I2C_DNF_DEFAULT                   0
 102 #define STM32_I2C_DNF_MAX                       16
 103
 104 #define STM32_I2C_ANALOG_FILTER_ENABLE  1
 105 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN       50      /* ns */
 106 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX       260     /* ns */
 107
 108 #define STM32_I2C_RISE_TIME_DEFAULT             25      /* ns */
 109 #define STM32_I2C_FALL_TIME_DEFAULT             10      /* ns */
 110
 111 #define STM32_PRESC_MAX                         BIT(4)
 112 #define STM32_SCLDEL_MAX                        BIT(4)
 113 #define STM32_SDADEL_MAX                        BIT(4)
 114 #define STM32_SCLH_MAX                          BIT(8)
 115 #define STM32_SCLL_MAX                          BIT(8)
 116
 117 #define STM32_NSEC_PER_SEC                      1000000000L
 118
 119 /**
 120  * struct stm32_i2c_spec - private i2c specification timing
 121  * @rate: I2C bus speed (Hz)
 122  * @rate_min: 80% of I2C bus speed (Hz)
 123  * @rate_max: 120% of I2C bus speed (Hz)
 124  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 125  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 126  * @hddat_min: Min data hold time (ns)
 127  * @vddat_max: Max data valid time (ns)
 128  * @sudat_min: Min data setup time (ns)
 129  * @l_min: Min low period of the SCL clock (ns)
 130  * @h_min: Min high period of the SCL clock (ns)
 131  */
 132
 133 struct stm32_i2c_spec {
 134         u32 rate;
 135         u32 rate_min;
 136         u32 rate_max;
 137         u32 fall_max;
 138         u32 rise_max;
 139         u32 hddat_min;
 140         u32 vddat_max;
 141         u32 sudat_min;
 142         u32 l_min;
 143         u32 h_min;
 144 };
 145
 146 /**
 147  * struct stm32_i2c_setup - private I2C timing setup parameters
 148  * @speed: I2C speed mode (standard, Fast Plus)
 149  * @speed_freq: I2C speed frequency  (Hz)
 150  * @clock_src: I2C clock source frequency (Hz)
 151  * @rise_time: Rise time (ns)
 152  * @fall_time: Fall time (ns)
 153  * @dnf: Digital filter coefficient (0-16)
 154  * @analog_filter: Analog filter delay (On/Off)
 155  */
 156 struct stm32_i2c_setup {
 157         enum i2c_speed_mode speed;
 158         u32 speed_freq;
 159         u32 clock_src;
 160         u32 rise_time;
 161         u32 fall_time;
 162         u8 dnf;
 163         bool analog_filter;
 164 };
 165
 166 /**
 167  * struct stm32_i2c_timings - private I2C output parameters
 168  * @prec: Prescaler value
 169  * @scldel: Data setup time
 170  * @sdadel: Data hold time
 171  * @sclh: SCL high period (master mode)
 172  * @sclh: SCL low period (master mode)
 173  */
 174 struct stm32_i2c_timings {
 175         struct list_head node;
 176         u8 presc;
 177         u8 scldel;
 178         u8 sdadel;
 179         u8 sclh;
 180         u8 scll;
 181 };
 182
 183 struct stm32_i2c_priv {
 184         struct stm32_i2c_regs *regs;
 185         struct clk clk;
 186         struct stm32_i2c_setup *setup;
 187         int speed;
 188 };
 189
 190 static const struct stm32_i2c_spec i2c_specs[] = {
 191         [IC_SPEED_MODE_STANDARD] = {
 192                 .rate = I2C_SPEED_STANDARD_RATE,
 193                 .rate_min = 8000,
 194                 .rate_max = 120000,
 195                 .fall_max = 300,
 196                 .rise_max = 1000,
 197                 .hddat_min = 0,
 198                 .vddat_max = 3450,
 199                 .sudat_min = 250,
 200                 .l_min = 4700,
 201                 .h_min = 4000,
 202         },
 203         [IC_SPEED_MODE_FAST] = {
 204                 .rate = I2C_SPEED_FAST_RATE,
 205                 .rate_min = 320000,
 206                 .rate_max = 480000,
 207                 .fall_max = 300,
 208                 .rise_max = 300,
 209                 .hddat_min = 0,
 210                 .vddat_max = 900,
 211                 .sudat_min = 100,
 212                 .l_min = 1300,
 213                 .h_min = 600,
 214         },
 215         [IC_SPEED_MODE_FAST_PLUS] = {
 216                 .rate = I2C_SPEED_FAST_PLUS_RATE,
 217                 .rate_min = 800000,
 218                 .rate_max = 1200000,
 219                 .fall_max = 100,
 220                 .rise_max = 120,
 221                 .hddat_min = 0,
 222                 .vddat_max = 450,
 223                 .sudat_min = 50,
 224                 .l_min = 500,
 225                 .h_min = 260,
 226         },
 227 };
 228
 229 static const struct stm32_i2c_setup stm32f7_setup = {
 230         .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
 231         .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
 232         .dnf = STM32_I2C_DNF_DEFAULT,
 233         .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
 234 };
 235
 236 static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
 237 {
 238         struct stm32_i2c_regs *regs = i2c_priv->regs;
 239         u32 status = readl(&regs->isr);
 240
 241         if (status & STM32_I2C_ISR_BUSY)
 242                 return -EBUSY;
 243
 244         return 0;
 245 }
 246
 247 static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
 248                                     struct i2c_msg *msg, bool stop)
 249 {
 250         struct stm32_i2c_regs *regs = i2c_priv->regs;
 251         u32 cr2 = readl(&regs->cr2);
 252
 253         /* Set transfer direction */
 254         cr2 &= ~STM32_I2C_CR2_RD_WRN;
 255         if (msg->flags & I2C_M_RD)
 256                 cr2 |= STM32_I2C_CR2_RD_WRN;
 257
 258         /* Set slave address */
 259         cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
 260         if (msg->flags & I2C_M_TEN) {
 261                 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
 262                 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
 263                 cr2 |= STM32_I2C_CR2_ADD10;
 264         } else {
 265                 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
 266                 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
 267         }
 268
 269         /* Set nb bytes to transfer and reload or autoend bits */
 270         cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
 271                  STM32_I2C_CR2_AUTOEND);
 272         if (msg->len > STM32_I2C_MAX_LEN) {
 273                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 274                 cr2 |= STM32_I2C_CR2_RELOAD;
 275         } else {
 276                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 277         }
 278
 279         /* Write configurations register */
 280         writel(cr2, &regs->cr2);
 281
 282         /* START/ReSTART generation */
 283         setbits_le32(&regs->cr2, STM32_I2C_CR2_START);
 284 }
 285
 286 /*
 287  * RELOAD mode must be selected if total number of data bytes to be
 288  * sent is greater than MAX_LEN
 289  */
 290
 291 static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
 292                                     struct i2c_msg *msg, bool stop)
 293 {
 294         struct stm32_i2c_regs *regs = i2c_priv->regs;
 295         u32 cr2 = readl(&regs->cr2);
 296
 297         cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
 298
 299         if (msg->len > STM32_I2C_MAX_LEN) {
 300                 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
 301         } else {
 302                 cr2 &= ~STM32_I2C_CR2_RELOAD;
 303                 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
 304         }
 305
 306         writel(cr2, &regs->cr2);
 307 }
 308
 309 static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
 310                                 u32 flags, u32 *status)
 311 {
 312         struct stm32_i2c_regs *regs = i2c_priv->regs;
 313         u32 time_start = get_timer(0);
 314
 315         *status = readl(&regs->isr);
 316         while (!(*status & flags)) {
 317                 if (get_timer(time_start) > CONFIG_SYS_HZ) {
 318                         debug("%s: i2c timeout\n", __func__);
 319                         return -ETIMEDOUT;
 320                 }
 321
 322                 *status = readl(&regs->isr);
 323         }
 324
 325         return 0;
 326 }
 327
 328 static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
 329 {
 330         struct stm32_i2c_regs *regs = i2c_priv->regs;
 331         u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
 332                    STM32_I2C_ISR_STOPF;
 333         u32 status;
 334         int ret;
 335
 336         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 337         if (ret)
 338                 return ret;
 339
 340         if (status & STM32_I2C_ISR_BERR) {
 341                 debug("%s: Bus error\n", __func__);
 342
 343                 /* Clear BERR flag */
 344                 setbits_le32(&regs->icr, STM32_I2C_ICR_BERRCF);
 345
 346                 return -EIO;
 347         }
 348
 349         if (status & STM32_I2C_ISR_ARLO) {
 350                 debug("%s: Arbitration lost\n", __func__);
 351
 352                 /* Clear ARLO flag */
 353                 setbits_le32(&regs->icr, STM32_I2C_ICR_ARLOCF);
 354
 355                 return -EAGAIN;
 356         }
 357
 358         if (status & STM32_I2C_ISR_NACKF) {
 359                 debug("%s: Receive NACK\n", __func__);
 360
 361                 /* Clear NACK flag */
 362                 setbits_le32(&regs->icr, STM32_I2C_ICR_NACKCF);
 363
 364                 /* Wait until STOPF flag is set */
 365                 mask = STM32_I2C_ISR_STOPF;
 366                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 367                 if (ret)
 368                         return ret;
 369
 370                 ret = -EIO;
 371         }
 372
 373         if (status & STM32_I2C_ISR_STOPF) {
 374                 /* Clear STOP flag */
 375                 setbits_le32(&regs->icr, STM32_I2C_ICR_STOPCF);
 376
 377                 /* Clear control register 2 */
 378                 setbits_le32(&regs->cr2, STM32_I2C_CR2_RESET_MASK);
 379         }
 380
 381         return ret;
 382 }
 383
 384 static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
 385                                   struct i2c_msg *msg, bool stop)
 386 {
 387         struct stm32_i2c_regs *regs = i2c_priv->regs;
 388         u32 status;
 389         u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 390                    STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 391         int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 392                           STM32_I2C_MAX_LEN : msg->len;
 393         int ret = 0;
 394
 395         /* Add errors */
 396         mask |= STM32_I2C_ISR_ERRORS;
 397
 398         stm32_i2c_message_start(i2c_priv, msg, stop);
 399
 400         while (msg->len) {
 401                 /*
 402                  * Wait until TXIS/NACKF/BERR/ARLO flags or
 403                  * RXNE/BERR/ARLO flags are set
 404                  */
 405                 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 406                 if (ret)
 407                         break;
 408
 409                 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
 410                         break;
 411
 412                 if (status & STM32_I2C_ISR_RXNE) {
 413                         *msg->buf++ = readb(&regs->rxdr);
 414                         msg->len--;
 415                         bytes_to_rw--;
 416                 }
 417
 418                 if (status & STM32_I2C_ISR_TXIS) {
 419                         writeb(*msg->buf++, &regs->txdr);
 420                         msg->len--;
 421                         bytes_to_rw--;
 422                 }
 423
 424                 if (!bytes_to_rw && msg->len) {
 425                         /* Wait until TCR flag is set */
 426                         mask = STM32_I2C_ISR_TCR;
 427                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 428                         if (ret)
 429                                 break;
 430
 431                         bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
 432                                       STM32_I2C_MAX_LEN : msg->len;
 433                         mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
 434                                STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
 435
 436                         stm32_i2c_handle_reload(i2c_priv, msg, stop);
 437                 } else if (!bytes_to_rw) {
 438                         /* Wait until TC flag is set */
 439                         mask = STM32_I2C_ISR_TC;
 440                         ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
 441                         if (ret)
 442                                 break;
 443
 444                         if (!stop)
 445                                 /* Message sent, new message has to be sent */
 446                                 return 0;
 447                 }
 448         }
 449
 450         /* End of transfer, send stop condition */
 451         mask = STM32_I2C_CR2_STOP;
 452         setbits_le32(&regs->cr2, mask);
 453
 454         return stm32_i2c_check_end_of_message(i2c_priv);
 455 }
 456
 457 static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 458                           int nmsgs)
 459 {
 460         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 461         int ret;
 462
 463         ret = stm32_i2c_check_device_busy(i2c_priv);
 464         if (ret)
 465                 return ret;
 466
 467         for (; nmsgs > 0; nmsgs--, msg++) {
 468                 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
 469                 if (ret)
 470                         return ret;
 471         }
 472
 473         return 0;
 474 }
 475
 476 static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
 477                                        struct list_head *solutions)
 478 {
 479         struct stm32_i2c_timings *v;
 480         u32 p_prev = STM32_PRESC_MAX;
 481         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 482                                        setup->clock_src);
 483         u32 af_delay_min, af_delay_max;
 484         u16 p, l, a;
 485         int sdadel_min, sdadel_max, scldel_min;
 486         int ret = 0;
 487
 488         af_delay_min = setup->analog_filter ?
 489                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 490         af_delay_max = setup->analog_filter ?
 491                        STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
 492
 493         sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
 494                      af_delay_min - (setup->dnf + 3) * i2cclk;
 495
 496         sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
 497                      af_delay_max - (setup->dnf + 4) * i2cclk;
 498
 499         scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
 500
 501         if (sdadel_min < 0)
 502                 sdadel_min = 0;
 503         if (sdadel_max < 0)
 504                 sdadel_max = 0;
 505
 506         debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
 507               sdadel_min, sdadel_max, scldel_min);
 508
 509         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 510         for (p = 0; p < STM32_PRESC_MAX; p++) {
 511                 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
 512                         int scldel = (l + 1) * (p + 1) * i2cclk;
 513
 514                         if (scldel < scldel_min)
 515                                 continue;
 516
 517                         for (a = 0; a < STM32_SDADEL_MAX; a++) {
 518                                 int sdadel = (a * (p + 1) + 1) * i2cclk;
 519
 520                                 if (((sdadel >= sdadel_min) &&
 521                                      (sdadel <= sdadel_max)) &&
 522                                     (p != p_prev)) {
 523                                         v = calloc(1, sizeof(*v));
 524                                         if (!v)
 525                                                 return -ENOMEM;
 526
 527                                         v->presc = p;
 528                                         v->scldel = l;
 529                                         v->sdadel = a;
 530                                         p_prev = p;
 531
 532                                         list_add_tail(&v->node, solutions);
 533                                         break;
 534                                 }
 535                         }
 536
 537                         if (p_prev == p)
 538                                 break;
 539                 }
 540         }
 541
 542         if (list_empty(solutions)) {
 543                 pr_err("%s: no Prescaler solution\n", __func__);
 544                 ret = -EPERM;
 545         }
 546
 547         return ret;
 548 }
 549
 550 static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
 551                                      struct list_head *solutions,
 552                                      struct stm32_i2c_timings *s)
 553 {
 554         struct stm32_i2c_timings *v;
 555         u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 556                                        setup->speed_freq);
 557         u32 clk_error_prev = i2cbus;
 558         u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
 559                                        setup->clock_src);
 560         u32 clk_min, clk_max;
 561         u32 af_delay_min;
 562         u32 dnf_delay;
 563         u32 tsync;
 564         u16 l, h;
 565         bool sol_found = false;
 566         int ret = 0;
 567
 568         af_delay_min = setup->analog_filter ?
 569                        STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
 570         dnf_delay = setup->dnf * i2cclk;
 571
 572         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 573         clk_max = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
 574         clk_min = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
 575
 576         /*
 577          * Among Prescaler possibilities discovered above figures out SCL Low
 578          * and High Period. Provided:
 579          * - SCL Low Period has to be higher than Low Period of the SCL Clock
 580          *   defined by I2C Specification. I2C Clock has to be lower than
 581          *   (SCL Low Period - Analog/Digital filters) / 4.
 582          * - SCL High Period has to be lower than High Period of the SCL Clock
 583          *   defined by I2C Specification
 584          * - I2C Clock has to be lower than SCL High Period
 585          */
 586         list_for_each_entry(v, solutions, node) {
 587                 u32 prescaler = (v->presc + 1) * i2cclk;
 588
 589                 for (l = 0; l < STM32_SCLL_MAX; l++) {
 590                         u32 tscl_l = (l + 1) * prescaler + tsync;
 591
 592                         if ((tscl_l < i2c_specs[setup->speed].l_min) ||
 593                             (i2cclk >=
 594                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 595                                 continue;
 596                         }
 597
 598                         for (h = 0; h < STM32_SCLH_MAX; h++) {
 599                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 600                                 u32 tscl = tscl_l + tscl_h +
 601                                            setup->rise_time + setup->fall_time;
 602
 603                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 604                                     (tscl_h >= i2c_specs[setup->speed].h_min) &&
 605                                     (i2cclk < tscl_h)) {
 606                                         u32 clk_error;
 607
 608                                         if (tscl > i2cbus)
 609                                                 clk_error = tscl - i2cbus;
 610                                         else
 611                                                 clk_error = i2cbus - tscl;
 612
 613                                         if (clk_error < clk_error_prev) {
 614                                                 clk_error_prev = clk_error;
 615                                                 v->scll = l;
 616                                                 v->sclh = h;
 617                                                 sol_found = true;
 618                                                 memcpy(s, v, sizeof(*s));
 619                                         }
 620                                 }
 621                         }
 622                 }
 623         }
 624
 625         if (!sol_found) {
 626                 pr_err("%s: no solution at all\n", __func__);
 627                 ret = -EPERM;
 628         }
 629
 630         return ret;
 631 }
 632
 633 static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
 634                                     struct stm32_i2c_setup *setup,
 635                                     struct stm32_i2c_timings *output)
 636 {
 637         struct stm32_i2c_timings *v, *_v;
 638         struct list_head solutions;
 639         int ret;
 640
 641         if (setup->speed >= ARRAY_SIZE(i2c_specs)) {
 642                 pr_err("%s: speed out of bound {%d/%d}\n", __func__,
 643                        setup->speed, ARRAY_SIZE(i2c_specs) - 1);
 644                 return -EINVAL;
 645         }
 646
 647         if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
 648             (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
 649                 pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 650                        __func__,
 651                        setup->rise_time, i2c_specs[setup->speed].rise_max,
 652                        setup->fall_time, i2c_specs[setup->speed].fall_max);
 653                 return -EINVAL;
 654         }
 655
 656         if (setup->dnf > STM32_I2C_DNF_MAX) {
 657                 pr_err("%s: DNF out of bound %d/%d\n", __func__,
 658                        setup->dnf, STM32_I2C_DNF_MAX);
 659                 return -EINVAL;
 660         }
 661
 662         if (setup->speed_freq > i2c_specs[setup->speed].rate) {
 663                 pr_err("%s: Freq {%d/%d}\n", __func__,
 664                        setup->speed_freq, i2c_specs[setup->speed].rate);
 665                 return -EINVAL;
 666         }
 667
 668         INIT_LIST_HEAD(&solutions);
 669         ret = stm32_i2c_compute_solutions(setup, &solutions);
 670         if (ret)
 671                 goto exit;
 672
 673         ret = stm32_i2c_choose_solution(setup, &solutions, output);
 674         if (ret)
 675                 goto exit;
 676
 677         debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 678               __func__, output->presc,
 679               output->scldel, output->sdadel,
 680               output->scll, output->sclh);
 681
 682 exit:
 683         /* Release list and memory */
 684         list_for_each_entry_safe(v, _v, &solutions, node) {
 685                 list_del(&v->node);
 686                 free(v);
 687         }
 688
 689         return ret;
 690 }
 691
 692 static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
 693                                   struct stm32_i2c_timings *timing)
 694 {
 695         struct stm32_i2c_setup *setup = i2c_priv->setup;
 696         int ret = 0;
 697
 698         setup->speed = i2c_priv->speed;
 699         setup->speed_freq = i2c_specs[setup->speed].rate;
 700         setup->clock_src = clk_get_rate(&i2c_priv->clk);
 701
 702         if (!setup->clock_src) {
 703                 pr_err("%s: clock rate is 0\n", __func__);
 704                 return -EINVAL;
 705         }
 706
 707         do {
 708                 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
 709                 if (ret) {
 710                         debug("%s: failed to compute I2C timings.\n",
 711                               __func__);
 712                         if (i2c_priv->speed > IC_SPEED_MODE_STANDARD) {
 713                                 i2c_priv->speed--;
 714                                 setup->speed = i2c_priv->speed;
 715                                 setup->speed_freq =
 716                                         i2c_specs[setup->speed].rate;
 717                                 debug("%s: downgrade I2C Speed Freq to (%i)\n",
 718                                       __func__, i2c_specs[setup->speed].rate);
 719                         } else {
 720                                 break;
 721                         }
 722                 }
 723         } while (ret);
 724
 725         if (ret) {
 726                 pr_err("%s: impossible to compute I2C timings.\n", __func__);
 727                 return ret;
 728         }
 729
 730         debug("%s: I2C Speed(%i), Freq(%i), Clk Source(%i)\n", __func__,
 731               setup->speed, setup->speed_freq, setup->clock_src);
 732         debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
 733               setup->rise_time, setup->fall_time);
 734         debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
 735               setup->analog_filter ? "On" : "Off", setup->dnf);
 736
 737         return 0;
 738 }
 739
 740 static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
 741 {
 742         struct stm32_i2c_regs *regs = i2c_priv->regs;
 743         struct stm32_i2c_timings t;
 744         int ret;
 745         u32 timing = 0;
 746
 747         ret = stm32_i2c_setup_timing(i2c_priv, &t);
 748         if (ret)
 749                 return ret;
 750
 751         /* Disable I2C */
 752         clrbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 753
 754         /* Timing settings */
 755         timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
 756         timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
 757         timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
 758         timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
 759         timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
 760         writel(timing, &regs->timingr);
 761
 762         /* Enable I2C */
 763         if (i2c_priv->setup->analog_filter)
 764                 clrbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 765         else
 766                 setbits_le32(&regs->cr1, STM32_I2C_CR1_ANFOFF);
 767         setbits_le32(&regs->cr1, STM32_I2C_CR1_PE);
 768
 769         return 0;
 770 }
 771
 772 static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 773 {
 774         struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
 775
 776         switch (speed) {
 777         case I2C_SPEED_STANDARD_RATE:
 778                 i2c_priv->speed = IC_SPEED_MODE_STANDARD;
 779                 break;
 780         case I2C_SPEED_FAST_RATE:
 781                 i2c_priv->speed = IC_SPEED_MODE_FAST;
 782                 break;
 783         case I2C_SPEED_FAST_PLUS_RATE:
 784                 i2c_priv->speed = IC_SPEED_MODE_FAST_PLUS;
 785                 break;
 786         default:
 787                 debug("%s: Speed %d not supported\n", __func__, speed);
 788                 return -EINVAL;
 789         }
 790
 791         return stm32_i2c_hw_config(i2c_priv);
 792 }
 793
 794 static int stm32_i2c_probe(struct udevice *dev)
 795 {
 796         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 797         struct reset_ctl reset_ctl;
 798         fdt_addr_t addr;
 799         int ret;
 800
 801         addr = dev_read_addr(dev);
 802         if (addr == FDT_ADDR_T_NONE)
 803                 return -EINVAL;
 804
 805         i2c_priv->regs = (struct stm32_i2c_regs *)addr;
 806
 807         ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
 808         if (ret)
 809                 return ret;
 810
 811         ret = clk_enable(&i2c_priv->clk);
 812         if (ret)
 813                 goto clk_free;
 814
 815         ret = reset_get_by_index(dev, 0, &reset_ctl);
 816         if (ret)
 817                 goto clk_disable;
 818
 819         reset_assert(&reset_ctl);
 820         udelay(2);
 821         reset_deassert(&reset_ctl);
 822
 823         return 0;
 824
 825 clk_disable:
 826         clk_disable(&i2c_priv->clk);
 827 clk_free:
 828         clk_free(&i2c_priv->clk);
 829
 830         return ret;
 831 }
 832
 833 static int stm32_ofdata_to_platdata(struct udevice *dev)
 834 {
 835         struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
 836         u32 rise_time, fall_time;
 837
 838         i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
 839         if (!i2c_priv->setup)
 840                 return -EINVAL;
 841
 842         rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
 843         if (rise_time)
 844                 i2c_priv->setup->rise_time = rise_time;
 845
 846         fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
 847         if (fall_time)
 848                 i2c_priv->setup->fall_time = fall_time;
 849
 850         return 0;
 851 }
 852
 853 static const struct dm_i2c_ops stm32_i2c_ops = {
 854         .xfer = stm32_i2c_xfer,
 855         .set_bus_speed = stm32_i2c_set_bus_speed,
 856 };
 857
 858 static const struct udevice_id stm32_i2c_of_match[] = {
 859         { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
 860         {}
 861 };
 862
 863 U_BOOT_DRIVER(stm32f7_i2c) = {
 864         .name = "stm32f7-i2c",
 865         .id = UCLASS_I2C,
 866         .of_match = stm32_i2c_of_match,
 867         .ofdata_to_platdata = stm32_ofdata_to_platdata,
 868         .probe = stm32_i2c_probe,
 869         .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
 870         .ops = &stm32_i2c_ops,
 871 };