1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2017 STMicroelectronics
13 #include <dm/device.h>
16 /* STM32 I2C registers */
17 struct stm32_i2c_regs {
18 u32 cr1; /* I2C control register 1 */
19 u32 cr2; /* I2C control register 2 */
20 u32 oar1; /* I2C own address 1 register */
21 u32 oar2; /* I2C own address 2 register */
22 u32 timingr; /* I2C timing register */
23 u32 timeoutr; /* I2C timeout register */
24 u32 isr; /* I2C interrupt and status register */
25 u32 icr; /* I2C interrupt clear register */
26 u32 pecr; /* I2C packet error checking register */
27 u32 rxdr; /* I2C receive data register */
28 u32 txdr; /* I2C transmit data register */
31 #define STM32_I2C_CR1 0x00
32 #define STM32_I2C_CR2 0x04
33 #define STM32_I2C_TIMINGR 0x10
34 #define STM32_I2C_ISR 0x18
35 #define STM32_I2C_ICR 0x1C
36 #define STM32_I2C_RXDR 0x24
37 #define STM32_I2C_TXDR 0x28
39 /* STM32 I2C control 1 */
40 #define STM32_I2C_CR1_ANFOFF BIT(12)
41 #define STM32_I2C_CR1_ERRIE BIT(7)
42 #define STM32_I2C_CR1_TCIE BIT(6)
43 #define STM32_I2C_CR1_STOPIE BIT(5)
44 #define STM32_I2C_CR1_NACKIE BIT(4)
45 #define STM32_I2C_CR1_ADDRIE BIT(3)
46 #define STM32_I2C_CR1_RXIE BIT(2)
47 #define STM32_I2C_CR1_TXIE BIT(1)
48 #define STM32_I2C_CR1_PE BIT(0)
50 /* STM32 I2C control 2 */
51 #define STM32_I2C_CR2_AUTOEND BIT(25)
52 #define STM32_I2C_CR2_RELOAD BIT(24)
53 #define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
54 #define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16)
55 #define STM32_I2C_CR2_NACK BIT(15)
56 #define STM32_I2C_CR2_STOP BIT(14)
57 #define STM32_I2C_CR2_START BIT(13)
58 #define STM32_I2C_CR2_HEAD10R BIT(12)
59 #define STM32_I2C_CR2_ADD10 BIT(11)
60 #define STM32_I2C_CR2_RD_WRN BIT(10)
61 #define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0)
62 #define STM32_I2C_CR2_SADD10(n) (n & STM32_I2C_CR2_SADD10_MASK)
63 #define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1)
64 #define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1)
65 #define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \
66 | STM32_I2C_CR2_NBYTES_MASK \
67 | STM32_I2C_CR2_SADD7_MASK \
68 | STM32_I2C_CR2_RELOAD \
69 | STM32_I2C_CR2_RD_WRN)
71 /* STM32 I2C Interrupt Status */
72 #define STM32_I2C_ISR_BUSY BIT(15)
73 #define STM32_I2C_ISR_ARLO BIT(9)
74 #define STM32_I2C_ISR_BERR BIT(8)
75 #define STM32_I2C_ISR_TCR BIT(7)
76 #define STM32_I2C_ISR_TC BIT(6)
77 #define STM32_I2C_ISR_STOPF BIT(5)
78 #define STM32_I2C_ISR_NACKF BIT(4)
79 #define STM32_I2C_ISR_ADDR BIT(3)
80 #define STM32_I2C_ISR_RXNE BIT(2)
81 #define STM32_I2C_ISR_TXIS BIT(1)
82 #define STM32_I2C_ISR_TXE BIT(0)
83 #define STM32_I2C_ISR_ERRORS (STM32_I2C_ISR_BERR \
86 /* STM32 I2C Interrupt Clear */
87 #define STM32_I2C_ICR_ARLOCF BIT(9)
88 #define STM32_I2C_ICR_BERRCF BIT(8)
89 #define STM32_I2C_ICR_STOPCF BIT(5)
90 #define STM32_I2C_ICR_NACKCF BIT(4)
92 /* STM32 I2C Timing */
93 #define STM32_I2C_TIMINGR_PRESC(n) ((n & 0xf) << 28)
94 #define STM32_I2C_TIMINGR_SCLDEL(n) ((n & 0xf) << 20)
95 #define STM32_I2C_TIMINGR_SDADEL(n) ((n & 0xf) << 16)
96 #define STM32_I2C_TIMINGR_SCLH(n) ((n & 0xff) << 8)
97 #define STM32_I2C_TIMINGR_SCLL(n) (n & 0xff)
99 #define STM32_I2C_MAX_LEN 0xff
101 #define STM32_I2C_DNF_DEFAULT 0
102 #define STM32_I2C_DNF_MAX 16
104 #define STM32_I2C_ANALOG_FILTER_ENABLE 1
105 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
106 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
108 #define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */
109 #define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */
111 #define STM32_PRESC_MAX BIT(4)
112 #define STM32_SCLDEL_MAX BIT(4)
113 #define STM32_SDADEL_MAX BIT(4)
114 #define STM32_SCLH_MAX BIT(8)
115 #define STM32_SCLL_MAX BIT(8)
117 #define STM32_NSEC_PER_SEC 1000000000L
120 * struct stm32_i2c_spec - private i2c specification timing
121 * @rate: I2C bus speed (Hz)
122 * @rate_min: 80% of I2C bus speed (Hz)
123 * @rate_max: 120% of I2C bus speed (Hz)
124 * @fall_max: Max fall time of both SDA and SCL signals (ns)
125 * @rise_max: Max rise time of both SDA and SCL signals (ns)
126 * @hddat_min: Min data hold time (ns)
127 * @vddat_max: Max data valid time (ns)
128 * @sudat_min: Min data setup time (ns)
129 * @l_min: Min low period of the SCL clock (ns)
130 * @h_min: Min high period of the SCL clock (ns)
133 struct stm32_i2c_spec {
147 * struct stm32_i2c_setup - private I2C timing setup parameters
148 * @speed: I2C speed mode (standard, Fast Plus)
149 * @speed_freq: I2C speed frequency (Hz)
150 * @clock_src: I2C clock source frequency (Hz)
151 * @rise_time: Rise time (ns)
152 * @fall_time: Fall time (ns)
153 * @dnf: Digital filter coefficient (0-16)
154 * @analog_filter: Analog filter delay (On/Off)
156 struct stm32_i2c_setup {
157 enum i2c_speed_mode speed;
167 * struct stm32_i2c_timings - private I2C output parameters
168 * @prec: Prescaler value
169 * @scldel: Data setup time
170 * @sdadel: Data hold time
171 * @sclh: SCL high period (master mode)
172 * @sclh: SCL low period (master mode)
174 struct stm32_i2c_timings {
175 struct list_head node;
183 struct stm32_i2c_priv {
184 struct stm32_i2c_regs *regs;
186 struct stm32_i2c_setup *setup;
190 static const struct stm32_i2c_spec i2c_specs[] = {
191 [IC_SPEED_MODE_STANDARD] = {
192 .rate = I2C_SPEED_STANDARD_RATE,
203 [IC_SPEED_MODE_FAST] = {
204 .rate = I2C_SPEED_FAST_RATE,
215 [IC_SPEED_MODE_FAST_PLUS] = {
216 .rate = I2C_SPEED_FAST_PLUS_RATE,
229 static const struct stm32_i2c_setup stm32f7_setup = {
230 .rise_time = STM32_I2C_RISE_TIME_DEFAULT,
231 .fall_time = STM32_I2C_FALL_TIME_DEFAULT,
232 .dnf = STM32_I2C_DNF_DEFAULT,
233 .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE,
236 static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv)
238 struct stm32_i2c_regs *regs = i2c_priv->regs;
239 u32 status = readl(®s->isr);
241 if (status & STM32_I2C_ISR_BUSY)
247 static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv,
248 struct i2c_msg *msg, bool stop)
250 struct stm32_i2c_regs *regs = i2c_priv->regs;
251 u32 cr2 = readl(®s->cr2);
253 /* Set transfer direction */
254 cr2 &= ~STM32_I2C_CR2_RD_WRN;
255 if (msg->flags & I2C_M_RD)
256 cr2 |= STM32_I2C_CR2_RD_WRN;
258 /* Set slave address */
259 cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10);
260 if (msg->flags & I2C_M_TEN) {
261 cr2 &= ~STM32_I2C_CR2_SADD10_MASK;
262 cr2 |= STM32_I2C_CR2_SADD10(msg->addr);
263 cr2 |= STM32_I2C_CR2_ADD10;
265 cr2 &= ~STM32_I2C_CR2_SADD7_MASK;
266 cr2 |= STM32_I2C_CR2_SADD7(msg->addr);
269 /* Set nb bytes to transfer and reload or autoend bits */
270 cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD |
271 STM32_I2C_CR2_AUTOEND);
272 if (msg->len > STM32_I2C_MAX_LEN) {
273 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
274 cr2 |= STM32_I2C_CR2_RELOAD;
276 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
279 /* Write configurations register */
280 writel(cr2, ®s->cr2);
282 /* START/ReSTART generation */
283 setbits_le32(®s->cr2, STM32_I2C_CR2_START);
287 * RELOAD mode must be selected if total number of data bytes to be
288 * sent is greater than MAX_LEN
291 static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv,
292 struct i2c_msg *msg, bool stop)
294 struct stm32_i2c_regs *regs = i2c_priv->regs;
295 u32 cr2 = readl(®s->cr2);
297 cr2 &= ~STM32_I2C_CR2_NBYTES_MASK;
299 if (msg->len > STM32_I2C_MAX_LEN) {
300 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN);
302 cr2 &= ~STM32_I2C_CR2_RELOAD;
303 cr2 |= STM32_I2C_CR2_NBYTES(msg->len);
306 writel(cr2, ®s->cr2);
309 static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv,
310 u32 flags, u32 *status)
312 struct stm32_i2c_regs *regs = i2c_priv->regs;
313 u32 time_start = get_timer(0);
315 *status = readl(®s->isr);
316 while (!(*status & flags)) {
317 if (get_timer(time_start) > CONFIG_SYS_HZ) {
318 debug("%s: i2c timeout\n", __func__);
322 *status = readl(®s->isr);
328 static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv)
330 struct stm32_i2c_regs *regs = i2c_priv->regs;
331 u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF |
336 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
340 if (status & STM32_I2C_ISR_BERR) {
341 debug("%s: Bus error\n", __func__);
343 /* Clear BERR flag */
344 setbits_le32(®s->icr, STM32_I2C_ICR_BERRCF);
349 if (status & STM32_I2C_ISR_ARLO) {
350 debug("%s: Arbitration lost\n", __func__);
352 /* Clear ARLO flag */
353 setbits_le32(®s->icr, STM32_I2C_ICR_ARLOCF);
358 if (status & STM32_I2C_ISR_NACKF) {
359 debug("%s: Receive NACK\n", __func__);
361 /* Clear NACK flag */
362 setbits_le32(®s->icr, STM32_I2C_ICR_NACKCF);
364 /* Wait until STOPF flag is set */
365 mask = STM32_I2C_ISR_STOPF;
366 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
373 if (status & STM32_I2C_ISR_STOPF) {
374 /* Clear STOP flag */
375 setbits_le32(®s->icr, STM32_I2C_ICR_STOPCF);
377 /* Clear control register 2 */
378 setbits_le32(®s->cr2, STM32_I2C_CR2_RESET_MASK);
384 static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv,
385 struct i2c_msg *msg, bool stop)
387 struct stm32_i2c_regs *regs = i2c_priv->regs;
389 u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
390 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
391 int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
392 STM32_I2C_MAX_LEN : msg->len;
396 mask |= STM32_I2C_ISR_ERRORS;
398 stm32_i2c_message_start(i2c_priv, msg, stop);
402 * Wait until TXIS/NACKF/BERR/ARLO flags or
403 * RXNE/BERR/ARLO flags are set
405 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
409 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS))
412 if (status & STM32_I2C_ISR_RXNE) {
413 *msg->buf++ = readb(®s->rxdr);
418 if (status & STM32_I2C_ISR_TXIS) {
419 writeb(*msg->buf++, ®s->txdr);
424 if (!bytes_to_rw && msg->len) {
425 /* Wait until TCR flag is set */
426 mask = STM32_I2C_ISR_TCR;
427 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
431 bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ?
432 STM32_I2C_MAX_LEN : msg->len;
433 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE :
434 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF;
436 stm32_i2c_handle_reload(i2c_priv, msg, stop);
437 } else if (!bytes_to_rw) {
438 /* Wait until TC flag is set */
439 mask = STM32_I2C_ISR_TC;
440 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status);
445 /* Message sent, new message has to be sent */
450 /* End of transfer, send stop condition */
451 mask = STM32_I2C_CR2_STOP;
452 setbits_le32(®s->cr2, mask);
454 return stm32_i2c_check_end_of_message(i2c_priv);
457 static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
460 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
463 ret = stm32_i2c_check_device_busy(i2c_priv);
467 for (; nmsgs > 0; nmsgs--, msg++) {
468 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1);
476 static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup,
477 struct list_head *solutions)
479 struct stm32_i2c_timings *v;
480 u32 p_prev = STM32_PRESC_MAX;
481 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
483 u32 af_delay_min, af_delay_max;
485 int sdadel_min, sdadel_max, scldel_min;
488 af_delay_min = setup->analog_filter ?
489 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
490 af_delay_max = setup->analog_filter ?
491 STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0;
493 sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
494 af_delay_min - (setup->dnf + 3) * i2cclk;
496 sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
497 af_delay_max - (setup->dnf + 4) * i2cclk;
499 scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
506 debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
507 sdadel_min, sdadel_max, scldel_min);
509 /* Compute possible values for PRESC, SCLDEL and SDADEL */
510 for (p = 0; p < STM32_PRESC_MAX; p++) {
511 for (l = 0; l < STM32_SCLDEL_MAX; l++) {
512 int scldel = (l + 1) * (p + 1) * i2cclk;
514 if (scldel < scldel_min)
517 for (a = 0; a < STM32_SDADEL_MAX; a++) {
518 int sdadel = (a * (p + 1) + 1) * i2cclk;
520 if (((sdadel >= sdadel_min) &&
521 (sdadel <= sdadel_max)) &&
523 v = calloc(1, sizeof(*v));
532 list_add_tail(&v->node, solutions);
542 if (list_empty(solutions)) {
543 pr_err("%s: no Prescaler solution\n", __func__);
550 static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup,
551 struct list_head *solutions,
552 struct stm32_i2c_timings *s)
554 struct stm32_i2c_timings *v;
555 u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
557 u32 clk_error_prev = i2cbus;
558 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
560 u32 clk_min, clk_max;
565 bool sol_found = false;
568 af_delay_min = setup->analog_filter ?
569 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0;
570 dnf_delay = setup->dnf * i2cclk;
572 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
573 clk_max = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
574 clk_min = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
577 * Among Prescaler possibilities discovered above figures out SCL Low
578 * and High Period. Provided:
579 * - SCL Low Period has to be higher than Low Period of the SCL Clock
580 * defined by I2C Specification. I2C Clock has to be lower than
581 * (SCL Low Period - Analog/Digital filters) / 4.
582 * - SCL High Period has to be lower than High Period of the SCL Clock
583 * defined by I2C Specification
584 * - I2C Clock has to be lower than SCL High Period
586 list_for_each_entry(v, solutions, node) {
587 u32 prescaler = (v->presc + 1) * i2cclk;
589 for (l = 0; l < STM32_SCLL_MAX; l++) {
590 u32 tscl_l = (l + 1) * prescaler + tsync;
592 if ((tscl_l < i2c_specs[setup->speed].l_min) ||
594 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
598 for (h = 0; h < STM32_SCLH_MAX; h++) {
599 u32 tscl_h = (h + 1) * prescaler + tsync;
600 u32 tscl = tscl_l + tscl_h +
601 setup->rise_time + setup->fall_time;
603 if ((tscl >= clk_min) && (tscl <= clk_max) &&
604 (tscl_h >= i2c_specs[setup->speed].h_min) &&
609 clk_error = tscl - i2cbus;
611 clk_error = i2cbus - tscl;
613 if (clk_error < clk_error_prev) {
614 clk_error_prev = clk_error;
618 memcpy(s, v, sizeof(*s));
626 pr_err("%s: no solution at all\n", __func__);
633 static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
634 struct stm32_i2c_setup *setup,
635 struct stm32_i2c_timings *output)
637 struct stm32_i2c_timings *v, *_v;
638 struct list_head solutions;
641 if (setup->speed >= ARRAY_SIZE(i2c_specs)) {
642 pr_err("%s: speed out of bound {%d/%d}\n", __func__,
643 setup->speed, ARRAY_SIZE(i2c_specs) - 1);
647 if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
648 (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
649 pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
651 setup->rise_time, i2c_specs[setup->speed].rise_max,
652 setup->fall_time, i2c_specs[setup->speed].fall_max);
656 if (setup->dnf > STM32_I2C_DNF_MAX) {
657 pr_err("%s: DNF out of bound %d/%d\n", __func__,
658 setup->dnf, STM32_I2C_DNF_MAX);
662 if (setup->speed_freq > i2c_specs[setup->speed].rate) {
663 pr_err("%s: Freq {%d/%d}\n", __func__,
664 setup->speed_freq, i2c_specs[setup->speed].rate);
668 INIT_LIST_HEAD(&solutions);
669 ret = stm32_i2c_compute_solutions(setup, &solutions);
673 ret = stm32_i2c_choose_solution(setup, &solutions, output);
677 debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
678 __func__, output->presc,
679 output->scldel, output->sdadel,
680 output->scll, output->sclh);
683 /* Release list and memory */
684 list_for_each_entry_safe(v, _v, &solutions, node) {
692 static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv,
693 struct stm32_i2c_timings *timing)
695 struct stm32_i2c_setup *setup = i2c_priv->setup;
698 setup->speed = i2c_priv->speed;
699 setup->speed_freq = i2c_specs[setup->speed].rate;
700 setup->clock_src = clk_get_rate(&i2c_priv->clk);
702 if (!setup->clock_src) {
703 pr_err("%s: clock rate is 0\n", __func__);
708 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
710 debug("%s: failed to compute I2C timings.\n",
712 if (i2c_priv->speed > IC_SPEED_MODE_STANDARD) {
714 setup->speed = i2c_priv->speed;
716 i2c_specs[setup->speed].rate;
717 debug("%s: downgrade I2C Speed Freq to (%i)\n",
718 __func__, i2c_specs[setup->speed].rate);
726 pr_err("%s: impossible to compute I2C timings.\n", __func__);
730 debug("%s: I2C Speed(%i), Freq(%i), Clk Source(%i)\n", __func__,
731 setup->speed, setup->speed_freq, setup->clock_src);
732 debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
733 setup->rise_time, setup->fall_time);
734 debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
735 setup->analog_filter ? "On" : "Off", setup->dnf);
740 static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv)
742 struct stm32_i2c_regs *regs = i2c_priv->regs;
743 struct stm32_i2c_timings t;
747 ret = stm32_i2c_setup_timing(i2c_priv, &t);
752 clrbits_le32(®s->cr1, STM32_I2C_CR1_PE);
754 /* Timing settings */
755 timing |= STM32_I2C_TIMINGR_PRESC(t.presc);
756 timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel);
757 timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel);
758 timing |= STM32_I2C_TIMINGR_SCLH(t.sclh);
759 timing |= STM32_I2C_TIMINGR_SCLL(t.scll);
760 writel(timing, ®s->timingr);
763 if (i2c_priv->setup->analog_filter)
764 clrbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF);
766 setbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF);
767 setbits_le32(®s->cr1, STM32_I2C_CR1_PE);
772 static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
774 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
777 case I2C_SPEED_STANDARD_RATE:
778 i2c_priv->speed = IC_SPEED_MODE_STANDARD;
780 case I2C_SPEED_FAST_RATE:
781 i2c_priv->speed = IC_SPEED_MODE_FAST;
783 case I2C_SPEED_FAST_PLUS_RATE:
784 i2c_priv->speed = IC_SPEED_MODE_FAST_PLUS;
787 debug("%s: Speed %d not supported\n", __func__, speed);
791 return stm32_i2c_hw_config(i2c_priv);
794 static int stm32_i2c_probe(struct udevice *dev)
796 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
797 struct reset_ctl reset_ctl;
801 addr = dev_read_addr(dev);
802 if (addr == FDT_ADDR_T_NONE)
805 i2c_priv->regs = (struct stm32_i2c_regs *)addr;
807 ret = clk_get_by_index(dev, 0, &i2c_priv->clk);
811 ret = clk_enable(&i2c_priv->clk);
815 ret = reset_get_by_index(dev, 0, &reset_ctl);
819 reset_assert(&reset_ctl);
821 reset_deassert(&reset_ctl);
826 clk_disable(&i2c_priv->clk);
828 clk_free(&i2c_priv->clk);
833 static int stm32_ofdata_to_platdata(struct udevice *dev)
835 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
836 u32 rise_time, fall_time;
838 i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev);
839 if (!i2c_priv->setup)
842 rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0);
844 i2c_priv->setup->rise_time = rise_time;
846 fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0);
848 i2c_priv->setup->fall_time = fall_time;
853 static const struct dm_i2c_ops stm32_i2c_ops = {
854 .xfer = stm32_i2c_xfer,
855 .set_bus_speed = stm32_i2c_set_bus_speed,
858 static const struct udevice_id stm32_i2c_of_match[] = {
859 { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup },
863 U_BOOT_DRIVER(stm32f7_i2c) = {
864 .name = "stm32f7-i2c",
866 .of_match = stm32_i2c_of_match,
867 .ofdata_to_platdata = stm32_ofdata_to_platdata,
868 .probe = stm32_i2c_probe,
869 .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv),
870 .ops = &stm32_i2c_ops,