1 // SPDX-License-Identifier: GPL-2.0+
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * Changes for multibus/multiadapter I2C support.
7 * (C) Copyright 2001, 2002
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * This has been changed substantially by Gerald Van Baren, Custom IDEAS,
11 * vanbaren@cideas.com. It was heavily influenced by LiMon, written by
14 * NOTE: This driver should be converted to driver model before June 2017.
15 * Please see doc/driver-model/i2c-howto.rst for instructions.
19 #if defined(CONFIG_AT91FAMILY)
21 #include <asm/arch/hardware.h>
22 #include <asm/arch/at91_pio.h>
23 #ifdef CONFIG_ATMEL_LEGACY
24 #include <asm/arch/gpio.h>
28 #include <linux/delay.h>
30 #if defined(CONFIG_SOFT_I2C_GPIO_SCL)
31 # include <asm/gpio.h>
33 # ifndef I2C_GPIO_SYNC
34 # define I2C_GPIO_SYNC
40 gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, "soft_i2c"); \
41 gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, "soft_i2c"); \
46 # define I2C_ACTIVE do { } while (0)
50 # define I2C_TRISTATE do { } while (0)
54 # define I2C_READ gpio_get_value(CONFIG_SOFT_I2C_GPIO_SDA)
58 # define I2C_SDA(bit) \
61 gpio_direction_input(CONFIG_SOFT_I2C_GPIO_SDA); \
63 gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SDA, 0); \
69 # define I2C_SCL(bit) \
71 gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SCL, bit); \
77 # define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
82 /* #define DEBUG_I2C */
84 DECLARE_GLOBAL_DATA_PTR;
86 #ifndef I2C_SOFT_DECLARATIONS
87 # define I2C_SOFT_DECLARATIONS
90 #if !defined(CONFIG_SYS_I2C_SOFT_SPEED)
91 #define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED
93 #if !defined(CONFIG_SYS_I2C_SOFT_SLAVE)
94 #define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE
97 /*-----------------------------------------------------------------------
102 #define I2C_ACK 0 /* PD_SDA level to ack a byte */
103 #define I2C_NOACK 1 /* PD_SDA level to noack a byte */
107 #define PRINTD(fmt,args...) do { \
108 printf (fmt ,##args); \
111 #define PRINTD(fmt,args...)
114 /*-----------------------------------------------------------------------
117 #if !defined(CONFIG_SYS_I2C_INIT_BOARD)
118 static void send_reset (void);
120 static void send_start (void);
121 static void send_stop (void);
122 static void send_ack (int);
123 static int write_byte (uchar byte);
124 static uchar read_byte (int);
126 #if !defined(CONFIG_SYS_I2C_INIT_BOARD)
127 /*-----------------------------------------------------------------------
128 * Send a reset sequence consisting of 9 clocks with the data signal high
129 * to clock any confused device back into an idle state. Also send a
130 * <stop> at the end of the sequence for belts & suspenders.
132 static void send_reset(void)
134 I2C_SOFT_DECLARATIONS /* intentional without ';' */
143 for(j = 0; j < 9; j++) {
156 /*-----------------------------------------------------------------------
157 * START: High -> Low on SDA while SCL is High
159 static void send_start(void)
161 I2C_SOFT_DECLARATIONS /* intentional without ';' */
173 /*-----------------------------------------------------------------------
174 * STOP: Low -> High on SDA while SCL is High
176 static void send_stop(void)
178 I2C_SOFT_DECLARATIONS /* intentional without ';' */
192 /*-----------------------------------------------------------------------
193 * ack should be I2C_ACK or I2C_NOACK
195 static void send_ack(int ack)
197 I2C_SOFT_DECLARATIONS /* intentional without ';' */
211 /*-----------------------------------------------------------------------
212 * Send 8 bits and look for an acknowledgement.
214 static int write_byte(uchar data)
216 I2C_SOFT_DECLARATIONS /* intentional without ';' */
221 for(j = 0; j < 8; j++) {
224 I2C_SDA(data & 0x80);
234 * Look for an <ACK>(negative logic) and return it.
249 return(nack); /* not a nack is an ack */
252 /*-----------------------------------------------------------------------
253 * if ack == I2C_ACK, ACK the byte so can continue reading, else
254 * send I2C_NOACK to end the read.
256 static uchar read_byte(int ack)
258 I2C_SOFT_DECLARATIONS /* intentional without ';' */
263 * Read 8 bits, MSB first.
268 for(j = 0; j < 8; j++) {
282 /*-----------------------------------------------------------------------
285 static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
287 #if defined(CONFIG_SYS_I2C_INIT_BOARD)
288 /* call board specific i2c bus reset routine before accessing the */
289 /* environment, which might be in a chip on that bus. For details */
290 /* about this problem see doc/I2C_Edge_Conditions. */
294 * WARNING: Do NOT save speed in a static variable: if the
295 * I2C routines are called before RAM is initialized (to read
296 * the DIMM SPD, for instance), RAM won't be usable and your
303 /*-----------------------------------------------------------------------
304 * Probe to see if a chip is present. Also good for checking for the
305 * completion of EEPROM writes since the chip stops responding until
306 * the write completes (typically 10mSec).
308 static int soft_i2c_probe(struct i2c_adapter *adap, uint8_t addr)
313 * perform 1 byte write transaction with just address byte
317 rc = write_byte ((addr << 1) | 0);
323 /*-----------------------------------------------------------------------
326 static int soft_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
327 int alen, uchar *buffer, int len)
330 PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
331 chip, addr, alen, buffer, len);
333 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
335 * EEPROM chips that implement "address overflow" are ones
336 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
337 * address and the extra bits end up in the "chip address"
338 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
339 * four 256 byte chips.
341 * Note that we consider the length of the address field to
342 * still be one byte because the extra address bits are
343 * hidden in the chip address.
345 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
347 PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
352 * Do the addressing portion of a write cycle to set the
353 * chip's address pointer. If the address length is zero,
354 * don't do the normal write cycle to set the address pointer,
355 * there is no address pointer in this chip.
359 if(write_byte(chip << 1)) { /* write cycle */
361 PRINTD("i2c_read, no chip responded %02X\n", chip);
364 shift = (alen-1) * 8;
366 if(write_byte(addr >> shift)) {
367 PRINTD("i2c_read, address not <ACK>ed\n");
373 /* Some I2C chips need a stop/start sequence here,
374 * other chips don't work with a full stop and need
375 * only a start. Default behaviour is to send the
376 * stop/start sequence.
378 #ifdef CONFIG_SOFT_I2C_READ_REPEATED_START
386 * Send the chip address again, this time for a read cycle.
387 * Then read the data. On the last byte, we do a NACK instead
388 * of an ACK(len == 0) to terminate the read.
390 write_byte((chip << 1) | 1); /* read cycle */
392 *buffer++ = read_byte(len == 0);
398 /*-----------------------------------------------------------------------
401 static int soft_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
402 int alen, uchar *buffer, int len)
404 int shift, failures = 0;
406 PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
407 chip, addr, alen, buffer, len);
410 if(write_byte(chip << 1)) { /* write cycle */
412 PRINTD("i2c_write, no chip responded %02X\n", chip);
415 shift = (alen-1) * 8;
417 if(write_byte(addr >> shift)) {
418 PRINTD("i2c_write, address not <ACK>ed\n");
425 if(write_byte(*buffer++)) {
434 * Register soft i2c adapters
436 U_BOOT_I2C_ADAP_COMPLETE(soft00, soft_i2c_init, soft_i2c_probe,
437 soft_i2c_read, soft_i2c_write, NULL,
438 CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE,
440 #if defined(I2C_SOFT_DECLARATIONS2)
441 U_BOOT_I2C_ADAP_COMPLETE(soft01, soft_i2c_init, soft_i2c_probe,
442 soft_i2c_read, soft_i2c_write, NULL,
443 CONFIG_SYS_I2C_SOFT_SPEED_2,
444 CONFIG_SYS_I2C_SOFT_SLAVE_2,
447 #if defined(I2C_SOFT_DECLARATIONS3)
448 U_BOOT_I2C_ADAP_COMPLETE(soft02, soft_i2c_init, soft_i2c_probe,
449 soft_i2c_read, soft_i2c_write, NULL,
450 CONFIG_SYS_I2C_SOFT_SPEED_3,
451 CONFIG_SYS_I2C_SOFT_SLAVE_3,
454 #if defined(I2C_SOFT_DECLARATIONS4)
455 U_BOOT_I2C_ADAP_COMPLETE(soft03, soft_i2c_init, soft_i2c_probe,
456 soft_i2c_read, soft_i2c_write, NULL,
457 CONFIG_SYS_I2C_SOFT_SPEED_4,
458 CONFIG_SYS_I2C_SOFT_SLAVE_4,
461 #if defined(I2C_SOFT_DECLARATIONS5)
462 U_BOOT_I2C_ADAP_COMPLETE(soft04, soft_i2c_init, soft_i2c_probe,
463 soft_i2c_read, soft_i2c_write, NULL,
464 CONFIG_SYS_I2C_SOFT_SPEED_5,
465 CONFIG_SYS_I2C_SOFT_SLAVE_5,
468 #if defined(I2C_SOFT_DECLARATIONS6)
469 U_BOOT_I2C_ADAP_COMPLETE(soft05, soft_i2c_init, soft_i2c_probe,
470 soft_i2c_read, soft_i2c_write, NULL,
471 CONFIG_SYS_I2C_SOFT_SPEED_6,
472 CONFIG_SYS_I2C_SOFT_SLAVE_6,
475 #if defined(I2C_SOFT_DECLARATIONS7)
476 U_BOOT_I2C_ADAP_COMPLETE(soft06, soft_i2c_init, soft_i2c_probe,
477 soft_i2c_read, soft_i2c_write, NULL,
478 CONFIG_SYS_I2C_SOFT_SPEED_7,
479 CONFIG_SYS_I2C_SOFT_SLAVE_7,
482 #if defined(I2C_SOFT_DECLARATIONS8)
483 U_BOOT_I2C_ADAP_COMPLETE(soft07, soft_i2c_init, soft_i2c_probe,
484 soft_i2c_read, soft_i2c_write, NULL,
485 CONFIG_SYS_I2C_SOFT_SPEED_8,
486 CONFIG_SYS_I2C_SOFT_SLAVE_8,
489 #if defined(I2C_SOFT_DECLARATIONS9)
490 U_BOOT_I2C_ADAP_COMPLETE(soft08, soft_i2c_init, soft_i2c_probe,
491 soft_i2c_read, soft_i2c_write, NULL,
492 CONFIG_SYS_I2C_SOFT_SPEED_9,
493 CONFIG_SYS_I2C_SOFT_SLAVE_9,
496 #if defined(I2C_SOFT_DECLARATIONS10)
497 U_BOOT_I2C_ADAP_COMPLETE(soft09, soft_i2c_init, soft_i2c_probe,
498 soft_i2c_read, soft_i2c_write, NULL,
499 CONFIG_SYS_I2C_SOFT_SPEED_10,
500 CONFIG_SYS_I2C_SOFT_SLAVE_10,
503 #if defined(I2C_SOFT_DECLARATIONS11)
504 U_BOOT_I2C_ADAP_COMPLETE(soft10, soft_i2c_init, soft_i2c_probe,
505 soft_i2c_read, soft_i2c_write, NULL,
506 CONFIG_SYS_I2C_SOFT_SPEED_11,
507 CONFIG_SYS_I2C_SOFT_SLAVE_11,
510 #if defined(I2C_SOFT_DECLARATIONS12)
511 U_BOOT_I2C_ADAP_COMPLETE(soft11, soft_i2c_init, soft_i2c_probe,
512 soft_i2c_read, soft_i2c_write, NULL,
513 CONFIG_SYS_I2C_SOFT_SPEED_12,
514 CONFIG_SYS_I2C_SOFT_SLAVE_12,