drivers/i2c/s3c24x0_i2c.c

   1 /*
   2  * (C) Copyright 2002
   3  * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /* This code should work for both the S3C2400 and the S3C2410
   9  * as they seem to have the same I2C controller inside.
  10  * The different address mapping is handled by the s3c24xx.h files below.
  11  */
  12 #include <common.h>
  13 #include <errno.h>
  14 #include <dm.h>
  15 #include <fdtdec.h>
  16 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  17 #include <asm/arch/clk.h>
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/pinmux.h>
  20 #else
  21 #include <asm/arch/s3c24x0_cpu.h>
  22 #endif
  23 #include <asm/io.h>
  24 #include <i2c.h>
  25 #include "s3c24x0_i2c.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 /*
  30  * Wait til the byte transfer is completed.
  31  *
  32  * @param i2c- pointer to the appropriate i2c register bank.
  33  * @return I2C_OK, if transmission was ACKED
  34  *         I2C_NACK, if transmission was NACKED
  35  *         I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
  36  */
  37
  38 static int WaitForXfer(struct s3c24x0_i2c *i2c)
  39 {
  40         ulong start_time = get_timer(0);
  41
  42         do {
  43                 if (readl(&i2c->iiccon) & I2CCON_IRPND)
  44                         return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
  45                                 I2C_NACK : I2C_OK;
  46         } while (get_timer(start_time) < I2C_TIMEOUT_MS);
  47
  48         return I2C_NOK_TOUT;
  49 }
  50
  51 static void read_write_byte(struct s3c24x0_i2c *i2c)
  52 {
  53         clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
  54 }
  55
  56 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
  57 {
  58         ulong freq, pres = 16, div;
  59 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  60         freq = get_i2c_clk();
  61 #else
  62         freq = get_PCLK();
  63 #endif
  64         /* calculate prescaler and divisor values */
  65         if ((freq / pres / (16 + 1)) > speed)
  66                 /* set prescaler to 512 */
  67                 pres = 512;
  68
  69         div = 0;
  70         while ((freq / pres / (div + 1)) > speed)
  71                 div++;
  72
  73         /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
  74         writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
  75
  76         /* init to SLAVE REVEIVE and set slaveaddr */
  77         writel(0, &i2c->iicstat);
  78         writel(slaveadd, &i2c->iicadd);
  79         /* program Master Transmit (and implicit STOP) */
  80         writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
  81 }
  82
  83 static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
  84 {
  85         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
  86
  87         i2c_bus->clock_frequency = speed;
  88
  89         i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
  90                     CONFIG_SYS_I2C_S3C24X0_SLAVE);
  91
  92         return 0;
  93 }
  94
  95 /*
  96  * cmd_type is 0 for write, 1 for read.
  97  *
  98  * addr_len can take any value from 0-255, it is only limited
  99  * by the char, we could make it larger if needed. If it is
 100  * 0 we skip the address write cycle.
 101  */
 102 static int i2c_transfer(struct s3c24x0_i2c *i2c,
 103                         unsigned char cmd_type,
 104                         unsigned char chip,
 105                         unsigned char addr[],
 106                         unsigned char addr_len,
 107                         unsigned char data[],
 108                         unsigned short data_len)
 109 {
 110         int i = 0, result;
 111         ulong start_time = get_timer(0);
 112
 113         if (data == 0 || data_len == 0) {
 114                 /*Don't support data transfer of no length or to address 0 */
 115                 debug("i2c_transfer: bad call\n");
 116                 return I2C_NOK;
 117         }
 118
 119         while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
 120                 if (get_timer(start_time) > I2C_TIMEOUT_MS)
 121                         return I2C_NOK_TOUT;
 122         }
 123
 124         writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
 125
 126         /* Get the slave chip address going */
 127         writel(chip, &i2c->iicds);
 128         if ((cmd_type == I2C_WRITE) || (addr && addr_len))
 129                 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
 130                        &i2c->iicstat);
 131         else
 132                 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
 133                        &i2c->iicstat);
 134
 135         /* Wait for chip address to transmit. */
 136         result = WaitForXfer(i2c);
 137         if (result != I2C_OK)
 138                 goto bailout;
 139
 140         /* If register address needs to be transmitted - do it now. */
 141         if (addr && addr_len) {
 142                 while ((i < addr_len) && (result == I2C_OK)) {
 143                         writel(addr[i++], &i2c->iicds);
 144                         read_write_byte(i2c);
 145                         result = WaitForXfer(i2c);
 146                 }
 147                 i = 0;
 148                 if (result != I2C_OK)
 149                         goto bailout;
 150         }
 151
 152         switch (cmd_type) {
 153         case I2C_WRITE:
 154                 while ((i < data_len) && (result == I2C_OK)) {
 155                         writel(data[i++], &i2c->iicds);
 156                         read_write_byte(i2c);
 157                         result = WaitForXfer(i2c);
 158                 }
 159                 break;
 160
 161         case I2C_READ:
 162                 if (addr && addr_len) {
 163                         /*
 164                          * Register address has been sent, now send slave chip
 165                          * address again to start the actual read transaction.
 166                          */
 167                         writel(chip, &i2c->iicds);
 168
 169                         /* Generate a re-START. */
 170                         writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
 171                                 &i2c->iicstat);
 172                         read_write_byte(i2c);
 173                         result = WaitForXfer(i2c);
 174
 175                         if (result != I2C_OK)
 176                                 goto bailout;
 177                 }
 178
 179                 while ((i < data_len) && (result == I2C_OK)) {
 180                         /* disable ACK for final READ */
 181                         if (i == data_len - 1)
 182                                 writel(readl(&i2c->iiccon)
 183                                        & ~I2CCON_ACKGEN,
 184                                        &i2c->iiccon);
 185                         read_write_byte(i2c);
 186                         result = WaitForXfer(i2c);
 187                         data[i++] = readl(&i2c->iicds);
 188                 }
 189                 if (result == I2C_NACK)
 190                         result = I2C_OK; /* Normal terminated read. */
 191                 break;
 192
 193         default:
 194                 debug("i2c_transfer: bad call\n");
 195                 result = I2C_NOK;
 196                 break;
 197         }
 198
 199 bailout:
 200         /* Send STOP. */
 201         writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 202         read_write_byte(i2c);
 203
 204         return result;
 205 }
 206
 207 static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
 208 {
 209         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
 210         uchar buf[1];
 211         int ret;
 212
 213         buf[0] = 0;
 214
 215         /*
 216          * What is needed is to send the chip address and verify that the
 217          * address was <ACK>ed (i.e. there was a chip at that address which
 218          * drove the data line low).
 219          */
 220         ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
 221
 222         return ret != I2C_OK;
 223 }
 224
 225 static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
 226                           int seq)
 227 {
 228         struct s3c24x0_i2c *i2c = i2c_bus->regs;
 229         bool is_read = msg->flags & I2C_M_RD;
 230         uint status;
 231         uint addr;
 232         int ret, i;
 233
 234         if (!seq)
 235                 setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
 236
 237         /* Get the slave chip address going */
 238         addr = msg->addr << 1;
 239         writel(addr, &i2c->iicds);
 240         status = I2C_TXRX_ENA | I2C_START_STOP;
 241         if (is_read)
 242                 status |= I2C_MODE_MR;
 243         else
 244                 status |= I2C_MODE_MT;
 245         writel(status, &i2c->iicstat);
 246         if (seq)
 247                 read_write_byte(i2c);
 248
 249         /* Wait for chip address to transmit */
 250         ret = WaitForXfer(i2c);
 251         if (ret)
 252                 goto err;
 253
 254         if (is_read) {
 255                 for (i = 0; !ret && i < msg->len; i++) {
 256                         /* disable ACK for final READ */
 257                         if (i == msg->len - 1)
 258                                 clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
 259                         read_write_byte(i2c);
 260                         ret = WaitForXfer(i2c);
 261                         msg->buf[i] = readl(&i2c->iicds);
 262                 }
 263                 if (ret == I2C_NACK)
 264                         ret = I2C_OK; /* Normal terminated read */
 265         } else {
 266                 for (i = 0; !ret && i < msg->len; i++) {
 267                         writel(msg->buf[i], &i2c->iicds);
 268                         read_write_byte(i2c);
 269                         ret = WaitForXfer(i2c);
 270                 }
 271         }
 272
 273 err:
 274         return ret;
 275 }
 276
 277 static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
 278                             int nmsgs)
 279 {
 280         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
 281         struct s3c24x0_i2c *i2c = i2c_bus->regs;
 282         ulong start_time;
 283         int ret, i;
 284
 285         start_time = get_timer(0);
 286         while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
 287                 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
 288                         debug("Timeout\n");
 289                         return -ETIMEDOUT;
 290                 }
 291         }
 292
 293         for (ret = 0, i = 0; !ret && i < nmsgs; i++)
 294                 ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
 295
 296         /* Send STOP */
 297         writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 298         read_write_byte(i2c);
 299
 300         return ret ? -EREMOTEIO : 0;
 301 }
 302
 303 static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
 304 {
 305         const void *blob = gd->fdt_blob;
 306         struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
 307         int node;
 308
 309         node = dev->of_offset;
 310
 311         i2c_bus->regs = (struct s3c24x0_i2c *)dev_get_addr(dev);
 312
 313         i2c_bus->id = pinmux_decode_periph_id(blob, node);
 314
 315         i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
 316                                                   "clock-frequency", 100000);
 317         i2c_bus->node = node;
 318         i2c_bus->bus_num = dev->seq;
 319
 320         exynos_pinmux_config(i2c_bus->id, 0);
 321
 322         i2c_bus->active = true;
 323
 324         return 0;
 325 }
 326
 327 static const struct dm_i2c_ops s3c_i2c_ops = {
 328         .xfer           = s3c24x0_i2c_xfer,
 329         .probe_chip     = s3c24x0_i2c_probe,
 330         .set_bus_speed  = s3c24x0_i2c_set_bus_speed,
 331 };
 332
 333 static const struct udevice_id s3c_i2c_ids[] = {
 334         { .compatible = "samsung,s3c2440-i2c" },
 335         { }
 336 };
 337
 338 U_BOOT_DRIVER(i2c_s3c) = {
 339         .name   = "i2c_s3c",
 340         .id     = UCLASS_I2C,
 341         .of_match = s3c_i2c_ids,
 342         .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
 343         .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
 344         .ops    = &s3c_i2c_ops,
 345 };