drivers/i2c/s3c24x0_i2c.c

   1 /*
   2  * (C) Copyright 2002
   3  * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* This code should work for both the S3C2400 and the S3C2410
  25  * as they seem to have the same I2C controller inside.
  26  * The different address mapping is handled by the s3c24xx.h files below.
  27  */
  28
  29 #include <common.h>
  30 #ifdef CONFIG_EXYNOS5
  31 #include <asm/arch/clk.h>
  32 #include <asm/arch/cpu.h>
  33 #else
  34 #include <asm/arch/s3c24x0_cpu.h>
  35 #endif
  36 #include <asm/io.h>
  37 #include <i2c.h>
  38 #include "s3c24x0_i2c.h"
  39
  40 #ifdef CONFIG_HARD_I2C
  41
  42 #define I2C_WRITE       0
  43 #define I2C_READ        1
  44
  45 #define I2C_OK          0
  46 #define I2C_NOK         1
  47 #define I2C_NACK        2
  48 #define I2C_NOK_LA      3       /* Lost arbitration */
  49 #define I2C_NOK_TOUT    4       /* time out */
  50
  51 #define I2CSTAT_BSY     0x20    /* Busy bit */
  52 #define I2CSTAT_NACK    0x01    /* Nack bit */
  53 #define I2CCON_ACKGEN   0x80    /* Acknowledge generation */
  54 #define I2CCON_IRPND    0x10    /* Interrupt pending bit */
  55 #define I2C_MODE_MT     0xC0    /* Master Transmit Mode */
  56 #define I2C_MODE_MR     0x80    /* Master Receive Mode */
  57 #define I2C_START_STOP  0x20    /* START / STOP */
  58 #define I2C_TXRX_ENA    0x10    /* I2C Tx/Rx enable */
  59
  60 #define I2C_TIMEOUT 1           /* 1 second */
  61
  62
  63 static unsigned int g_current_bus;      /* Stores Current I2C Bus */
  64
  65 #ifndef CONFIG_EXYNOS5
  66 static int GetI2CSDA(void)
  67 {
  68         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
  69
  70 #ifdef CONFIG_S3C2410
  71         return (readl(&gpio->gpedat) & 0x8000) >> 15;
  72 #endif
  73 #ifdef CONFIG_S3C2400
  74         return (readl(&gpio->pgdat) & 0x0020) >> 5;
  75 #endif
  76 }
  77
  78 #if 0
  79 static void SetI2CSDA(int x)
  80 {
  81         rGPEDAT = (rGPEDAT & ~0x8000) | (x & 1) << 15;
  82 }
  83 #endif
  84
  85 static void SetI2CSCL(int x)
  86 {
  87         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
  88
  89 #ifdef CONFIG_S3C2410
  90         writel((readl(&gpio->gpedat) & ~0x4000) |
  91                                         (x & 1) << 14, &gpio->gpedat);
  92 #endif
  93 #ifdef CONFIG_S3C2400
  94         writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
  95 #endif
  96 }
  97 #endif
  98
  99 static int WaitForXfer(struct s3c24x0_i2c *i2c)
 100 {
 101         int i;
 102
 103         i = I2C_TIMEOUT * 10000;
 104         while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) {
 105                 udelay(100);
 106                 i--;
 107         }
 108
 109         return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
 110 }
 111
 112 static int IsACK(struct s3c24x0_i2c *i2c)
 113 {
 114         return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
 115 }
 116
 117 static void ReadWriteByte(struct s3c24x0_i2c *i2c)
 118 {
 119         writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
 120 }
 121
 122 static struct s3c24x0_i2c *get_base_i2c(void)
 123 {
 124 #ifdef CONFIG_EXYNOS5
 125         struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 126                                                         + (EXYNOS5_I2C_SPACING
 127                                                         * g_current_bus));
 128         return i2c;
 129 #else
 130         return s3c24x0_get_base_i2c();
 131 #endif
 132 }
 133
 134 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
 135 {
 136         ulong freq, pres = 16, div;
 137 #ifdef CONFIG_EXYNOS5
 138         freq = get_i2c_clk();
 139 #else
 140         freq = get_PCLK();
 141 #endif
 142         /* calculate prescaler and divisor values */
 143         if ((freq / pres / (16 + 1)) > speed)
 144                 /* set prescaler to 512 */
 145                 pres = 512;
 146
 147         div = 0;
 148         while ((freq / pres / (div + 1)) > speed)
 149                 div++;
 150
 151         /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
 152         writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
 153
 154         /* init to SLAVE REVEIVE and set slaveaddr */
 155         writel(0, &i2c->iicstat);
 156         writel(slaveadd, &i2c->iicadd);
 157         /* program Master Transmit (and implicit STOP) */
 158         writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 159 }
 160
 161 void i2c_init(int speed, int slaveadd)
 162 {
 163         struct s3c24x0_i2c *i2c;
 164 #ifndef CONFIG_EXYNOS5
 165         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 166 #endif
 167         int i;
 168
 169         /* By default i2c channel 0 is the current bus */
 170         g_current_bus = 0;
 171         i2c = get_base_i2c();
 172
 173         /* wait for some time to give previous transfer a chance to finish */
 174         i = I2C_TIMEOUT * 1000;
 175         while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
 176                 udelay(1000);
 177                 i--;
 178         }
 179
 180 #ifndef CONFIG_EXYNOS5
 181         if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
 182 #ifdef CONFIG_S3C2410
 183                 ulong old_gpecon = readl(&gpio->gpecon);
 184 #endif
 185 #ifdef CONFIG_S3C2400
 186                 ulong old_gpecon = readl(&gpio->pgcon);
 187 #endif
 188                 /* bus still busy probably by (most) previously interrupted
 189                    transfer */
 190
 191 #ifdef CONFIG_S3C2410
 192                 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
 193                 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
 194                        &gpio->gpecon);
 195 #endif
 196 #ifdef CONFIG_S3C2400
 197                 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
 198                 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
 199                        &gpio->pgcon);
 200 #endif
 201
 202                 /* toggle I2CSCL until bus idle */
 203                 SetI2CSCL(0);
 204                 udelay(1000);
 205                 i = 10;
 206                 while ((i > 0) && (GetI2CSDA() != 1)) {
 207                         SetI2CSCL(1);
 208                         udelay(1000);
 209                         SetI2CSCL(0);
 210                         udelay(1000);
 211                         i--;
 212                 }
 213                 SetI2CSCL(1);
 214                 udelay(1000);
 215
 216                 /* restore pin functions */
 217 #ifdef CONFIG_S3C2410
 218                 writel(old_gpecon, &gpio->gpecon);
 219 #endif
 220 #ifdef CONFIG_S3C2400
 221                 writel(old_gpecon, &gpio->pgcon);
 222 #endif
 223         }
 224 #endif /* #ifndef CONFIG_EXYNOS5 */
 225         i2c_ch_init(i2c, speed, slaveadd);
 226 }
 227
 228 /*
 229  * cmd_type is 0 for write, 1 for read.
 230  *
 231  * addr_len can take any value from 0-255, it is only limited
 232  * by the char, we could make it larger if needed. If it is
 233  * 0 we skip the address write cycle.
 234  */
 235 static int i2c_transfer(struct s3c24x0_i2c *i2c,
 236                         unsigned char cmd_type,
 237                         unsigned char chip,
 238                         unsigned char addr[],
 239                         unsigned char addr_len,
 240                         unsigned char data[],
 241                         unsigned short data_len)
 242 {
 243         int i, result;
 244
 245         if (data == 0 || data_len == 0) {
 246                 /*Don't support data transfer of no length or to address 0 */
 247                 debug("i2c_transfer: bad call\n");
 248                 return I2C_NOK;
 249         }
 250
 251         /* Check I2C bus idle */
 252         i = I2C_TIMEOUT * 1000;
 253         while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
 254                 udelay(1000);
 255                 i--;
 256         }
 257
 258         if (readl(&i2c->iicstat) & I2CSTAT_BSY)
 259                 return I2C_NOK_TOUT;
 260
 261         writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
 262         result = I2C_OK;
 263
 264         switch (cmd_type) {
 265         case I2C_WRITE:
 266                 if (addr && addr_len) {
 267                         writel(chip, &i2c->iicds);
 268                         /* send START */
 269                         writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
 270                                &i2c->iicstat);
 271                         i = 0;
 272                         while ((i < addr_len) && (result == I2C_OK)) {
 273                                 result = WaitForXfer(i2c);
 274                                 writel(addr[i], &i2c->iicds);
 275                                 ReadWriteByte(i2c);
 276                                 i++;
 277                         }
 278                         i = 0;
 279                         while ((i < data_len) && (result == I2C_OK)) {
 280                                 result = WaitForXfer(i2c);
 281                                 writel(data[i], &i2c->iicds);
 282                                 ReadWriteByte(i2c);
 283                                 i++;
 284                         }
 285                 } else {
 286                         writel(chip, &i2c->iicds);
 287                         /* send START */
 288                         writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
 289                                &i2c->iicstat);
 290                         i = 0;
 291                         while ((i < data_len) && (result = I2C_OK)) {
 292                                 result = WaitForXfer(i2c);
 293                                 writel(data[i], &i2c->iicds);
 294                                 ReadWriteByte(i2c);
 295                                 i++;
 296                         }
 297                 }
 298
 299                 if (result == I2C_OK)
 300                         result = WaitForXfer(i2c);
 301
 302                 /* send STOP */
 303                 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 304                 ReadWriteByte(i2c);
 305                 break;
 306
 307         case I2C_READ:
 308                 if (addr && addr_len) {
 309                         writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 310                         writel(chip, &i2c->iicds);
 311                         /* send START */
 312                         writel(readl(&i2c->iicstat) | I2C_START_STOP,
 313                                &i2c->iicstat);
 314                         result = WaitForXfer(i2c);
 315                         if (IsACK(i2c)) {
 316                                 i = 0;
 317                                 while ((i < addr_len) && (result == I2C_OK)) {
 318                                         writel(addr[i], &i2c->iicds);
 319                                         ReadWriteByte(i2c);
 320                                         result = WaitForXfer(i2c);
 321                                         i++;
 322                                 }
 323
 324                                 writel(chip, &i2c->iicds);
 325                                 /* resend START */
 326                                 writel(I2C_MODE_MR | I2C_TXRX_ENA |
 327                                        I2C_START_STOP, &i2c->iicstat);
 328                         ReadWriteByte(i2c);
 329                         result = WaitForXfer(i2c);
 330                                 i = 0;
 331                                 while ((i < data_len) && (result == I2C_OK)) {
 332                                         /* disable ACK for final READ */
 333                                         if (i == data_len - 1)
 334                                                 writel(readl(&i2c->iiccon)
 335                                                         & ~I2CCON_ACKGEN,
 336                                                         &i2c->iiccon);
 337                                 ReadWriteByte(i2c);
 338                                 result = WaitForXfer(i2c);
 339                                         data[i] = readl(&i2c->iicds);
 340                                         i++;
 341                                 }
 342                         } else {
 343                                 result = I2C_NACK;
 344                         }
 345
 346                 } else {
 347                         writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 348                         writel(chip, &i2c->iicds);
 349                         /* send START */
 350                         writel(readl(&i2c->iicstat) | I2C_START_STOP,
 351                                &i2c->iicstat);
 352                         result = WaitForXfer(i2c);
 353
 354                         if (IsACK(i2c)) {
 355                                 i = 0;
 356                                 while ((i < data_len) && (result == I2C_OK)) {
 357                                         /* disable ACK for final READ */
 358                                         if (i == data_len - 1)
 359                                                 writel(readl(&i2c->iiccon) &
 360                                                         ~I2CCON_ACKGEN,
 361                                                         &i2c->iiccon);
 362                                         ReadWriteByte(i2c);
 363                                         result = WaitForXfer(i2c);
 364                                         data[i] = readl(&i2c->iicds);
 365                                         i++;
 366                                 }
 367                         } else {
 368                                 result = I2C_NACK;
 369                         }
 370                 }
 371
 372                 /* send STOP */
 373                 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 374                 ReadWriteByte(i2c);
 375                 break;
 376
 377         default:
 378                 debug("i2c_transfer: bad call\n");
 379                 result = I2C_NOK;
 380                 break;
 381         }
 382
 383         return result;
 384 }
 385
 386 int i2c_probe(uchar chip)
 387 {
 388         struct s3c24x0_i2c *i2c;
 389         uchar buf[1];
 390
 391         i2c = get_base_i2c();
 392         buf[0] = 0;
 393
 394         /*
 395          * What is needed is to send the chip address and verify that the
 396          * address was <ACK>ed (i.e. there was a chip at that address which
 397          * drove the data line low).
 398          */
 399         return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
 400 }
 401
 402 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 403 {
 404         struct s3c24x0_i2c *i2c;
 405         uchar xaddr[4];
 406         int ret;
 407
 408         if (alen > 4) {
 409                 debug("I2C read: addr len %d not supported\n", alen);
 410                 return 1;
 411         }
 412
 413         if (alen > 0) {
 414                 xaddr[0] = (addr >> 24) & 0xFF;
 415                 xaddr[1] = (addr >> 16) & 0xFF;
 416                 xaddr[2] = (addr >> 8) & 0xFF;
 417                 xaddr[3] = addr & 0xFF;
 418         }
 419
 420 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 421         /*
 422          * EEPROM chips that implement "address overflow" are ones
 423          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 424          * address and the extra bits end up in the "chip address"
 425          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 426          * four 256 byte chips.
 427          *
 428          * Note that we consider the length of the address field to
 429          * still be one byte because the extra address bits are
 430          * hidden in the chip address.
 431          */
 432         if (alen > 0)
 433                 chip |= ((addr >> (alen * 8)) &
 434                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 435 #endif
 436         i2c = get_base_i2c();
 437         ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen,
 438                         buffer, len);
 439         if (ret != 0) {
 440                 debug("I2c read: failed %d\n", ret);
 441                 return 1;
 442         }
 443         return 0;
 444 }
 445
 446 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 447 {
 448         struct s3c24x0_i2c *i2c;
 449         uchar xaddr[4];
 450
 451         if (alen > 4) {
 452                 debug("I2C write: addr len %d not supported\n", alen);
 453                 return 1;
 454         }
 455
 456         if (alen > 0) {
 457                 xaddr[0] = (addr >> 24) & 0xFF;
 458                 xaddr[1] = (addr >> 16) & 0xFF;
 459                 xaddr[2] = (addr >> 8) & 0xFF;
 460                 xaddr[3] = addr & 0xFF;
 461         }
 462 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 463         /*
 464          * EEPROM chips that implement "address overflow" are ones
 465          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 466          * address and the extra bits end up in the "chip address"
 467          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 468          * four 256 byte chips.
 469          *
 470          * Note that we consider the length of the address field to
 471          * still be one byte because the extra address bits are
 472          * hidden in the chip address.
 473          */
 474         if (alen > 0)
 475                 chip |= ((addr >> (alen * 8)) &
 476                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 477 #endif
 478         i2c = get_base_i2c();
 479         return (i2c_transfer
 480                 (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
 481                  len) != 0);
 482 }
 483 #endif /* CONFIG_HARD_I2C */