drivers/i2c/s3c24x0_i2c.c

   1 /*
   2  * (C) Copyright 2002
   3  * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* This code should work for both the S3C2400 and the S3C2410
  25  * as they seem to have the same I2C controller inside.
  26  * The different address mapping is handled by the s3c24xx.h files below.
  27  */
  28
  29 #include <common.h>
  30 #include <fdtdec.h>
  31 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  32 #include <asm/arch/clk.h>
  33 #include <asm/arch/cpu.h>
  34 #include <asm/arch/pinmux.h>
  35 #else
  36 #include <asm/arch/s3c24x0_cpu.h>
  37 #endif
  38 #include <asm/io.h>
  39 #include <i2c.h>
  40 #include "s3c24x0_i2c.h"
  41
  42 #ifdef CONFIG_HARD_I2C
  43
  44 #define I2C_WRITE       0
  45 #define I2C_READ        1
  46
  47 #define I2C_OK          0
  48 #define I2C_NOK         1
  49 #define I2C_NACK        2
  50 #define I2C_NOK_LA      3       /* Lost arbitration */
  51 #define I2C_NOK_TOUT    4       /* time out */
  52
  53 #define I2CSTAT_BSY     0x20    /* Busy bit */
  54 #define I2CSTAT_NACK    0x01    /* Nack bit */
  55 #define I2CCON_ACKGEN   0x80    /* Acknowledge generation */
  56 #define I2CCON_IRPND    0x10    /* Interrupt pending bit */
  57 #define I2C_MODE_MT     0xC0    /* Master Transmit Mode */
  58 #define I2C_MODE_MR     0x80    /* Master Receive Mode */
  59 #define I2C_START_STOP  0x20    /* START / STOP */
  60 #define I2C_TXRX_ENA    0x10    /* I2C Tx/Rx enable */
  61
  62 #define I2C_TIMEOUT 1           /* 1 second */
  63
  64
  65 /*
  66  * For SPL boot some boards need i2c before SDRAM is initialised so force
  67  * variables to live in SRAM
  68  */
  69 static unsigned int g_current_bus __attribute__((section(".data")));
  70 static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
  71                         __attribute__((section(".data")));
  72 static int i2c_busses __attribute__((section(".data")));
  73
  74 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  75 static int GetI2CSDA(void)
  76 {
  77         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
  78
  79 #ifdef CONFIG_S3C2410
  80         return (readl(&gpio->gpedat) & 0x8000) >> 15;
  81 #endif
  82 #ifdef CONFIG_S3C2400
  83         return (readl(&gpio->pgdat) & 0x0020) >> 5;
  84 #endif
  85 }
  86
  87 #if 0
  88 static void SetI2CSDA(int x)
  89 {
  90         rGPEDAT = (rGPEDAT & ~0x8000) | (x & 1) << 15;
  91 }
  92 #endif
  93
  94 static void SetI2CSCL(int x)
  95 {
  96         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
  97
  98 #ifdef CONFIG_S3C2410
  99         writel((readl(&gpio->gpedat) & ~0x4000) |
 100                                         (x & 1) << 14, &gpio->gpedat);
 101 #endif
 102 #ifdef CONFIG_S3C2400
 103         writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
 104 #endif
 105 }
 106 #endif
 107
 108 static int WaitForXfer(struct s3c24x0_i2c *i2c)
 109 {
 110         int i;
 111
 112         i = I2C_TIMEOUT * 10000;
 113         while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) {
 114                 udelay(100);
 115                 i--;
 116         }
 117
 118         return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
 119 }
 120
 121 static int IsACK(struct s3c24x0_i2c *i2c)
 122 {
 123         return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
 124 }
 125
 126 static void ReadWriteByte(struct s3c24x0_i2c *i2c)
 127 {
 128         writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
 129 }
 130
 131 static struct s3c24x0_i2c *get_base_i2c(void)
 132 {
 133 #ifdef CONFIG_EXYNOS4
 134         struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 135                                                         + (EXYNOS4_I2C_SPACING
 136                                                         * g_current_bus));
 137         return i2c;
 138 #elif defined CONFIG_EXYNOS5
 139         struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 140                                                         + (EXYNOS5_I2C_SPACING
 141                                                         * g_current_bus));
 142         return i2c;
 143 #else
 144         return s3c24x0_get_base_i2c();
 145 #endif
 146 }
 147
 148 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
 149 {
 150         ulong freq, pres = 16, div;
 151 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 152         freq = get_i2c_clk();
 153 #else
 154         freq = get_PCLK();
 155 #endif
 156         /* calculate prescaler and divisor values */
 157         if ((freq / pres / (16 + 1)) > speed)
 158                 /* set prescaler to 512 */
 159                 pres = 512;
 160
 161         div = 0;
 162         while ((freq / pres / (div + 1)) > speed)
 163                 div++;
 164
 165         /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
 166         writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
 167
 168         /* init to SLAVE REVEIVE and set slaveaddr */
 169         writel(0, &i2c->iicstat);
 170         writel(slaveadd, &i2c->iicadd);
 171         /* program Master Transmit (and implicit STOP) */
 172         writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 173 }
 174
 175 /*
 176  * MULTI BUS I2C support
 177  */
 178
 179 #ifdef CONFIG_I2C_MULTI_BUS
 180 int i2c_set_bus_num(unsigned int bus)
 181 {
 182         struct s3c24x0_i2c *i2c;
 183
 184         if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) {
 185                 debug("Bad bus: %d\n", bus);
 186                 return -1;
 187         }
 188
 189         g_current_bus = bus;
 190         i2c = get_base_i2c();
 191         i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 192
 193         return 0;
 194 }
 195
 196 unsigned int i2c_get_bus_num(void)
 197 {
 198         return g_current_bus;
 199 }
 200 #endif
 201
 202 void i2c_init(int speed, int slaveadd)
 203 {
 204         struct s3c24x0_i2c *i2c;
 205 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 206         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 207 #endif
 208         int i;
 209
 210         /* By default i2c channel 0 is the current bus */
 211         g_current_bus = 0;
 212         i2c = get_base_i2c();
 213
 214         /* wait for some time to give previous transfer a chance to finish */
 215         i = I2C_TIMEOUT * 1000;
 216         while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
 217                 udelay(1000);
 218                 i--;
 219         }
 220
 221 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 222         if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
 223 #ifdef CONFIG_S3C2410
 224                 ulong old_gpecon = readl(&gpio->gpecon);
 225 #endif
 226 #ifdef CONFIG_S3C2400
 227                 ulong old_gpecon = readl(&gpio->pgcon);
 228 #endif
 229                 /* bus still busy probably by (most) previously interrupted
 230                    transfer */
 231
 232 #ifdef CONFIG_S3C2410
 233                 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
 234                 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
 235                        &gpio->gpecon);
 236 #endif
 237 #ifdef CONFIG_S3C2400
 238                 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
 239                 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
 240                        &gpio->pgcon);
 241 #endif
 242
 243                 /* toggle I2CSCL until bus idle */
 244                 SetI2CSCL(0);
 245                 udelay(1000);
 246                 i = 10;
 247                 while ((i > 0) && (GetI2CSDA() != 1)) {
 248                         SetI2CSCL(1);
 249                         udelay(1000);
 250                         SetI2CSCL(0);
 251                         udelay(1000);
 252                         i--;
 253                 }
 254                 SetI2CSCL(1);
 255                 udelay(1000);
 256
 257                 /* restore pin functions */
 258 #ifdef CONFIG_S3C2410
 259                 writel(old_gpecon, &gpio->gpecon);
 260 #endif
 261 #ifdef CONFIG_S3C2400
 262                 writel(old_gpecon, &gpio->pgcon);
 263 #endif
 264         }
 265 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
 266         i2c_ch_init(i2c, speed, slaveadd);
 267 }
 268
 269 /*
 270  * cmd_type is 0 for write, 1 for read.
 271  *
 272  * addr_len can take any value from 0-255, it is only limited
 273  * by the char, we could make it larger if needed. If it is
 274  * 0 we skip the address write cycle.
 275  */
 276 static int i2c_transfer(struct s3c24x0_i2c *i2c,
 277                         unsigned char cmd_type,
 278                         unsigned char chip,
 279                         unsigned char addr[],
 280                         unsigned char addr_len,
 281                         unsigned char data[],
 282                         unsigned short data_len)
 283 {
 284         int i, result;
 285
 286         if (data == 0 || data_len == 0) {
 287                 /*Don't support data transfer of no length or to address 0 */
 288                 debug("i2c_transfer: bad call\n");
 289                 return I2C_NOK;
 290         }
 291
 292         /* Check I2C bus idle */
 293         i = I2C_TIMEOUT * 1000;
 294         while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
 295                 udelay(1000);
 296                 i--;
 297         }
 298
 299         if (readl(&i2c->iicstat) & I2CSTAT_BSY)
 300                 return I2C_NOK_TOUT;
 301
 302         writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
 303         result = I2C_OK;
 304
 305         switch (cmd_type) {
 306         case I2C_WRITE:
 307                 if (addr && addr_len) {
 308                         writel(chip, &i2c->iicds);
 309                         /* send START */
 310                         writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
 311                                &i2c->iicstat);
 312                         i = 0;
 313                         while ((i < addr_len) && (result == I2C_OK)) {
 314                                 result = WaitForXfer(i2c);
 315                                 writel(addr[i], &i2c->iicds);
 316                                 ReadWriteByte(i2c);
 317                                 i++;
 318                         }
 319                         i = 0;
 320                         while ((i < data_len) && (result == I2C_OK)) {
 321                                 result = WaitForXfer(i2c);
 322                                 writel(data[i], &i2c->iicds);
 323                                 ReadWriteByte(i2c);
 324                                 i++;
 325                         }
 326                 } else {
 327                         writel(chip, &i2c->iicds);
 328                         /* send START */
 329                         writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
 330                                &i2c->iicstat);
 331                         i = 0;
 332                         while ((i < data_len) && (result = I2C_OK)) {
 333                                 result = WaitForXfer(i2c);
 334                                 writel(data[i], &i2c->iicds);
 335                                 ReadWriteByte(i2c);
 336                                 i++;
 337                         }
 338                 }
 339
 340                 if (result == I2C_OK)
 341                         result = WaitForXfer(i2c);
 342
 343                 /* send STOP */
 344                 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 345                 ReadWriteByte(i2c);
 346                 break;
 347
 348         case I2C_READ:
 349                 if (addr && addr_len) {
 350                         writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 351                         writel(chip, &i2c->iicds);
 352                         /* send START */
 353                         writel(readl(&i2c->iicstat) | I2C_START_STOP,
 354                                &i2c->iicstat);
 355                         result = WaitForXfer(i2c);
 356                         if (IsACK(i2c)) {
 357                                 i = 0;
 358                                 while ((i < addr_len) && (result == I2C_OK)) {
 359                                         writel(addr[i], &i2c->iicds);
 360                                         ReadWriteByte(i2c);
 361                                         result = WaitForXfer(i2c);
 362                                         i++;
 363                                 }
 364
 365                                 writel(chip, &i2c->iicds);
 366                                 /* resend START */
 367                                 writel(I2C_MODE_MR | I2C_TXRX_ENA |
 368                                        I2C_START_STOP, &i2c->iicstat);
 369                         ReadWriteByte(i2c);
 370                         result = WaitForXfer(i2c);
 371                                 i = 0;
 372                                 while ((i < data_len) && (result == I2C_OK)) {
 373                                         /* disable ACK for final READ */
 374                                         if (i == data_len - 1)
 375                                                 writel(readl(&i2c->iiccon)
 376                                                         & ~I2CCON_ACKGEN,
 377                                                         &i2c->iiccon);
 378                                 ReadWriteByte(i2c);
 379                                 result = WaitForXfer(i2c);
 380                                         data[i] = readl(&i2c->iicds);
 381                                         i++;
 382                                 }
 383                         } else {
 384                                 result = I2C_NACK;
 385                         }
 386
 387                 } else {
 388                         writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 389                         writel(chip, &i2c->iicds);
 390                         /* send START */
 391                         writel(readl(&i2c->iicstat) | I2C_START_STOP,
 392                                &i2c->iicstat);
 393                         result = WaitForXfer(i2c);
 394
 395                         if (IsACK(i2c)) {
 396                                 i = 0;
 397                                 while ((i < data_len) && (result == I2C_OK)) {
 398                                         /* disable ACK for final READ */
 399                                         if (i == data_len - 1)
 400                                                 writel(readl(&i2c->iiccon) &
 401                                                         ~I2CCON_ACKGEN,
 402                                                         &i2c->iiccon);
 403                                         ReadWriteByte(i2c);
 404                                         result = WaitForXfer(i2c);
 405                                         data[i] = readl(&i2c->iicds);
 406                                         i++;
 407                                 }
 408                         } else {
 409                                 result = I2C_NACK;
 410                         }
 411                 }
 412
 413                 /* send STOP */
 414                 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 415                 ReadWriteByte(i2c);
 416                 break;
 417
 418         default:
 419                 debug("i2c_transfer: bad call\n");
 420                 result = I2C_NOK;
 421                 break;
 422         }
 423
 424         return result;
 425 }
 426
 427 int i2c_probe(uchar chip)
 428 {
 429         struct s3c24x0_i2c *i2c;
 430         uchar buf[1];
 431
 432         i2c = get_base_i2c();
 433         buf[0] = 0;
 434
 435         /*
 436          * What is needed is to send the chip address and verify that the
 437          * address was <ACK>ed (i.e. there was a chip at that address which
 438          * drove the data line low).
 439          */
 440         return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
 441 }
 442
 443 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 444 {
 445         struct s3c24x0_i2c *i2c;
 446         uchar xaddr[4];
 447         int ret;
 448
 449         if (alen > 4) {
 450                 debug("I2C read: addr len %d not supported\n", alen);
 451                 return 1;
 452         }
 453
 454         if (alen > 0) {
 455                 xaddr[0] = (addr >> 24) & 0xFF;
 456                 xaddr[1] = (addr >> 16) & 0xFF;
 457                 xaddr[2] = (addr >> 8) & 0xFF;
 458                 xaddr[3] = addr & 0xFF;
 459         }
 460
 461 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 462         /*
 463          * EEPROM chips that implement "address overflow" are ones
 464          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 465          * address and the extra bits end up in the "chip address"
 466          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 467          * four 256 byte chips.
 468          *
 469          * Note that we consider the length of the address field to
 470          * still be one byte because the extra address bits are
 471          * hidden in the chip address.
 472          */
 473         if (alen > 0)
 474                 chip |= ((addr >> (alen * 8)) &
 475                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 476 #endif
 477         i2c = get_base_i2c();
 478         ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen,
 479                         buffer, len);
 480         if (ret != 0) {
 481                 debug("I2c read: failed %d\n", ret);
 482                 return 1;
 483         }
 484         return 0;
 485 }
 486
 487 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 488 {
 489         struct s3c24x0_i2c *i2c;
 490         uchar xaddr[4];
 491
 492         if (alen > 4) {
 493                 debug("I2C write: addr len %d not supported\n", alen);
 494                 return 1;
 495         }
 496
 497         if (alen > 0) {
 498                 xaddr[0] = (addr >> 24) & 0xFF;
 499                 xaddr[1] = (addr >> 16) & 0xFF;
 500                 xaddr[2] = (addr >> 8) & 0xFF;
 501                 xaddr[3] = addr & 0xFF;
 502         }
 503 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 504         /*
 505          * EEPROM chips that implement "address overflow" are ones
 506          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 507          * address and the extra bits end up in the "chip address"
 508          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 509          * four 256 byte chips.
 510          *
 511          * Note that we consider the length of the address field to
 512          * still be one byte because the extra address bits are
 513          * hidden in the chip address.
 514          */
 515         if (alen > 0)
 516                 chip |= ((addr >> (alen * 8)) &
 517                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 518 #endif
 519         i2c = get_base_i2c();
 520         return (i2c_transfer
 521                 (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
 522                  len) != 0);
 523 }
 524
 525 #ifdef CONFIG_OF_CONTROL
 526 void board_i2c_init(const void *blob)
 527 {
 528         int node_list[CONFIG_MAX_I2C_NUM];
 529         int count, i;
 530
 531         count = fdtdec_find_aliases_for_id(blob, "i2c",
 532                 COMPAT_SAMSUNG_S3C2440_I2C, node_list,
 533                 CONFIG_MAX_I2C_NUM);
 534
 535         for (i = 0; i < count; i++) {
 536                 struct s3c24x0_i2c_bus *bus;
 537                 int node = node_list[i];
 538
 539                 if (node <= 0)
 540                         continue;
 541                 bus = &i2c_bus[i];
 542                 bus->regs = (struct s3c24x0_i2c *)
 543                         fdtdec_get_addr(blob, node, "reg");
 544                 bus->id = pinmux_decode_periph_id(blob, node);
 545                 bus->node = node;
 546                 bus->bus_num = i2c_busses++;
 547                 exynos_pinmux_config(bus->id, 0);
 548         }
 549 }
 550
 551 static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
 552 {
 553         if (bus_idx < i2c_busses)
 554                 return &i2c_bus[bus_idx];
 555
 556         debug("Undefined bus: %d\n", bus_idx);
 557         return NULL;
 558 }
 559
 560 int i2c_get_bus_num_fdt(int node)
 561 {
 562         int i;
 563
 564         for (i = 0; i < i2c_busses; i++) {
 565                 if (node == i2c_bus[i].node)
 566                         return i;
 567         }
 568
 569         debug("%s: Can't find any matched I2C bus\n", __func__);
 570         return -1;
 571 }
 572
 573 int i2c_reset_port_fdt(const void *blob, int node)
 574 {
 575         struct s3c24x0_i2c_bus *i2c;
 576         int bus;
 577
 578         bus = i2c_get_bus_num_fdt(node);
 579         if (bus < 0) {
 580                 debug("could not get bus for node %d\n", node);
 581                 return -1;
 582         }
 583
 584         i2c = get_bus(bus);
 585         if (!i2c) {
 586                 debug("get_bus() failed for node node %d\n", node);
 587                 return -1;
 588         }
 589
 590         i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 591
 592         return 0;
 593 }
 594 #endif
 595
 596 #endif /* CONFIG_HARD_I2C */