drivers/i2c/s3c24x0_i2c.c

   1 /*
   2  * (C) Copyright 2002
   3  * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /* This code should work for both the S3C2400 and the S3C2410
   9  * as they seem to have the same I2C controller inside.
  10  * The different address mapping is handled by the s3c24xx.h files below.
  11  */
  12
  13 #include <common.h>
  14 #include <fdtdec.h>
  15 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  16 #include <asm/arch/clk.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/pinmux.h>
  19 #else
  20 #include <asm/arch/s3c24x0_cpu.h>
  21 #endif
  22 #include <asm/io.h>
  23 #include <i2c.h>
  24 #include "s3c24x0_i2c.h"
  25
  26 #define I2C_WRITE       0
  27 #define I2C_READ        1
  28
  29 #define I2C_OK          0
  30 #define I2C_NOK         1
  31 #define I2C_NACK        2
  32 #define I2C_NOK_LA      3       /* Lost arbitration */
  33 #define I2C_NOK_TOUT    4       /* time out */
  34
  35 /* HSI2C specific register description */
  36
  37 /* I2C_CTL Register bits */
  38 #define HSI2C_FUNC_MODE_I2C             (1u << 0)
  39 #define HSI2C_MASTER                    (1u << 3)
  40 #define HSI2C_RXCHON                    (1u << 6)       /* Write/Send */
  41 #define HSI2C_TXCHON                    (1u << 7)       /* Read/Receive */
  42 #define HSI2C_SW_RST                    (1u << 31)
  43
  44 /* I2C_FIFO_CTL Register bits */
  45 #define HSI2C_RXFIFO_EN                 (1u << 0)
  46 #define HSI2C_TXFIFO_EN                 (1u << 1)
  47 #define HSI2C_TXFIFO_TRIGGER_LEVEL      (0x20 << 16)
  48 #define HSI2C_RXFIFO_TRIGGER_LEVEL      (0x20 << 4)
  49
  50 /* I2C_TRAILING_CTL Register bits */
  51 #define HSI2C_TRAILING_COUNT            (0xff)
  52
  53 /* I2C_INT_EN Register bits */
  54 #define HSI2C_TX_UNDERRUN_EN            (1u << 2)
  55 #define HSI2C_TX_OVERRUN_EN             (1u << 3)
  56 #define HSI2C_RX_UNDERRUN_EN            (1u << 4)
  57 #define HSI2C_RX_OVERRUN_EN             (1u << 5)
  58 #define HSI2C_INT_TRAILING_EN           (1u << 6)
  59 #define HSI2C_INT_I2C_EN                (1u << 9)
  60
  61 #define HSI2C_INT_ERROR_MASK    (HSI2C_TX_UNDERRUN_EN |\
  62                                  HSI2C_TX_OVERRUN_EN  |\
  63                                  HSI2C_RX_UNDERRUN_EN |\
  64                                  HSI2C_RX_OVERRUN_EN  |\
  65                                  HSI2C_INT_TRAILING_EN)
  66
  67 /* I2C_CONF Register bits */
  68 #define HSI2C_AUTO_MODE                 (1u << 31)
  69 #define HSI2C_10BIT_ADDR_MODE           (1u << 30)
  70 #define HSI2C_HS_MODE                   (1u << 29)
  71
  72 /* I2C_AUTO_CONF Register bits */
  73 #define HSI2C_READ_WRITE                (1u << 16)
  74 #define HSI2C_STOP_AFTER_TRANS          (1u << 17)
  75 #define HSI2C_MASTER_RUN                (1u << 31)
  76
  77 /* I2C_TIMEOUT Register bits */
  78 #define HSI2C_TIMEOUT_EN                (1u << 31)
  79
  80 /* I2C_TRANS_STATUS register bits */
  81 #define HSI2C_MASTER_BUSY               (1u << 17)
  82 #define HSI2C_SLAVE_BUSY                (1u << 16)
  83 #define HSI2C_TIMEOUT_AUTO              (1u << 4)
  84 #define HSI2C_NO_DEV                    (1u << 3)
  85 #define HSI2C_NO_DEV_ACK                (1u << 2)
  86 #define HSI2C_TRANS_ABORT               (1u << 1)
  87 #define HSI2C_TRANS_SUCCESS             (1u << 0)
  88 #define HSI2C_TRANS_ERROR_MASK  (HSI2C_TIMEOUT_AUTO |\
  89                                  HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\
  90                                  HSI2C_TRANS_ABORT)
  91 #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)
  92
  93
  94 /* I2C_FIFO_STAT Register bits */
  95 #define HSI2C_RX_FIFO_EMPTY             (1u << 24)
  96 #define HSI2C_RX_FIFO_FULL              (1u << 23)
  97 #define HSI2C_TX_FIFO_EMPTY             (1u << 8)
  98 #define HSI2C_TX_FIFO_FULL              (1u << 7)
  99 #define HSI2C_RX_FIFO_LEVEL(x)          (((x) >> 16) & 0x7f)
 100 #define HSI2C_TX_FIFO_LEVEL(x)          ((x) & 0x7f)
 101
 102 #define HSI2C_SLV_ADDR_MAS(x)           ((x & 0x3ff) << 10)
 103
 104 /* S3C I2C Controller bits */
 105 #define I2CSTAT_BSY     0x20    /* Busy bit */
 106 #define I2CSTAT_NACK    0x01    /* Nack bit */
 107 #define I2CCON_ACKGEN   0x80    /* Acknowledge generation */
 108 #define I2CCON_IRPND    0x10    /* Interrupt pending bit */
 109 #define I2C_MODE_MT     0xC0    /* Master Transmit Mode */
 110 #define I2C_MODE_MR     0x80    /* Master Receive Mode */
 111 #define I2C_START_STOP  0x20    /* START / STOP */
 112 #define I2C_TXRX_ENA    0x10    /* I2C Tx/Rx enable */
 113
 114 #define I2C_TIMEOUT_MS 1000             /* 1 second */
 115
 116 #define HSI2C_TIMEOUT_US 100000 /* 100 ms, finer granularity */
 117
 118
 119 /* To support VCMA9 boards and other who dont define max_i2c_num */
 120 #ifndef CONFIG_MAX_I2C_NUM
 121 #define CONFIG_MAX_I2C_NUM 1
 122 #endif
 123
 124 /*
 125  * For SPL boot some boards need i2c before SDRAM is initialised so force
 126  * variables to live in SRAM
 127  */
 128 static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
 129                         __attribute__((section(".data")));
 130
 131 /**
 132  * Get a pointer to the given bus index
 133  *
 134  * @bus_idx: Bus index to look up
 135  * @return pointer to bus, or NULL if invalid or not available
 136  */
 137 static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
 138 {
 139         if (bus_idx < ARRAY_SIZE(i2c_bus)) {
 140                 struct s3c24x0_i2c_bus *bus;
 141
 142                 bus = &i2c_bus[bus_idx];
 143                 if (bus->active)
 144                         return bus;
 145         }
 146
 147         debug("Undefined bus: %d\n", bus_idx);
 148         return NULL;
 149 }
 150
 151 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 152 static int GetI2CSDA(void)
 153 {
 154         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 155
 156 #ifdef CONFIG_S3C2410
 157         return (readl(&gpio->gpedat) & 0x8000) >> 15;
 158 #endif
 159 #ifdef CONFIG_S3C2400
 160         return (readl(&gpio->pgdat) & 0x0020) >> 5;
 161 #endif
 162 }
 163
 164 static void SetI2CSCL(int x)
 165 {
 166         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 167
 168 #ifdef CONFIG_S3C2410
 169         writel((readl(&gpio->gpedat) & ~0x4000) |
 170                                         (x & 1) << 14, &gpio->gpedat);
 171 #endif
 172 #ifdef CONFIG_S3C2400
 173         writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
 174 #endif
 175 }
 176 #endif
 177
 178 /*
 179  * Wait til the byte transfer is completed.
 180  *
 181  * @param i2c- pointer to the appropriate i2c register bank.
 182  * @return I2C_OK, if transmission was ACKED
 183  *         I2C_NACK, if transmission was NACKED
 184  *         I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
 185  */
 186
 187 static int WaitForXfer(struct s3c24x0_i2c *i2c)
 188 {
 189         ulong start_time = get_timer(0);
 190
 191         do {
 192                 if (readl(&i2c->iiccon) & I2CCON_IRPND)
 193                         return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
 194                                 I2C_NACK : I2C_OK;
 195         } while (get_timer(start_time) < I2C_TIMEOUT_MS);
 196
 197         return I2C_NOK_TOUT;
 198 }
 199
 200 /*
 201  * Wait for transfer completion.
 202  *
 203  * This function reads the interrupt status register waiting for the INT_I2C
 204  * bit to be set, which indicates copletion of a transaction.
 205  *
 206  * @param i2c: pointer to the appropriate register bank
 207  *
 208  * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case
 209  *          the status bits do not get set in time, or an approrpiate error
 210  *          value in case of transfer errors.
 211  */
 212 static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c)
 213 {
 214         int i = HSI2C_TIMEOUT_US;
 215
 216         while (i-- > 0) {
 217                 u32 int_status = readl(&i2c->usi_int_stat);
 218
 219                 if (int_status & HSI2C_INT_I2C_EN) {
 220                         u32 trans_status = readl(&i2c->usi_trans_status);
 221
 222                         /* Deassert pending interrupt. */
 223                         writel(int_status, &i2c->usi_int_stat);
 224
 225                         if (trans_status & HSI2C_NO_DEV_ACK) {
 226                                 debug("%s: no ACK from device\n", __func__);
 227                                 return I2C_NACK;
 228                         }
 229                         if (trans_status & HSI2C_NO_DEV) {
 230                                 debug("%s: no device\n", __func__);
 231                                 return I2C_NOK;
 232                         }
 233                         if (trans_status & HSI2C_TRANS_ABORT) {
 234                                 debug("%s: arbitration lost\n", __func__);
 235                                 return I2C_NOK_LA;
 236                         }
 237                         if (trans_status & HSI2C_TIMEOUT_AUTO) {
 238                                 debug("%s: device timed out\n", __func__);
 239                                 return I2C_NOK_TOUT;
 240                         }
 241                         return I2C_OK;
 242                 }
 243                 udelay(1);
 244         }
 245         debug("%s: transaction timeout!\n", __func__);
 246         return I2C_NOK_TOUT;
 247 }
 248
 249 static void ReadWriteByte(struct s3c24x0_i2c *i2c)
 250 {
 251         writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
 252 }
 253
 254 static struct s3c24x0_i2c *get_base_i2c(int bus)
 255 {
 256 #ifdef CONFIG_EXYNOS4
 257         struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 258                                                         + (EXYNOS4_I2C_SPACING
 259                                                         * bus));
 260         return i2c;
 261 #elif defined CONFIG_EXYNOS5
 262         struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 263                                                         + (EXYNOS5_I2C_SPACING
 264                                                         * bus));
 265         return i2c;
 266 #else
 267         return s3c24x0_get_base_i2c();
 268 #endif
 269 }
 270
 271 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
 272 {
 273         ulong freq, pres = 16, div;
 274 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 275         freq = get_i2c_clk();
 276 #else
 277         freq = get_PCLK();
 278 #endif
 279         /* calculate prescaler and divisor values */
 280         if ((freq / pres / (16 + 1)) > speed)
 281                 /* set prescaler to 512 */
 282                 pres = 512;
 283
 284         div = 0;
 285         while ((freq / pres / (div + 1)) > speed)
 286                 div++;
 287
 288         /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
 289         writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
 290
 291         /* init to SLAVE REVEIVE and set slaveaddr */
 292         writel(0, &i2c->iicstat);
 293         writel(slaveadd, &i2c->iicadd);
 294         /* program Master Transmit (and implicit STOP) */
 295         writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 296 }
 297
 298 static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
 299 {
 300         struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
 301         ulong clkin;
 302         unsigned int op_clk = i2c_bus->clock_frequency;
 303         unsigned int i = 0, utemp0 = 0, utemp1 = 0;
 304         unsigned int t_ftl_cycle;
 305
 306 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 307         clkin = get_i2c_clk();
 308 #else
 309         clkin = get_PCLK();
 310 #endif
 311         /* FPCLK / FI2C =
 312          * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
 313          * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
 314          * uTemp1 = (TSCLK_L + TSCLK_H + 2)
 315          * uTemp2 = TSCLK_L + TSCLK_H
 316          */
 317         t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7;
 318         utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
 319
 320         /* CLK_DIV max is 256 */
 321         for (i = 0; i < 256; i++) {
 322                 utemp1 = utemp0 / (i + 1);
 323                 if ((utemp1 < 512) && (utemp1 > 4)) {
 324                         i2c_bus->clk_cycle = utemp1 - 2;
 325                         i2c_bus->clk_div = i;
 326                         return 0;
 327                 }
 328         }
 329         return -1;
 330 }
 331
 332 static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
 333 {
 334         struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
 335         unsigned int t_sr_release;
 336         unsigned int n_clkdiv;
 337         unsigned int t_start_su, t_start_hd;
 338         unsigned int t_stop_su;
 339         unsigned int t_data_su, t_data_hd;
 340         unsigned int t_scl_l, t_scl_h;
 341         u32 i2c_timing_s1;
 342         u32 i2c_timing_s2;
 343         u32 i2c_timing_s3;
 344         u32 i2c_timing_sla;
 345
 346         n_clkdiv = i2c_bus->clk_div;
 347         t_scl_l = i2c_bus->clk_cycle / 2;
 348         t_scl_h = i2c_bus->clk_cycle / 2;
 349         t_start_su = t_scl_l;
 350         t_start_hd = t_scl_l;
 351         t_stop_su = t_scl_l;
 352         t_data_su = t_scl_l / 2;
 353         t_data_hd = t_scl_l / 2;
 354         t_sr_release = i2c_bus->clk_cycle;
 355
 356         i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
 357         i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
 358         i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
 359         i2c_timing_sla = t_data_hd << 0;
 360
 361         writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl);
 362
 363         /* Clear to enable Timeout */
 364         clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0);
 365
 366         /* set AUTO mode */
 367         writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
 368
 369         /* Enable completion conditions' reporting. */
 370         writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en);
 371
 372         /* Enable FIFOs */
 373         writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
 374
 375         /* Currently operating in Fast speed mode. */
 376         writel(i2c_timing_s1, &hsregs->usi_timing_fs1);
 377         writel(i2c_timing_s2, &hsregs->usi_timing_fs2);
 378         writel(i2c_timing_s3, &hsregs->usi_timing_fs3);
 379         writel(i2c_timing_sla, &hsregs->usi_timing_sla);
 380 }
 381
 382 /* SW reset for the high speed bus */
 383 static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
 384 {
 385         struct exynos5_hsi2c *i2c = i2c_bus->hsregs;
 386         u32 i2c_ctl;
 387
 388         /* Set and clear the bit for reset */
 389         i2c_ctl = readl(&i2c->usi_ctl);
 390         i2c_ctl |= HSI2C_SW_RST;
 391         writel(i2c_ctl, &i2c->usi_ctl);
 392
 393         i2c_ctl = readl(&i2c->usi_ctl);
 394         i2c_ctl &= ~HSI2C_SW_RST;
 395         writel(i2c_ctl, &i2c->usi_ctl);
 396
 397         /* Initialize the configure registers */
 398         hsi2c_ch_init(i2c_bus);
 399 }
 400
 401 static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 402 {
 403         struct s3c24x0_i2c *i2c;
 404         struct s3c24x0_i2c_bus *bus;
 405
 406 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 407         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 408 #endif
 409         ulong start_time = get_timer(0);
 410
 411         /* By default i2c channel 0 is the current bus */
 412         i2c = get_base_i2c(adap->hwadapnr);
 413
 414         /*
 415          * In case the previous transfer is still going, wait to give it a
 416          * chance to finish.
 417          */
 418         while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
 419                 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
 420                         printf("%s: I2C bus busy for %p\n", __func__,
 421                                &i2c->iicstat);
 422                         return;
 423                 }
 424         }
 425
 426 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 427         int i;
 428
 429         if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
 430 #ifdef CONFIG_S3C2410
 431                 ulong old_gpecon = readl(&gpio->gpecon);
 432 #endif
 433 #ifdef CONFIG_S3C2400
 434                 ulong old_gpecon = readl(&gpio->pgcon);
 435 #endif
 436                 /* bus still busy probably by (most) previously interrupted
 437                    transfer */
 438
 439 #ifdef CONFIG_S3C2410
 440                 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
 441                 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
 442                        &gpio->gpecon);
 443 #endif
 444 #ifdef CONFIG_S3C2400
 445                 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
 446                 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
 447                        &gpio->pgcon);
 448 #endif
 449
 450                 /* toggle I2CSCL until bus idle */
 451                 SetI2CSCL(0);
 452                 udelay(1000);
 453                 i = 10;
 454                 while ((i > 0) && (GetI2CSDA() != 1)) {
 455                         SetI2CSCL(1);
 456                         udelay(1000);
 457                         SetI2CSCL(0);
 458                         udelay(1000);
 459                         i--;
 460                 }
 461                 SetI2CSCL(1);
 462                 udelay(1000);
 463
 464                 /* restore pin functions */
 465 #ifdef CONFIG_S3C2410
 466                 writel(old_gpecon, &gpio->gpecon);
 467 #endif
 468 #ifdef CONFIG_S3C2400
 469                 writel(old_gpecon, &gpio->pgcon);
 470 #endif
 471         }
 472 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
 473         i2c_ch_init(i2c, speed, slaveadd);
 474
 475         bus = &i2c_bus[adap->hwadapnr];
 476         bus->active = true;
 477         bus->regs = i2c;
 478 }
 479
 480 /*
 481  * Poll the appropriate bit of the fifo status register until the interface is
 482  * ready to process the next byte or timeout expires.
 483  *
 484  * In addition to the FIFO status register this function also polls the
 485  * interrupt status register to be able to detect unexpected transaction
 486  * completion.
 487  *
 488  * When FIFO is ready to process the next byte, this function returns I2C_OK.
 489  * If in course of polling the INT_I2C assertion is detected, the function
 490  * returns I2C_NOK. If timeout happens before any of the above conditions is
 491  * met - the function returns I2C_NOK_TOUT;
 492
 493  * @param i2c: pointer to the appropriate i2c register bank.
 494  * @param rx_transfer: set to True if the receive transaction is in progress.
 495  * @return: as described above.
 496  */
 497 static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer)
 498 {
 499         u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL;
 500         int i = HSI2C_TIMEOUT_US;
 501
 502         while (readl(&i2c->usi_fifo_stat) & fifo_bit) {
 503                 if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) {
 504                         /*
 505                          * There is a chance that assertion of
 506                          * HSI2C_INT_I2C_EN and deassertion of
 507                          * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's
 508                          * give FIFO status priority and check it one more
 509                          * time before reporting interrupt. The interrupt will
 510                          * be reported next time this function is called.
 511                          */
 512                         if (rx_transfer &&
 513                             !(readl(&i2c->usi_fifo_stat) & fifo_bit))
 514                                 break;
 515                         return I2C_NOK;
 516                 }
 517                 if (!i--) {
 518                         debug("%s: FIFO polling timeout!\n", __func__);
 519                         return I2C_NOK_TOUT;
 520                 }
 521                 udelay(1);
 522         }
 523         return I2C_OK;
 524 }
 525
 526 /*
 527  * Preapre hsi2c transaction, either read or write.
 528  *
 529  * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of
 530  * the 5420 UM.
 531  *
 532  * @param i2c: pointer to the appropriate i2c register bank.
 533  * @param chip: slave address on the i2c bus (with read/write bit exlcuded)
 534  * @param len: number of bytes expected to be sent or received
 535  * @param rx_transfer: set to true for receive transactions
 536  * @param: issue_stop: set to true if i2c stop condition should be generated
 537  *         after this transaction.
 538  * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US,
 539  *          I2C_OK otherwise.
 540  */
 541 static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c,
 542                                      u8 chip,
 543                                      u16 len,
 544                                      bool rx_transfer,
 545                                      bool issue_stop)
 546 {
 547         u32 conf;
 548
 549         conf = len | HSI2C_MASTER_RUN;
 550
 551         if (issue_stop)
 552                 conf |= HSI2C_STOP_AFTER_TRANS;
 553
 554         /* Clear to enable Timeout */
 555         writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout);
 556
 557         /* Set slave address */
 558         writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
 559
 560         if (rx_transfer) {
 561                 /* i2c master, read transaction */
 562                 writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
 563                        &i2c->usi_ctl);
 564
 565                 /* read up to len bytes, stop after transaction is finished */
 566                 writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf);
 567         } else {
 568                 /* i2c master, write transaction */
 569                 writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
 570                        &i2c->usi_ctl);
 571
 572                 /* write up to len bytes, stop after transaction is finished */
 573                 writel(conf, &i2c->usi_auto_conf);
 574         }
 575
 576         /* Reset all pending interrupt status bits we care about, if any */
 577         writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat);
 578
 579         return I2C_OK;
 580 }
 581
 582 /*
 583  * Wait while i2c bus is settling down (mostly stop gets completed).
 584  */
 585 static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c)
 586 {
 587         int i = HSI2C_TIMEOUT_US;
 588
 589         while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) {
 590                 if (!i--) {
 591                         debug("%s: bus busy\n", __func__);
 592                         return I2C_NOK_TOUT;
 593                 }
 594                 udelay(1);
 595         }
 596         return I2C_OK;
 597 }
 598
 599 static int hsi2c_write(struct exynos5_hsi2c *i2c,
 600                        unsigned char chip,
 601                        unsigned char addr[],
 602                        unsigned char alen,
 603                        unsigned char data[],
 604                        unsigned short len,
 605                        bool issue_stop)
 606 {
 607         int i, rv = 0;
 608
 609         if (!(len + alen)) {
 610                 /* Writes of zero length not supported in auto mode. */
 611                 debug("%s: zero length writes not supported\n", __func__);
 612                 return I2C_NOK;
 613         }
 614
 615         rv = hsi2c_prepare_transaction
 616                 (i2c, chip, len + alen, false, issue_stop);
 617         if (rv != I2C_OK)
 618                 return rv;
 619
 620         /* Move address, if any, and the data, if any, into the FIFO. */
 621         for (i = 0; i < alen; i++) {
 622                 rv = hsi2c_poll_fifo(i2c, false);
 623                 if (rv != I2C_OK) {
 624                         debug("%s: address write failed\n", __func__);
 625                         goto write_error;
 626                 }
 627                 writel(addr[i], &i2c->usi_txdata);
 628         }
 629
 630         for (i = 0; i < len; i++) {
 631                 rv = hsi2c_poll_fifo(i2c, false);
 632                 if (rv != I2C_OK) {
 633                         debug("%s: data write failed\n", __func__);
 634                         goto write_error;
 635                 }
 636                 writel(data[i], &i2c->usi_txdata);
 637         }
 638
 639         rv = hsi2c_wait_for_trx(i2c);
 640
 641  write_error:
 642         if (issue_stop) {
 643                 int tmp_ret = hsi2c_wait_while_busy(i2c);
 644                 if (rv == I2C_OK)
 645                         rv = tmp_ret;
 646         }
 647
 648         writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
 649         return rv;
 650 }
 651
 652 static int hsi2c_read(struct exynos5_hsi2c *i2c,
 653                       unsigned char chip,
 654                       unsigned char addr[],
 655                       unsigned char alen,
 656                       unsigned char data[],
 657                       unsigned short len)
 658 {
 659         int i, rv, tmp_ret;
 660         bool drop_data = false;
 661
 662         if (!len) {
 663                 /* Reads of zero length not supported in auto mode. */
 664                 debug("%s: zero length read adjusted\n", __func__);
 665                 drop_data = true;
 666                 len = 1;
 667         }
 668
 669         if (alen) {
 670                 /* Internal register adress needs to be written first. */
 671                 rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false);
 672                 if (rv != I2C_OK)
 673                         return rv;
 674         }
 675
 676         rv = hsi2c_prepare_transaction(i2c, chip, len, true, true);
 677
 678         if (rv != I2C_OK)
 679                 return rv;
 680
 681         for (i = 0; i < len; i++) {
 682                 rv = hsi2c_poll_fifo(i2c, true);
 683                 if (rv != I2C_OK)
 684                         goto read_err;
 685                 if (drop_data)
 686                         continue;
 687                 data[i] = readl(&i2c->usi_rxdata);
 688         }
 689
 690         rv = hsi2c_wait_for_trx(i2c);
 691
 692  read_err:
 693         tmp_ret = hsi2c_wait_while_busy(i2c);
 694         if (rv == I2C_OK)
 695                 rv = tmp_ret;
 696
 697         writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
 698         return rv;
 699 }
 700
 701 static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
 702                                           unsigned int speed)
 703 {
 704         struct s3c24x0_i2c_bus *i2c_bus;
 705
 706         i2c_bus = get_bus(adap->hwadapnr);
 707         if (!i2c_bus)
 708                 return -1;
 709
 710         i2c_bus->clock_frequency = speed;
 711
 712         if (i2c_bus->is_highspeed) {
 713                 if (hsi2c_get_clk_details(i2c_bus))
 714                         return -1;
 715                 hsi2c_ch_init(i2c_bus);
 716         } else {
 717                 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
 718                             CONFIG_SYS_I2C_S3C24X0_SLAVE);
 719         }
 720
 721         return 0;
 722 }
 723
 724 /*
 725  * cmd_type is 0 for write, 1 for read.
 726  *
 727  * addr_len can take any value from 0-255, it is only limited
 728  * by the char, we could make it larger if needed. If it is
 729  * 0 we skip the address write cycle.
 730  */
 731 static int i2c_transfer(struct s3c24x0_i2c *i2c,
 732                         unsigned char cmd_type,
 733                         unsigned char chip,
 734                         unsigned char addr[],
 735                         unsigned char addr_len,
 736                         unsigned char data[],
 737                         unsigned short data_len)
 738 {
 739         int i = 0, result;
 740         ulong start_time = get_timer(0);
 741
 742         if (data == 0 || data_len == 0) {
 743                 /*Don't support data transfer of no length or to address 0 */
 744                 debug("i2c_transfer: bad call\n");
 745                 return I2C_NOK;
 746         }
 747
 748         while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
 749                 if (get_timer(start_time) > I2C_TIMEOUT_MS)
 750                         return I2C_NOK_TOUT;
 751         }
 752
 753         writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
 754
 755         /* Get the slave chip address going */
 756         writel(chip, &i2c->iicds);
 757         if ((cmd_type == I2C_WRITE) || (addr && addr_len))
 758                 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
 759                        &i2c->iicstat);
 760         else
 761                 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
 762                        &i2c->iicstat);
 763
 764         /* Wait for chip address to transmit. */
 765         result = WaitForXfer(i2c);
 766         if (result != I2C_OK)
 767                 goto bailout;
 768
 769         /* If register address needs to be transmitted - do it now. */
 770         if (addr && addr_len) {
 771                 while ((i < addr_len) && (result == I2C_OK)) {
 772                         writel(addr[i++], &i2c->iicds);
 773                         ReadWriteByte(i2c);
 774                         result = WaitForXfer(i2c);
 775                 }
 776                 i = 0;
 777                 if (result != I2C_OK)
 778                         goto bailout;
 779         }
 780
 781         switch (cmd_type) {
 782         case I2C_WRITE:
 783                 while ((i < data_len) && (result == I2C_OK)) {
 784                         writel(data[i++], &i2c->iicds);
 785                         ReadWriteByte(i2c);
 786                         result = WaitForXfer(i2c);
 787                 }
 788                 break;
 789
 790         case I2C_READ:
 791                 if (addr && addr_len) {
 792                         /*
 793                          * Register address has been sent, now send slave chip
 794                          * address again to start the actual read transaction.
 795                          */
 796                         writel(chip, &i2c->iicds);
 797
 798                         /* Generate a re-START. */
 799                         writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
 800                                 &i2c->iicstat);
 801                         ReadWriteByte(i2c);
 802                         result = WaitForXfer(i2c);
 803
 804                         if (result != I2C_OK)
 805                                 goto bailout;
 806                 }
 807
 808                 while ((i < data_len) && (result == I2C_OK)) {
 809                         /* disable ACK for final READ */
 810                         if (i == data_len - 1)
 811                                 writel(readl(&i2c->iiccon)
 812                                        & ~I2CCON_ACKGEN,
 813                                        &i2c->iiccon);
 814                         ReadWriteByte(i2c);
 815                         result = WaitForXfer(i2c);
 816                         data[i++] = readl(&i2c->iicds);
 817                 }
 818                 if (result == I2C_NACK)
 819                         result = I2C_OK; /* Normal terminated read. */
 820                 break;
 821
 822         default:
 823                 debug("i2c_transfer: bad call\n");
 824                 result = I2C_NOK;
 825                 break;
 826         }
 827
 828 bailout:
 829         /* Send STOP. */
 830         writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 831         ReadWriteByte(i2c);
 832
 833         return result;
 834 }
 835
 836 static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip)
 837 {
 838         struct s3c24x0_i2c_bus *i2c_bus;
 839         uchar buf[1];
 840         int ret;
 841
 842         i2c_bus = get_bus(adap->hwadapnr);
 843         if (!i2c_bus)
 844                 return -1;
 845         buf[0] = 0;
 846
 847         /*
 848          * What is needed is to send the chip address and verify that the
 849          * address was <ACK>ed (i.e. there was a chip at that address which
 850          * drove the data line low).
 851          */
 852         if (i2c_bus->is_highspeed) {
 853                 ret = hsi2c_read(i2c_bus->hsregs,
 854                                 chip, 0, 0, buf, 1);
 855         } else {
 856                 ret = i2c_transfer(i2c_bus->regs,
 857                                 I2C_READ, chip << 1, 0, 0, buf, 1);
 858         }
 859
 860         return ret != I2C_OK;
 861 }
 862
 863 static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 864                             int alen, uchar *buffer, int len)
 865 {
 866         struct s3c24x0_i2c_bus *i2c_bus;
 867         uchar xaddr[4];
 868         int ret;
 869
 870         if (alen > 4) {
 871                 debug("I2C read: addr len %d not supported\n", alen);
 872                 return 1;
 873         }
 874
 875         if (alen > 0) {
 876                 xaddr[0] = (addr >> 24) & 0xFF;
 877                 xaddr[1] = (addr >> 16) & 0xFF;
 878                 xaddr[2] = (addr >> 8) & 0xFF;
 879                 xaddr[3] = addr & 0xFF;
 880         }
 881
 882 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 883         /*
 884          * EEPROM chips that implement "address overflow" are ones
 885          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 886          * address and the extra bits end up in the "chip address"
 887          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 888          * four 256 byte chips.
 889          *
 890          * Note that we consider the length of the address field to
 891          * still be one byte because the extra address bits are
 892          * hidden in the chip address.
 893          */
 894         if (alen > 0)
 895                 chip |= ((addr >> (alen * 8)) &
 896                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 897 #endif
 898         i2c_bus = get_bus(adap->hwadapnr);
 899         if (!i2c_bus)
 900                 return -1;
 901
 902         if (i2c_bus->is_highspeed)
 903                 ret = hsi2c_read(i2c_bus->hsregs, chip, &xaddr[4 - alen],
 904                                  alen, buffer, len);
 905         else
 906                 ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1,
 907                                 &xaddr[4 - alen], alen, buffer, len);
 908
 909         if (ret) {
 910                 if (i2c_bus->is_highspeed)
 911                         exynos5_i2c_reset(i2c_bus);
 912                 debug("I2c read failed %d\n", ret);
 913                 return 1;
 914         }
 915         return 0;
 916 }
 917
 918 static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 919                          int alen, uchar *buffer, int len)
 920 {
 921         struct s3c24x0_i2c_bus *i2c_bus;
 922         uchar xaddr[4];
 923         int ret;
 924
 925         if (alen > 4) {
 926                 debug("I2C write: addr len %d not supported\n", alen);
 927                 return 1;
 928         }
 929
 930         if (alen > 0) {
 931                 xaddr[0] = (addr >> 24) & 0xFF;
 932                 xaddr[1] = (addr >> 16) & 0xFF;
 933                 xaddr[2] = (addr >> 8) & 0xFF;
 934                 xaddr[3] = addr & 0xFF;
 935         }
 936 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 937         /*
 938          * EEPROM chips that implement "address overflow" are ones
 939          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 940          * address and the extra bits end up in the "chip address"
 941          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 942          * four 256 byte chips.
 943          *
 944          * Note that we consider the length of the address field to
 945          * still be one byte because the extra address bits are
 946          * hidden in the chip address.
 947          */
 948         if (alen > 0)
 949                 chip |= ((addr >> (alen * 8)) &
 950                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 951 #endif
 952         i2c_bus = get_bus(adap->hwadapnr);
 953         if (!i2c_bus)
 954                 return -1;
 955
 956         if (i2c_bus->is_highspeed)
 957                 ret = hsi2c_write(i2c_bus->hsregs, chip, &xaddr[4 - alen],
 958                                   alen, buffer, len, true);
 959         else
 960                 ret = i2c_transfer(i2c_bus->regs, I2C_WRITE, chip << 1,
 961                                 &xaddr[4 - alen], alen, buffer, len);
 962
 963         if (ret != 0) {
 964                 if (i2c_bus->is_highspeed)
 965                         exynos5_i2c_reset(i2c_bus);
 966                 return 1;
 967         } else {
 968                 return 0;
 969         }
 970 }
 971
 972 #ifdef CONFIG_OF_CONTROL
 973 static void process_nodes(const void *blob, int node_list[], int count,
 974                          int is_highspeed)
 975 {
 976         struct s3c24x0_i2c_bus *bus;
 977         int i;
 978
 979         for (i = 0; i < count; i++) {
 980                 int node = node_list[i];
 981
 982                 if (node <= 0)
 983                         continue;
 984
 985                 bus = &i2c_bus[i];
 986                 bus->active = true;
 987                 bus->is_highspeed = is_highspeed;
 988
 989                 if (is_highspeed)
 990                         bus->hsregs = (struct exynos5_hsi2c *)
 991                                         fdtdec_get_addr(blob, node, "reg");
 992                 else
 993                         bus->regs = (struct s3c24x0_i2c *)
 994                                         fdtdec_get_addr(blob, node, "reg");
 995
 996                 bus->id = pinmux_decode_periph_id(blob, node);
 997                 bus->clock_frequency = fdtdec_get_int(blob, node,
 998                                                 "clock-frequency",
 999                                                 CONFIG_SYS_I2C_S3C24X0_SPEED);
1000                 bus->node = node;
1001                 bus->bus_num = i;
1002                 exynos_pinmux_config(bus->id, 0);
1003
1004                 /* Mark position as used */
1005                 node_list[i] = -1;
1006         }
1007 }
1008
1009 void board_i2c_init(const void *blob)
1010 {
1011         int node_list[CONFIG_MAX_I2C_NUM];
1012         int count;
1013
1014         /* First get the normal i2c ports */
1015         count = fdtdec_find_aliases_for_id(blob, "i2c",
1016                 COMPAT_SAMSUNG_S3C2440_I2C, node_list,
1017                 CONFIG_MAX_I2C_NUM);
1018         process_nodes(blob, node_list, count, 0);
1019
1020         /* Now look for high speed i2c ports */
1021         count = fdtdec_find_aliases_for_id(blob, "i2c",
1022                 COMPAT_SAMSUNG_EXYNOS5_I2C, node_list,
1023                 CONFIG_MAX_I2C_NUM);
1024         process_nodes(blob, node_list, count, 1);
1025
1026 }
1027
1028 int i2c_get_bus_num_fdt(int node)
1029 {
1030         int i;
1031
1032         for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) {
1033                 if (node == i2c_bus[i].node)
1034                         return i;
1035         }
1036
1037         debug("%s: Can't find any matched I2C bus\n", __func__);
1038         return -1;
1039 }
1040
1041 int i2c_reset_port_fdt(const void *blob, int node)
1042 {
1043         struct s3c24x0_i2c_bus *i2c_bus;
1044         int bus;
1045
1046         bus = i2c_get_bus_num_fdt(node);
1047         if (bus < 0) {
1048                 debug("could not get bus for node %d\n", node);
1049                 return -1;
1050         }
1051
1052         i2c_bus = get_bus(bus);
1053         if (!i2c_bus) {
1054                 debug("get_bus() failed for node node %d\n", node);
1055                 return -1;
1056         }
1057
1058         if (i2c_bus->is_highspeed) {
1059                 if (hsi2c_get_clk_details(i2c_bus))
1060                         return -1;
1061                 hsi2c_ch_init(i2c_bus);
1062         } else {
1063                 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
1064                             CONFIG_SYS_I2C_S3C24X0_SLAVE);
1065         }
1066
1067         return 0;
1068 }
1069 #endif
1070
1071 /*
1072  * Register s3c24x0 i2c adapters
1073  */
1074 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1075                          s3c24x0_i2c_read, s3c24x0_i2c_write,
1076                          s3c24x0_i2c_set_bus_speed,
1077                          CONFIG_SYS_I2C_S3C24X0_SPEED,
1078                          CONFIG_SYS_I2C_S3C24X0_SLAVE,
1079                          0)
1080 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_1, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1081                          s3c24x0_i2c_read, s3c24x0_i2c_write,
1082                          s3c24x0_i2c_set_bus_speed,
1083                          CONFIG_SYS_I2C_S3C24X0_SPEED,
1084                          CONFIG_SYS_I2C_S3C24X0_SLAVE,
1085                          1)
1086 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_2, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1087                          s3c24x0_i2c_read, s3c24x0_i2c_write,
1088                          s3c24x0_i2c_set_bus_speed,
1089                          CONFIG_SYS_I2C_S3C24X0_SPEED,
1090                          CONFIG_SYS_I2C_S3C24X0_SLAVE,
1091                          2)
1092 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_3, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1093                          s3c24x0_i2c_read, s3c24x0_i2c_write,
1094                          s3c24x0_i2c_set_bus_speed,
1095                          CONFIG_SYS_I2C_S3C24X0_SPEED,
1096                          CONFIG_SYS_I2C_S3C24X0_SLAVE,
1097                          3)
1098 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_4, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1099                          s3c24x0_i2c_read, s3c24x0_i2c_write,
1100                          s3c24x0_i2c_set_bus_speed,
1101                          CONFIG_SYS_I2C_S3C24X0_SPEED,
1102                          CONFIG_SYS_I2C_S3C24X0_SLAVE,
1103                          4)
1104 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_5, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1105                          s3c24x0_i2c_read, s3c24x0_i2c_write,
1106                          s3c24x0_i2c_set_bus_speed,
1107                          CONFIG_SYS_I2C_S3C24X0_SPEED,
1108                          CONFIG_SYS_I2C_S3C24X0_SLAVE,
1109                          5)
1110 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_6, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1111                          s3c24x0_i2c_read, s3c24x0_i2c_write,
1112                          s3c24x0_i2c_set_bus_speed,
1113                          CONFIG_SYS_I2C_S3C24X0_SPEED,
1114                          CONFIG_SYS_I2C_S3C24X0_SLAVE,
1115                          6)
1116 U_BOOT_I2C_ADAP_COMPLETE(s3c24x0_7, s3c24x0_i2c_init, s3c24x0_i2c_probe,
1117                          s3c24x0_i2c_read, s3c24x0_i2c_write,
1118                          s3c24x0_i2c_set_bus_speed,
1119                          CONFIG_SYS_I2C_S3C24X0_SPEED,
1120                          CONFIG_SYS_I2C_S3C24X0_SLAVE,
1121                          7)