3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5 * SPDX-License-Identifier: GPL-2.0+
8 /* This code should work for both the S3C2400 and the S3C2410
9 * as they seem to have the same I2C controller inside.
10 * The different address mapping is handled by the s3c24xx.h files below.
15 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
16 #include <asm/arch/clk.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/pinmux.h>
20 #include <asm/arch/s3c24x0_cpu.h>
24 #include "s3c24x0_i2c.h"
26 #ifdef CONFIG_HARD_I2C
34 #define I2C_NOK_LA 3 /* Lost arbitration */
35 #define I2C_NOK_TOUT 4 /* time out */
37 #define I2CSTAT_BSY 0x20 /* Busy bit */
38 #define I2CSTAT_NACK 0x01 /* Nack bit */
39 #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
40 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */
41 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
42 #define I2C_MODE_MR 0x80 /* Master Receive Mode */
43 #define I2C_START_STOP 0x20 /* START / STOP */
44 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
46 #define I2C_TIMEOUT_MS 1000 /* 1 second */
50 * For SPL boot some boards need i2c before SDRAM is initialised so force
51 * variables to live in SRAM
53 static unsigned int g_current_bus __attribute__((section(".data")));
54 #ifdef CONFIG_OF_CONTROL
55 static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
56 __attribute__((section(".data")));
59 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
60 static int GetI2CSDA(void)
62 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
65 return (readl(&gpio->gpedat) & 0x8000) >> 15;
68 return (readl(&gpio->pgdat) & 0x0020) >> 5;
72 static void SetI2CSCL(int x)
74 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
77 writel((readl(&gpio->gpedat) & ~0x4000) |
78 (x & 1) << 14, &gpio->gpedat);
81 writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
87 * Wait til the byte transfer is completed.
89 * @param i2c- pointer to the appropriate i2c register bank.
90 * @return I2C_OK, if transmission was ACKED
91 * I2C_NACK, if transmission was NACKED
92 * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
95 static int WaitForXfer(struct s3c24x0_i2c *i2c)
97 ulong start_time = get_timer(0);
100 if (readl(&i2c->iiccon) & I2CCON_IRPND)
101 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
103 } while (get_timer(start_time) < I2C_TIMEOUT_MS);
108 static void ReadWriteByte(struct s3c24x0_i2c *i2c)
110 writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
113 static struct s3c24x0_i2c *get_base_i2c(void)
115 #ifdef CONFIG_EXYNOS4
116 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
117 + (EXYNOS4_I2C_SPACING
120 #elif defined CONFIG_EXYNOS5
121 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
122 + (EXYNOS5_I2C_SPACING
126 return s3c24x0_get_base_i2c();
130 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
132 ulong freq, pres = 16, div;
133 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
134 freq = get_i2c_clk();
138 /* calculate prescaler and divisor values */
139 if ((freq / pres / (16 + 1)) > speed)
140 /* set prescaler to 512 */
144 while ((freq / pres / (div + 1)) > speed)
147 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
148 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
150 /* init to SLAVE REVEIVE and set slaveaddr */
151 writel(0, &i2c->iicstat);
152 writel(slaveadd, &i2c->iicadd);
153 /* program Master Transmit (and implicit STOP) */
154 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
158 * MULTI BUS I2C support
161 #ifdef CONFIG_I2C_MULTI_BUS
162 int i2c_set_bus_num(unsigned int bus)
164 struct s3c24x0_i2c *i2c;
166 i2c_bus = get_bus(bus);
172 i2c = get_base_i2c();
173 i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
178 unsigned int i2c_get_bus_num(void)
180 return g_current_bus;
184 void i2c_init(int speed, int slaveadd)
187 struct s3c24x0_i2c *i2c;
188 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
189 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
191 ulong start_time = get_timer(0);
193 /* By default i2c channel 0 is the current bus */
195 i2c = get_base_i2c();
198 * In case the previous transfer is still going, wait to give it a
201 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
202 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
203 printf("%s: I2C bus busy for %p\n", __func__,
209 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
210 if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
211 #ifdef CONFIG_S3C2410
212 ulong old_gpecon = readl(&gpio->gpecon);
214 #ifdef CONFIG_S3C2400
215 ulong old_gpecon = readl(&gpio->pgcon);
217 /* bus still busy probably by (most) previously interrupted
220 #ifdef CONFIG_S3C2410
221 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
222 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
225 #ifdef CONFIG_S3C2400
226 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
227 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
231 /* toggle I2CSCL until bus idle */
235 while ((i > 0) && (GetI2CSDA() != 1)) {
245 /* restore pin functions */
246 #ifdef CONFIG_S3C2410
247 writel(old_gpecon, &gpio->gpecon);
249 #ifdef CONFIG_S3C2400
250 writel(old_gpecon, &gpio->pgcon);
253 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
254 i2c_ch_init(i2c, speed, slaveadd);
258 * cmd_type is 0 for write, 1 for read.
260 * addr_len can take any value from 0-255, it is only limited
261 * by the char, we could make it larger if needed. If it is
262 * 0 we skip the address write cycle.
264 static int i2c_transfer(struct s3c24x0_i2c *i2c,
265 unsigned char cmd_type,
267 unsigned char addr[],
268 unsigned char addr_len,
269 unsigned char data[],
270 unsigned short data_len)
273 ulong start_time = get_timer(0);
275 if (data == 0 || data_len == 0) {
276 /*Don't support data transfer of no length or to address 0 */
277 debug("i2c_transfer: bad call\n");
281 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
282 if (get_timer(start_time) > I2C_TIMEOUT_MS)
286 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
288 /* Get the slave chip address going */
289 writel(chip, &i2c->iicds);
290 if ((cmd_type == I2C_WRITE) || (addr && addr_len))
291 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
294 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
297 /* Wait for chip address to transmit. */
298 result = WaitForXfer(i2c);
299 if (result != I2C_OK)
302 /* If register address needs to be transmitted - do it now. */
303 if (addr && addr_len) {
304 while ((i < addr_len) && (result == I2C_OK)) {
305 writel(addr[i++], &i2c->iicds);
307 result = WaitForXfer(i2c);
310 if (result != I2C_OK)
316 while ((i < data_len) && (result == I2C_OK)) {
317 writel(data[i++], &i2c->iicds);
319 result = WaitForXfer(i2c);
324 if (addr && addr_len) {
326 * Register address has been sent, now send slave chip
327 * address again to start the actual read transaction.
329 writel(chip, &i2c->iicds);
331 /* Generate a re-START. */
332 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
335 result = WaitForXfer(i2c);
337 if (result != I2C_OK)
341 while ((i < data_len) && (result == I2C_OK)) {
342 /* disable ACK for final READ */
343 if (i == data_len - 1)
344 writel(readl(&i2c->iiccon)
348 result = WaitForXfer(i2c);
349 data[i++] = readl(&i2c->iicds);
351 if (result == I2C_NACK)
352 result = I2C_OK; /* Normal terminated read. */
356 debug("i2c_transfer: bad call\n");
363 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
369 int i2c_probe(uchar chip)
371 struct s3c24x0_i2c *i2c;
374 i2c = get_base_i2c();
378 * What is needed is to send the chip address and verify that the
379 * address was <ACK>ed (i.e. there was a chip at that address which
380 * drove the data line low).
382 return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
385 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
387 struct s3c24x0_i2c *i2c;
392 debug("I2C read: addr len %d not supported\n", alen);
397 xaddr[0] = (addr >> 24) & 0xFF;
398 xaddr[1] = (addr >> 16) & 0xFF;
399 xaddr[2] = (addr >> 8) & 0xFF;
400 xaddr[3] = addr & 0xFF;
403 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
405 * EEPROM chips that implement "address overflow" are ones
406 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
407 * address and the extra bits end up in the "chip address"
408 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
409 * four 256 byte chips.
411 * Note that we consider the length of the address field to
412 * still be one byte because the extra address bits are
413 * hidden in the chip address.
416 chip |= ((addr >> (alen * 8)) &
417 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
419 i2c = get_base_i2c();
420 ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen,
423 debug("I2c read: failed %d\n", ret);
429 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
431 struct s3c24x0_i2c *i2c;
435 debug("I2C write: addr len %d not supported\n", alen);
440 xaddr[0] = (addr >> 24) & 0xFF;
441 xaddr[1] = (addr >> 16) & 0xFF;
442 xaddr[2] = (addr >> 8) & 0xFF;
443 xaddr[3] = addr & 0xFF;
445 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
447 * EEPROM chips that implement "address overflow" are ones
448 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
449 * address and the extra bits end up in the "chip address"
450 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
451 * four 256 byte chips.
453 * Note that we consider the length of the address field to
454 * still be one byte because the extra address bits are
455 * hidden in the chip address.
458 chip |= ((addr >> (alen * 8)) &
459 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
461 i2c = get_base_i2c();
463 (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
467 #ifdef CONFIG_OF_CONTROL
468 void board_i2c_init(const void *blob)
471 int node_list[CONFIG_MAX_I2C_NUM];
474 count = fdtdec_find_aliases_for_id(blob, "i2c",
475 COMPAT_SAMSUNG_S3C2440_I2C, node_list,
478 for (i = 0; i < count; i++) {
479 struct s3c24x0_i2c_bus *bus;
480 int node = node_list[i];
486 bus->regs = (struct s3c24x0_i2c *)
487 fdtdec_get_addr(blob, node, "reg");
488 bus->id = pinmux_decode_periph_id(blob, node);
491 exynos_pinmux_config(bus->id, 0);
496 * Get a pointer to the given bus index
498 * @bus_idx: Bus index to look up
499 * @return pointer to bus, or NULL if invalid or not available
501 static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
503 if (bus_idx < ARRAY_SIZE(i2c_bus)) {
504 struct s3c24x0_i2c_bus *bus;
506 bus = &i2c_bus[bus_idx];
511 debug("Undefined bus: %d\n", bus_idx);
515 int i2c_get_bus_num_fdt(int node)
519 for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) {
520 if (node == i2c_bus[i].node)
524 debug("%s: Can't find any matched I2C bus\n", __func__);
528 int i2c_reset_port_fdt(const void *blob, int node)
530 struct s3c24x0_i2c_bus *i2c;
533 bus = i2c_get_bus_num_fdt(node);
535 debug("could not get bus for node %d\n", node);
541 debug("get_bus() failed for node node %d\n", node);
545 i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
551 #endif /* CONFIG_HARD_I2C */