2 * drivers/i2c/rcar_i2c.c
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 * SPDX-License-Identifier: GPL-2.0
14 DECLARE_GLOBAL_DATA_PTR;
33 #define MCR_MDBS 0x80 /* non-fifo mode switch */
34 #define MCR_FSCL 0x40 /* override SCL pin */
35 #define MCR_FSDA 0x20 /* override SDA pin */
36 #define MCR_OBPC 0x10 /* override pins */
37 #define MCR_MIE 0x08 /* master if enable */
39 #define MCR_FSB 0x02 /* force stop bit */
40 #define MCR_ESG 0x01 /* en startbit gen. */
43 #define MSR_MNR 0x40 /* nack received */
44 #define MSR_MAL 0x20 /* arbitration lost */
45 #define MSR_MST 0x10 /* sent a stop */
49 #define MSR_MAT 0x01 /* slave addr xfer done */
51 static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = {
52 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE,
53 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE,
54 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE,
55 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE,
58 static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr)
60 /* set slave address */
61 writel(chip << 1, &dev->icmar);
62 /* set register address */
63 writel(addr, &dev->icrxdtxd);
65 writel(0, &dev->icmsr);
66 /* start master send */
67 writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
69 while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE))
70 != (MSR_MAT | MSR_MDE))
74 writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
76 writel(~(MSR_MAT | MSR_MDE), &dev->icmsr);
78 while (!(readl(&dev->icmsr) & MSR_MDE))
82 static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev)
84 while (!(readl(&dev->icmsr) & MSR_MST))
87 writel(0, &dev->icmcr);
91 rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size)
93 rcar_i2c_raw_rw_common(dev, chip, addr);
96 writel(*val, &dev->icrxdtxd);
98 writel(~MSR_MDE, &dev->icmsr);
100 while (!(readl(&dev->icmsr) & MSR_MDE))
103 /* set stop condition */
104 writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
106 writel(~MSR_MDE, &dev->icmsr);
108 rcar_i2c_raw_rw_finish(dev);
114 rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr)
118 rcar_i2c_raw_rw_common(dev, chip, addr);
120 /* set slave address, receive */
121 writel((chip << 1) | 1, &dev->icmar);
122 /* start master receive */
123 writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
125 while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE))
126 != (MSR_MAT | MSR_MDE))
130 writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
131 /* prepare stop condition */
132 writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
134 writel(~(MSR_MAT | MSR_MDR), &dev->icmsr);
136 while (!(readl(&dev->icmsr) & MSR_MDR))
139 /* get receive data */
140 ret = (u8)readl(&dev->icrxdtxd);
142 writel(~MSR_MDR, &dev->icmsr);
144 rcar_i2c_raw_rw_finish(dev);
150 * SCL = iicck / (20 + SCGD * 8 + F[(ticf + tr + intd) * iicck])
151 * iicck : I2C internal clock < 20 MHz
152 * ticf : I2C SCL falling time: 35 ns
153 * tr : I2C SCL rising time: 200 ns
154 * intd : LSI internal delay: I2C0: 50 ns I2C1-3: 5
155 * F[n] : n rounded up to an integer
157 static u32 rcar_clock_gen(int i2c_no, u32 bus_speed)
159 u32 iicck, f, scl, scgd;
162 int bit = 0, cdf_width = 3;
163 for (bit = 0; bit < (1 << cdf_width); bit++) {
164 iicck = CONFIG_HP_CLK_FREQ / (1 + bit);
165 if (iicck < 20000000)
169 if (bit > (1 << cdf_width)) {
170 puts("rcar-i2c: Can not get CDF\n");
177 f = (35 + 200 + intd) * (iicck / 1000000000);
179 for (scgd = 0; scgd < 0x40; scgd++) {
180 scl = iicck / (20 + (scgd * 8) + f);
181 if (scl <= bus_speed)
186 puts("rcar-i2c: Can not get SDGB\n");
190 debug("%s: scl: %d\n", __func__, scl);
191 debug("%s: bit %x\n", __func__, bit);
192 debug("%s: scgd %x\n", __func__, scgd);
193 debug("%s: iccr %x\n", __func__, (scgd << (cdf_width) | bit));
195 return scgd << (cdf_width) | bit;
199 rcar_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
201 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
204 /* No i2c support prior to relocation */
205 if (!(gd->flags & GD_FLG_RELOC))
210 * slave mode is not used on this driver
212 writel(0, &dev->icsier);
213 writel(0, &dev->icsar);
214 writel(0, &dev->icscr);
215 writel(0, &dev->icssr);
217 /* reset master mode */
218 writel(0, &dev->icmier);
219 writel(0, &dev->icmcr);
220 writel(0, &dev->icmsr);
221 writel(0, &dev->icmar);
223 icccr = rcar_clock_gen(adap->hwadapnr, adap->speed);
225 puts("I2C: Init failed\n");
227 writel(icccr, &dev->icccr);
230 static int rcar_i2c_read(struct i2c_adapter *adap, uint8_t chip,
231 uint addr, int alen, u8 *data, int len)
233 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
236 for (i = 0; i < len; i++)
237 data[i] = rcar_i2c_raw_read(dev, chip, addr + i);
242 static int rcar_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
243 int alen, u8 *data, int len)
245 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
246 return rcar_i2c_raw_write(dev, chip, addr, data, len);
250 rcar_i2c_probe(struct i2c_adapter *adap, u8 dev)
252 return rcar_i2c_read(adap, dev, 0, 0, NULL, 0);
255 static unsigned int rcar_i2c_set_bus_speed(struct i2c_adapter *adap,
258 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
262 rcar_i2c_raw_rw_finish(dev);
264 icccr = rcar_clock_gen(adap->hwadapnr, speed);
266 puts("I2C: Init failed\n");
269 writel(icccr, &dev->icccr);
275 * Register RCAR i2c adapters
277 U_BOOT_I2C_ADAP_COMPLETE(rcar_0, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
278 rcar_i2c_write, rcar_i2c_set_bus_speed,
279 CONFIG_SYS_RCAR_I2C0_SPEED, 0, 0)
280 U_BOOT_I2C_ADAP_COMPLETE(rcar_1, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
281 rcar_i2c_write, rcar_i2c_set_bus_speed,
282 CONFIG_SYS_RCAR_I2C1_SPEED, 0, 1)
283 U_BOOT_I2C_ADAP_COMPLETE(rcar_2, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
284 rcar_i2c_write, rcar_i2c_set_bus_speed,
285 CONFIG_SYS_RCAR_I2C2_SPEED, 0, 2)
286 U_BOOT_I2C_ADAP_COMPLETE(rcar_3, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
287 rcar_i2c_write, rcar_i2c_set_bus_speed,
288 CONFIG_SYS_RCAR_I2C3_SPEED, 0, 3)